201034132 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電子元件封裝體及其製法，且 特別是有關於以一種由液態固化的材料層作為上封裝層 及/或具有穿矽通孔（TSV)之電子元件封裝體。 【先前技術】 光感測元件或發光元件等光電元件在擷取影像或照 Φ 明的應用中扮演著重要的角色，這些光電元件均已廣泛 地應用於例如是數位相機（digital camera)、數位攝錄像機 (digital video recorder)、手機（mobile phone)、太陽能電 池、螢幕、照明設備等的消費電子元件和攜帶型電子元 件中。隨著上述各種電子元件愈來愈輕巧化，使得光電 元件封裝體的尺寸也愈來愈縮小化。 傳統的半導體封裝主要是將半導體晶片封裝於一不 透明的電子元件封裝體中’以避免半導體晶片受到外界 ❿的污染且保護半導體晶片不受外界撞擊的影響。反之， 光電元件（例如CMOS影像感應器或發光二極體元件）必 須封裝於具有至少一透明基板（如玻璃基板）作為上封穿 層的電子元件封裝體中以接受外界的光線或輸出光線： 通常所採取的封裝方式是將透明基底整面塗以黏著劑而 接合至具有光感測元件或發光元件之晶圓上而完成封 裝。然而，黏著劑可能會造成光線折射而影響光線的接 收或輸出。 為了避免黏著劑影響光線的接收或輸出，目前已發 9002-A33562TWF/jychen 3 201034132 ^ 展出一種利用圍堰結構（dam)撐起透明基板並圍出空穴 (cavity)的技術。在此技術中，圍堰結構取代整面塗以黏 著劑而將透明基板固定於光電元件上（僅於圍堰結構塗上 黏著劑），光電元件對於光線之接收或輸出係透過所圍出 的空穴與透明基板，不需經由透光率不佳的黏著劑，具 較佳的光線接收與輸出。然而，圍堰結構之結構強度較 差，容易於接面處（例如與透明基板的接合處）發生裂痕 (crack)、脫層（delaminate)、彎曲（bending)等現象。此外， ®所使用之透明基板一般為玻璃基板，除了價格不菲，亦 增加封裝體的重量。 此外，隨著半導體製程技術的不斷進步，可於更小 的晶片中形成更多的半導體元件。除了使晶片的效能更 為提升外，還能節省晶圓面積而降低成本。然而，隨著 晶片尺寸縮小化與元件密度之增加，其輸出/輸入連接 (I/O)之數目與密度亦增加，因而造成封裝上的困難。 因此，業界亟需一種新穎的封裝技術及結構以改善 ⑩光電元件之封裝。 【發明内容】 本發明實施例提供一種電子元件封裝體，包括一具 有電子元件之基底，其中此基底具有第一表面與相反之 第二表面；以及一上封裝層，直接液態固化形成於第一 表面上，且上封裝層與第一表面之間不含黏著劑，其中 由液態固化的上封裝層具有平坦的上表面，且由液態固 化的上封裝層透光率大於90%。 9002-A33562TWF/jychen 4 201034132 本發明實施例另提供一種形成電子元件封裝體的方 法，包括提供一具有電子元件之基底，此基底具有第一 表面與相反之第二表面；以及直接於第一表面上液態固 化形成一上封裝層，上封裝層與第一表面之間不含黏著 劑，其中由液態固化的上封裝層具有大抵平坦的上表 面，且由液態固化的上封裝層之透光率約大於9〇% :其 中，由液態固化的上封裝層之形成包括：將—液態材料 直接覆蓋於第一表面上；以及將液態材料固化以形成上 Ο 封裝層。 、本發明實施例又提供一種電子元件封裝體的形成方 法，包括提供一承載基底，具有一上表面及一相反之下 表面；於承載基底之該上表面形成至少一凹槽；於凹槽 中"又置具有導電電極之晶# ’晶片並由一上封裝層所 覆蓋；於承載基底之凹槽中形成—填充層，填充層圍繞 上述晶片；自下表面薄化承载基底至一既定深度；於晶 片内或承載基底内形成至少—穿孔；以及於穿孔之侧壁 上形成一導，層，且導電層與導電電極形成電性接觸。 本發明實施例又提供一種電子元件封裝體，包括一 承載基底，具有至少—開口，此開口係、自承載基底之上 表面向下延伸；一填充層，位於開口中；一晶片，位於 開口中’且被填充層圍繞，此晶片具有一導電電極；一 上封裝層，覆蓋上述晶片；至少—穿孔，位於晶片内或 承載基底内；以及一導電層，位於穿孔之侧壁上，且導 電層與導電電極形成電性接觸。 為讓本發明之上述和其他目的、特徵、和優點能更 9002-A33562TWF/jychen „ 201034132 明顯易懂，下文特舉出較佳實施例，並配合所附圖式， 作詳細說明如下： 【實施方式】 本發明之一實施例係提供一種具有以由液態固化的 材料層為上封裝層之電子元件封裝體，利用將液態材料 固化以形成透明的上封裝層。本發明之另一實施例還提 供具有穿矽通孔（TSV)之封裝結構，利用穿矽通孔與線路 Φ 重佈層（RDL)形成晶片與封裝結構外部之導電通路。本發 明實施例之各階段製程將以圖式表示。在本發明實施例 之圖式與敛述中，相似的兀件將以相似的標被>標不。 第1A-1D圖顯示本發明實施例之電子元件封裝體的 一系列製程剖面圖。如第1A圖所示，首先提供一包含電 子元件之基底100,其具有第一表面102與一相反之第二 表面104。基底100可為矽基底、半導體基底、化合物半 導體基底、半導體晶圓、藍寶石基底、或前述之組合。 φ 本發明實施例之電子元件封裝體包括晶圓級封裝，主要 係指在晶圓階段完成封裝步驟後，再予以切割成獨立的 封裝體。然而，在一特定實施例中，例如將已分離的半 導體晶片重新分佈在一承載晶圓上，再進行封裝製程， 亦可稱之為晶圓級封裝製程。上述晶圓級封裝製程亦適 用於藉堆疊（stack)方式安排具有積體電路之多片晶圓，以 形成多層積體電路（multi-layer integrated circuit device) 之封裝體。 . 在一實施例中，基底100中具有於第一表面102露 9002-A33562T WF/jychen 6 201034132 出之電子元件106，其可為各種光電元件。例如，電子元 件106可為光感測元件、太陽能電池、或發光元件等。 電子元件 106亦可為微機電系統（micro electro mechanical system, MEMS)、微流體系統（micro fluidic systems)、或利用熱、光線及壓力等物理變化量來測量的 物理感測器（physical sensor)、射頻元件（RF circuit)、加 速計（accelerators)、陀螺儀（gyroscopes)、微制動器（micro actuators)、表面聲波元件、壓力感測器（pressure ❹ sensors)、或噴墨頭（ink printer heads)等。為了保護電子 元件106免於受到外界的污染或傷害，需於其上形成透 明的上封裝層，以提供保護並使光線能順利地進入與輸 出。 接著，進行本發明實施例之一特徵步驟，直接於第 一表面102上液態固化形成一材料層，其具有大抵平坦 的上表面，且其透光率約大於90〇/〇。由液態固化的材料 層可作為本發明實施例之電子元件封裝體的上封裝層， ❿可取代習知的破璃基板、黏著劑、或圍堰結構。在一實 施例中，上封裝層與第一表面102之間不含額外的黏著 劑。 请參照第1B -1C圖，其顯示本發明實施例中之由液 態固化的上封裝層108的形成過程。如第1B圖所示，首 先將具流動性的液態材料10 8 a直接塗佈於基底1 〇 〇的第 一表面102上’利用液態材料108a本身的披覆性形成大 抵平坦的塗膜。液態材料108a可以各種濕式塗佈法直接 塗佈於第一表面102上，例如刮刀塗佈（bar c〇ating)、旋 9002-A33562TWF/jychen 7 201034132 轉塗佈（spin coating)、淋幕塗佈（curtain coating)、或噴塗 (spray coating)等。 液態材料108a包括固化後為透明的高分子材料，較 佳為熱固性高分子材料，可使固化後之上封裝層108具 有足夠的硬度（例如大於約諾氏(Rockwell) 100度）與耐熱 性。適合的液態材料108a例如包括（但不限於）齡搭環氧 樹脂，如 CAS 編號為 28906-96-9 之 Novolac phenol epoxy resin。在其他實施例中，可將酚醛環氧樹脂與例如丙位 丁内醋（Gamma Butyrolactone，CAS No. 96-48-0)混合以 作為液態材料108a。或者，亦可進一步添加其他的添加 劑，例如三芳基硫六氟*録酸鹽（triarylsulfonium hexafluoroantimonate salt, CAS No. 109037-75-4)或/及碳 酸丙晞酉旨(propylene carbonate，CAS No. 108-32-7)等。 在一實施例中，可將適合用作液態材料108a之高分 子加熱至約大於其玻璃轉換溫度而使具有流動性，接著 將具流動性的液態材料10 8 a塗佈至第一表面102上。在 ❿一實施例中，可利用液態材料l〇8a本身的披覆性形成大 抵平坦的塗膜。此外，亦可將基底100放置在可旋轉平 台上，利用類似旋轉塗佈的方式，使液態材料l〇8a均勾 地覆蓋於第一表面102上，並具有大抵平坦的上表面。 由於高分子材質即使處於略高於玻璃轉換溫度下，其仍 具有一定的黏度，因而不致於完全從第一表面上流失。 然亦可於基底100之第一表面102之邊緣上形成阻擋結 構（未顯示）以避免液態材料108a於固化前流失。或者， 阻擋結構（未顯示）亦可形成在放置基底1〇〇的平台上，用 9002-A33562TWF/jychen 8 201034132 ' 以圍住基底100。此外，液態材料l〇8a中亦可加入適當 的溶劑，以調控其塗佈性質。 接著，例如可於液態材料108a上方照射紫外光10 而使液態材料l〇8a產生交聯而固化形成上封裝層108(如 第1C圖所示）。經固化後之上封裝層108亦可保有大抵 平坦之上表面。此外，在一實施例中，由液態固化的上 封裝層108之厚度大於約ΙΟμπι，較佳為約Ιμπι至5μπι 之間。此外，以上述方法製成之上封裝層固化後由於其 ❿ 熱膨率較小，因此可以確保電子元件封裝體的穩定性。 在上述實施例中，上封裝層108具有大抵平坦的上 表面，此處的大抵平坦係指上封裝層108表面最高處與 最低處之高低差很小，而不影響光線之輸入或輸出。例 如，在一實施例中，上封裝層108表面最高處與最低處 之高低差小於約3 μιη，較佳者，其高低差小於約1 μιη。 然應注意的是，隨著所傳送光線波長的不同或封裝體之 尺寸與種類不同，上封裝層108表面之高低差可能會有 © 差異，不限於前述之高低差範圍。由於由液態固化的上 封裝層108包括選用透明的高分子材料且又具大抵平坦 的上表面，電子元件106可透過透明的由液態固化的上 封裝層108接收或輸出光線，而不致產生折射或散射等 問題。 此外，可於由液態固化的上封裝層108中加入其他 添加劑。例如，可加入硬化劑（hardener)等，例如可直接 加在液態材料10 8 a中。再者，亦可於由液態固化的上封 裝層108中添加螢光材料（例如螢光粉），可用以調變輸出 9002-A33562TWF/jychen 9 201034132 * 或輸入光線的波長。螢光材料除了加入上封裝層108中， 亦可加在上封裝層108上’例如可於上封裝層上形 成螢光粉層。此外’其餘各種光學元件亦可形成在電子 元件106上或由液態固化的上封裝層ι〇8上，以符合各 種需求。例如’可視情況設置微透鏡陣列結構(mier〇lens array)、濾光片、抗反射層、偏光唭、分色膜（dichr〇ic filter)、光栅（optical grating)、光波導（〇ptical wave guide) 等於電子元件106上。 ❹ 請接著參照第1D圖’可以各種習知技術於基底1〇〇 之第二表面104上形成導電結構114，例如冬導電凸塊。 導電結構114與電子元件1〇6之間可設置有各種導電通 路（未顯不）’其與基底1〇〇之間可更包括絕緣層11〇及防 銲層112。在一實施例中，以導電凸塊作為導電結構114， 可將防銲層112圖案化以形成終端接觸墊開口於導電通 路（未顯示）的表面上，接著藉由圖案化的光阻層進行銲料 電鍍或是藉由網版印刷塗佈銲料而填入終端接觸墊開口 ®中，最後去除種晶層或光阻層以及進行迴銲形成銲球， 完成導電凸塊製程。電性連接至電子元件1〇6的導電結 構114’可作為電子元件1〇6與電子元件封裝體之外部電 路間的訊號溝通橋樑。其中，絕緣層11〇之材質可為環 氧樹脂、防銲材料、或其他適合之絕緣物質，例如無機 材=之氧化矽層、氮化矽層、氮氧化矽層、金屬氧化物、 或刚述之組合；或亦可為有機高分子材料之聚醢亞胺樹 月曰（polyimide)、笨環丁稀（butylcycl〇butene, 道氏化 子么司）、聚對二曱苯（parylene)、萘聚合物 9002-A33562TWF/jychen ^ 201034132 (polynaphthalenes) ' l 碳化物（fluorocarbons)、丙烯酸西旨 (acrylates)等。絕緣層110的形成方式可包含塗佈方式， 例如旋轉塗佈（spin coating)、喷塗（spray coating)、或淋 幕塗佈（curtain coating) ’或其他適合之沈積方式，例如， 液相沈積、物理氣相沈積、化學氣相沈積、低壓化學氣 相沈積、電漿增強式化學氣相沈積、快速熱化學氣相沈 積、或常壓化學氣相沈積等製程。 前述實施例，係將具流動性之液態材料l〇8a直接塗 ❹佈至第一表面上，然本發明實施例之形成方式不限 於此。第2A-2C圖顯示本發明另一實施例之電子元件封 裝體的一系列製程剖面圖。 如第2Α圖所示，將固態的粒狀材料丨〇8b舖於第一 表面102上。接著，如第2B圖所示，於粒狀材料1〇扑 上A?、射紅外光20以加熱粒狀材料1〇8b。當受熱後的粒狀 材料108b溫度高於其玻璃轉換溫度時，會轉變為且流動 性之液態材料108c(如第2B圖所示）。接著，可類似於第 ❿1B圖所述之實施例，使具流動性之液態材料i 〇 8 c自然流 動或透過旋轉基底100而使具有大抵平坦之上表面（如第 2C圖所示）。在一實施例中，將第2B圖中所示之結構放 置於可旋轉平台（未顯示）上並旋轉之，此時可同步照射紅 外光20。透過調整可旋轉平台之轉速及紅外光2〇之波長 與強度，可調控液態材料108c之表面型態’使具有大抵 平坦之上表面（如第2C圖）。例如，隨著液態材料1〇8c 之上表面漸漸平坦化時，可逐漸減小紅外光2〇之強度及 /或可旋轉平台之轉速’使液態材料1〇8c之流動性逐漸減 9002-A33562TWF/jychen 11 201034132 低而定形。最後，如第2C圖所示，可以紫外光10照射 液態材料108c，使固化為如第1C圖所示之由液態固化的 上封裝層108,以作為本發明實施例之電子元件封裝體的 上封裝層。同樣地，在其他實施例中，可透過對溫度的 控制來調控液態材料之流動性，以獲得具大抵平坦上表 面且透明之上封裝層。之後的製程同第1D圖所示，可進 行導電結構之形成，在此不予贅述。 本發明實施例具有許多優點，例如第一表面1 〇2上 ❹或由液態固化的上封裝層1〇8上不具有玻璃基板，而以 由液態固化的上封裝層1〇8取代玻璃基板，可有效避免 習知技術中’黏著劑對透光率之影響，並可避免強度較 弱之圍堰結構所造成可靠度上的疑慮。本發明一實施例 中，不需要於第一表面1〇2或由液態固化的上封裝層1〇8 上δ又置玻璃基板之製程，除了大幅減少成本外，還能節 省許多製程時間。在一些實施例中，採用透明的熱固性 高分子作為上封裝層1〇8，可具有較高的耐熱性，使上封 _裝層1〇8即使在較高的操作溫度下，仍能維持透明且大 抵平坦。此外，由液態固化的上封裝層1〇8之重量較玻 璃基板輕許多，更適於各種攜帶式電子產品之應用。 上述液態固化的材料層或上封裝層可適用於各種封 裝結構，為方便說明起見，以下係以具有穿矽通孔V 之封裝結構為例，但其不應以此為限。 請接著參照目，其顯*本發明實施 具有穿石夕通孔(TSV)之封裝結構的一系列製程剖_。首 先，如第3A圖所示，提供承载基底3〇〇，具有上表面3⑽ 9002-A33562TWF/jychen 12 201034132 及相反之下表面304。承載基底300可包括矽基底、半導 體基底、化合物半導體基底、半導體晶圓、藍寶石基底、 或前述之組合。 接著，於承載基底300之上表面302形成至少一凹 槽306。應注意的是，在一較佳實施例中，承載基底300 較佳選用矽晶圓，且較佳形成複數個凹槽306。可於晶圓 中的數個凹槽放置數個晶片，再經過後續的封裝與切割 製程後，獲得數個電子元件封裝體。凹槽306可例如以 ❹ 微影及蝕刻製程形成。 請接著參照第3B圖，將具有導電電極之晶片308設 置於凹槽306中，例如可透過（但不限於）黏著層314而將 晶片308固定於凹槽306中。在此實施例中，晶片308 具有導電電極310,並由上封裝層312所覆蓋，其中上封 裝層312位於導電電極310之上。導電電極310可作為 晶片308中之電子元件與封裝體之間的導電通路，例如 導電電極310可由半導體晶片之金屬内連線構成。晶片 ⑩ 308中之電子元件可包括（但不限於）微機電系統、微流 體系統、或利用熱、光線及壓力等物理變化量來測量的 物理感測器、射頻元件、加速計、陀螺儀、微制動器、 表面聲波元件、壓力感測器、或喷墨頭等。上封裝層312 可用於保護晶片308中之電子元件。當所欲保護之電子 元件屬光電元件時，例如包括發光二極體元件、光感測 元件、光伏電池(photovoltaic cell)，上封裝層312較佳選 用透明之材質。例如，在一實施例中，上封裝層312採 用第1C圖實施例中之由液態固化的上封裝層。在另一實 9002-A33562TWF/jychen 13 201034132 施例中，由液態固化的上封裴層具有大抵平坦的上表 面’且具有透光率約大於90%。在又一實施例中，上封 裝層312與晶片308之間不含黏著劑。 接著，如第3C圖所示，於承載基底3〇〇上形成填充 層316。填充層316可將凹槽3〇6填滿，並圍繞晶片3〇8。 填充層316之材質包括高分子材料，例如是環氧樹脂、 有機南分子材料之聚醢亞胺樹脂（polyimide)、苯環丁烯 (butylcyclobutene，BCB，道氏化學公司）、矽膠、或前述 ❹之組合。 其次，如第3D及3E圖所示，自下表面3〇4薄化承 載基底300至一既定深度。在此實施例中，承載基底3〇〇 薄化後露出部分的晶片308以及承載基底3〇〇之薄化後 下表面304a。請參照第3D圖，為了使承载基底3〇〇之 薄化及後續製程能較順利地完成，較佳將承載基底3〇〇 固定於一可回收之輔助基底318上。在一實施例中，可 先於承載基底300或輔助基底318上塗上可脫離黏著層 ® 320。接著，透過可脫離黏著層32〇使承載基底3〇〇與輔 助基底318接合。可脫離黏著層32〇例如包括可脫離膠 或膠帶。可脫離膠包括受熱脫離型、受光脫離型、或溶 劑洗去型等。 凊接著參照第3E圖，以輔助基底318為支撐，自承 載基底300之下表面304將承载基底3〇〇薄化至一既定 /木度以露出部分的晶片308及薄化後下表面3〇4a。承載 基底300之薄化可例如採用機械研磨（mechanjcai griding) 或化學機械研磨（CMP)等，而經此薄化步驟之後，即可直 9002-A33562TWF/jychen 14 - 201034132 接對露出之晶片下表面進行穿孔步驟，而不必使用多道 蝕刻製程。在一實施例中，可以進一步濕式清理薄化後 下表面304a。 接著，如第3F圖所示，於露出的晶片308上形成至 少一穿孔322，穿孔322可位於晶片308内之導電電極 310下方。穿孔322之形成方式例如包括微影及蝕刻製矛呈 或雷射穿孔製程等。在一實施例中，穿孔322露出至少 部分的導電電極310。在後續於穿孔322之侧壁形成導電 ❹層時，導電層可進一步與導電電極310電性連接，而形 成晶片308與外部電路的橋樑。 如第3G圖所示，為了避免導電層直接與晶片308中 之基底直接接觸而造成短路，或者避免導電層之材質擴 散進入晶片308中之電子元件而影響運作’較佳於形成 導電層之前，先於穿孔322之侧壁與底部上形成絕緣層 324。絕緣層324之材質可為環氧樹脂、防銲材料、或其 他適合之絕緣物質，例如無機材料之氧化带層、氮化石夕 ❹層、氮氧化矽層、金屬氧化物、或前述之組合；或亦可 為有機高分子材料之聚醯亞胺樹脂（Polyimide)、苯環丁烯 (butylcyclobutene, BCB，道氏化學公司）、聚對二曱苯 (parylene)、萘聚合物（polynaphthalenes)、氟碟化物 (fluorocarbons)、丙烯酸酯（acrylates)等。絕緣層 324 的形 成方式可包含塗佈方式，例如旋轉塗佈（spin coating)、喷 塗（spray coating)、或淋幕塗佈（curtain c〇ating)，或其他 適合之沈積方式，例如，液相沈積、物理氣相沈積、化 學氣相沈積、低壓化學氣相沈積、電漿增強式化學氣相 9002-A33562TWF/jychen 201034132 * 沈積、快速熱化學氣相沈積、或常壓化學氣相沈積等製 程。 在形成絕緣層324之後，較佳於絕緣層324上形成 露出導電電極310之第一開口 326。第一開口 326之形成 包括使用能量束移除部份的絕緣層324，例如使用雷射、 電子束、離子束等。或者，當絕緣層324之材質屬光阻 材料時，可直接透過曝光及顯影製程形成第一開口 326。 請接著參照第3H圖，於穿孔322之侧壁上形成導電 ❿ 層328。導電層328與導電電極310之間形成電性接觸。 在此實施例中，還進一步延伸至承載基底300之薄化後 下表面304a上。導電層328之材質包括金屬材料、導電 高分子材料、導電陶瓷材料、或前述之組合，可採用物 理氣相沉積、化學氣相沉積、或電化學電鍍等方法來形 成導電層328。 在一實施例中，導電層328例如透過絕緣層324上 所預先形成的第一開口 326而與導電電極310接觸。因 ⑩ 此，晶片308中的電子元件可透過筹電電極310及導電 層328而輸出或接收電子訊號。透過由穿孔322之侧壁 向下延伸至薄化後下表面304a上的導電層328，可增加 封裝體内連線的佈局區域，使輸出/輸入連接（I/O)之密度 降低。此外，雖然圖式中的導電層328係順應性地沉積 於穿孔322之侧壁上，但在其他實施例中，導電層328 亦可大抵完全填滿穿孔322,再透過線路重佈層而將導電 通路延伸至薄化後下表面304a上。 請接著參照第31圖，在一實施例中，可選擇性於薄 9002-A33562T WF/jychen 16 201034132 化後下表面304a及導電層328上形成保護層33〇。保護 層330之材質例如是高分子材料。保護層33〇之形成例 如包括噴塗法、噴墨法、浸鍍法、化學氣相沉積、網印 (printing)或前述之組合。接著，移除部份的保護層3扣 以形成至少一第二開口 332。保護層33〇之移除可&用任 何習知之方法或亦可以能量束移除。第二開口露出部分 延伸在薄化後下表面3〇4a上的導電層328，提供與外部 電路連接的接觸區。例如，在一實施例中，如第耵圖所 ❹示，於第二開口 332中形成導電結構334。例如，可於露 出之導電層328上進行凸塊化製程而形成銲球（即導電結 構334)。所形成之電子元件封裝結構可保護晶片3〇8，並 可提供與外部電路間之導電通路。 ^接著，如第3K圖所示，將輔助基底318及可脫離黏 著層320自承載基底3〇〇上移除，而獲得本發明一實施 例之電子^件封裝體。在一實施例中，承載基底3〇〇為 晶其封裝有複數個晶片308。在此實施例中，更包括 切割承載基底300以分離出至少一晶片封裝體。此外， 切割承載基底300之步驟可於移除辅助基底318之前或 之後進行。例如，當以可脫離膠帶作為黏著層32〇時， 較佳將承載基底300沿預定之切割道切穿至可 層320為止，但不整個切穿可脫離黏著層32〇。接著，再 一次移除辅助基底318而獲得數個晶片封裝體，如此， 可留下完整的輔助基底318並繼續回收使用。在其他實 施例中，係先將辅助基底318.整體移除後，才切割承載 基底300以分離出數個晶片封裝體。 ° 9002-A33562TWF/jychen 17 201034132 第3L圖顯示本發明一實施例中之電子元件封裝體 340。電子元件封裝體34〇包括承載基底3〇〇，具有至少 一開口 301 ’開口 301係自承載基底3〇〇之上表面3〇2向 下延伸。在此實施例中，開口 301自承載基底3〇〇之上 表面302貫穿至相反之下表面3〇4a。開口 3〇ι中填有填 充層316’且設置有晶片308’其中晶片308被填充層316 圍繞。晶片308具有導電電極310及至少一穿孔322，且 由上封裝層312所覆蓋。穿孔322之側壁上形成有導電 ❹層328，導電層328可進一步延伸至下表面3〇牦，且電 性連接至導電電極310。如第3L圖所示，導電層328將 導電通路自晶片308之導電電極310延伸至承载基底3〇〇 之下表面304a上，可增加封裝體内連線的佈局區域，使 輸出/輸入連接(I/O)之密度降低。隨著晶片3〇8尺寸不斷 地縮小化，本發明實施例所提供之方法及結構，更可有 效舒緩過於密集的導電通路佈局，使電子元件封裝體之 製作難度降低而有較高的良率。 ® 第4A-4L圖顯示本發明另一實施例中，具有穿石夕通 孔之封裝結構的一系列製程剖面圖。有別於第3圖所示 貫施例將穿石夕通孔形成於晶片中’此實施例將穿破通孔 形成於承載基底中。在第4圖之實施例中，相似的元件 將以相似的標號標示。 首先’如第4A圖所示，提供承載基底400，其具有 上表面402及相反之下表面404。承載基底4〇〇可包括矽 基底、化合物半導體基底、半導體晶圓、藍.寶石基底、 或前述之組合。接著，於承載基底4〇〇之上表面402形 9002-A33562TWF/jychen 18 201034132 成至少一凹槽406。如第4B圖所示，將具有導電電極之 晶片408設置於凹槽406中，例如可透過（但不限於）黏著 層414而將晶片408固定於凹槽406中。在此實施例中， 晶片408具有導電電極410,並部分由上封裝層412所覆 蓋，其中上封裝層412可位於導電電極410之上。晶片 408中之電子元件可包括（但不限於）微機電系統、微流 體系統、或利用熱、光線及壓力等物理變化量來測量的 物理感測器、射頻元件、加速計、陀螺儀、微制動器、 ❿表面聲波元件、壓力感測器、或喷墨頭等。上封裝層412 可用於保護晶片408中之電子元件。當所欲保護之電子 元件屬光電元件時，例如包括發光二極體元件、光感測 元件、光伏電池，上封裝層412較佳選用透明之材質。 例如，在一實施例中，上封裝層412採用第1C圖實施例 中之由液態固化的上封裝層。在另一實施例中，由液態 固化的上封裝層具有大抵平坦的上表面，且具有透光率 約大於90%。在又一實施例中，上封裝層412與晶片408 ❿之間不含黏著劑。 接著，如第4C圖所示，於承載基底400上形成填充 層416。填充層416圍繞晶片408。接著，於填充層416 上形成線路重佈層417,線路重佈層417電性連接至導電 電極410,且延伸至上表面402上。線路重佈層417之材 質包括金屬材料、導電高分子材料、導電陶瓷材料、或 前述之組合，可採用物理氣相沉積、化學氣相沉積、或 電化學電鍍等方法來形成線路重佈層417。 接著，如第4D及4E圖所示，自下表面404薄化承 9002-A33562TWF/jychen 19 201034132 載基底400至一既定深度。在此實施例中，薄化後之承 載基底400露出部分的晶片408以及承載基底400之薄 化後下表面404a。請參閱第4d圖，為了使承載基底400 之薄化及後續製程能較順利地完成，較佳將承載基底4〇〇 固定於輔助基底418上。在一實施例中，可先於承載基 底400或輔助基底4i8上塗上可脫離黏著層42〇。接著， 透過黏著層420使承載基底4〇〇與辅助基底418接合。 黏著層420例如包括可脫離膠或膠帶。可脫離膠包括受 ❿熱脫離型、受光脫離型、或溶劑洗去型等。 請接著參照第4E圖，以輔助基底418為支撐，自承 載基底400之下表面4〇4將承載基底4〇〇薄化至露出部 分的晶片408及薄化後下表面4〇4a。承載基底4〇〇之薄 化可例如採用機械研磨（mechanical gridi 研磨（CMP)等。在—實施例中，可以進—步溪式清== 後下表面404a。 ❹ —— 弟处圖所示，於路田的缚化後下表面4丨 上形成至少-穿孔422。穿孔422之形成方式例如包名 影及姓刻製程或雷射穿孔製程等。在—實施例中， 422露出至少部分的線路重佈層417。在後續於穿孔 之側壁形成導電層時’導電層可進—步 =連接(透過線路重佈層417)，而形成晶片4】:; 電路的橋樑。 〃 1 圖所示，為了避免導電層直接與晶片_ 之基底直接接觸而造成短路，或者避 散進入晶片408中之雷電曰之材負 〒之電子το件㈣響運作，較佳於开 9002-A33562TWF/jychen ^ ' 201034132 導電層之前，先於穿孔422之側壁與底部上形成絕緣層 424。 在形成絕緣層424之後，較佳於絕緣層424上形成 露出線路重佈層417之第一開口 426。第一開口 426之形 成包括使用能量束移除部份的絕緣層424，例如使用雷 射、電子束、離子束等。或者，當絕緣層424之材質屬 光阻材料時，可直接透過曝光及顯影製程形成第一開口 426 〇 G 請接著參照第4H圖，於穿孔422之側壁上形成導電 層428。導電層428透過線路重佈層417而電性連接至導 電電極410，且可延伸至承載基底400之薄化後下表面 404a上。導電層428之材質包括金屬材料、導電高分子 材料、導電陶瓷材料、或前述之組合，可採用物理氣相 沉積、化學氣相沉積、或電化學電鍍等方法來形成導電 層 428。 在一實施例中，導電層428例如透過絕緣層424上 ⑩ 所預先形成的第一開口 426而與線路重佈層417及導電 電極410電性接觸。因此，晶片408中的電子元件可透 過導電電極410、線路重佈層417、及導電層428而輸出 或接收電子訊號。透過由穿孔422之側壁向下延伸至薄 化後下表面404a上的導電層428，可增加封裝體内連線 的佈局區域，使輸出/輸入連接(I/O)之密度降低。此外， 雖然圖式中的導電層428係順應性地沉積於穿孔422之 側壁上，但在其他實施例中，導電層428亦可大抵完全 填滿穿孔422。 9002-A33562TWF/jychen 21 201034132 化後;圖，在一實施例中，可選擇性於薄 層之椅質例如是高分子材料 = (如包t括:塗r喷墨法、浸鐘法、化‘ :=前;之組合。接著，移除部份的保護層‘ 何習知之；法或：開口 432。保護層430之移除可使用任 延伸mis戈可以能量束移除。第二開口露出部分 申薄化後下表面404a上的導電層428201034132 VI. Description of the Invention: [Technical Field] The present invention relates to an electronic component package and a method of fabricating the same, and in particular to a layer of a material that is solidified by a liquid as an upper encapsulation layer and/or has a pass-through Through hole (TSV) electronic component package. [Prior Art] Photoelectric elements such as light sensing elements or light emitting elements play an important role in the application of capturing images or illuminating light. These photoelectric elements have been widely used, for example, in digital cameras and digital devices. In consumer electronic components and portable electronic components such as digital video recorders, mobile phones, solar cells, screens, and lighting devices. As the above various electronic components become lighter and lighter, the size of the photovoltaic device package has become smaller and smaller. Conventional semiconductor packages primarily encapsulate semiconductor wafers in an opaque electronic component package to avoid contamination of the semiconductor wafer by external defects and to protect the semiconductor wafer from external impact. Conversely, a photovoltaic element (such as a CMOS image sensor or a light-emitting diode element) must be packaged in an electronic component package having at least one transparent substrate (such as a glass substrate) as an upper sealing layer to receive external light or output light: The package is usually packaged by coating the entire surface of the transparent substrate with an adhesive and bonding it to a wafer having a light sensing element or a light emitting element. However, the adhesive may cause light to refract and affect the reception or output of light. In order to prevent the adhesive from affecting the reception or output of light, 9002-A33562TWF/jychen 3 201034132 ^ has been developed to use a dam structure to support a transparent substrate and enclose a cavity. In this technique, the cofferdam structure is used to fix the transparent substrate on the photovoltaic element instead of the entire surface (only the adhesive is applied to the cofferdam structure), and the photoelectric element is surrounded by the light receiving or outputting. The hole and the transparent substrate do not need to pass through an adhesive with poor light transmittance, and have better light receiving and output. However, the structural strength of the dam structure is poor, and it is easy to crack, delaminate, bend, etc. at the joint (for example, at the joint with the transparent substrate). In addition, the transparent substrate used by ® is generally a glass substrate, which increases the weight of the package in addition to being expensive. In addition, as semiconductor process technology continues to advance, more semiconductor components can be formed in smaller wafers. In addition to improving the performance of the wafer, it also saves wafer area and reduces cost. However, as wafer size is reduced and component density is increased, the number and density of output/input connections (I/O) are also increased, thereby causing packaging difficulties. Therefore, there is a need in the industry for a novel packaging technique and structure to improve the packaging of 10 photovoltaic components. SUMMARY OF THE INVENTION Embodiments of the present invention provide an electronic component package including a substrate having an electronic component, wherein the substrate has a first surface and an opposite second surface, and an upper encapsulation layer directly formed by liquid curing in the first On the surface, and the upper encapsulating layer and the first surface do not contain an adhesive, wherein the liquid-cured upper encapsulating layer has a flat upper surface, and the liquid-cured upper encapsulating layer has a light transmittance of more than 90%. 9002-A33562TWF/jychen 4 201034132 Another embodiment of the present invention provides a method of forming an electronic component package, comprising: providing a substrate having an electronic component, the substrate having a first surface and an opposite second surface; and directly to the first surface Forming an upper encapsulating layer by liquid curing, the adhesive layer is not contained between the upper encapsulating layer and the first surface, wherein the upper encapsulating layer solidified by the liquid has a flat upper surface, and the light transmittance of the liquid encapsulating upper encapsulating layer About greater than 9% by weight: wherein the formation of the liquid-cured upper encapsulation layer comprises: directly covering the liquid material on the first surface; and curing the liquid material to form the upper encapsulation layer. The embodiment of the present invention further provides a method for forming an electronic component package, comprising: providing a carrier substrate having an upper surface and an opposite lower surface; forming at least one recess on the upper surface of the carrier substrate; " another crystal having a conductive electrode and being covered by an upper encapsulation layer; forming a filling layer in the recess of the carrier substrate, the filling layer surrounding the wafer; thinning the carrier substrate from the lower surface to a predetermined depth Forming at least a via in the wafer or in the carrier substrate; and forming a conductive layer on the sidewall of the via, and the conductive layer is in electrical contact with the conductive electrode. The embodiment of the present invention further provides an electronic component package comprising a carrier substrate having at least an opening extending downward from the upper surface of the carrier substrate, a filling layer located in the opening, and a wafer located in the opening 'and surrounded by a filled layer, the wafer having a conductive electrode; an upper encapsulation layer covering the wafer; at least - a via, located within the wafer or within the carrier substrate; and a conductive layer on the sidewall of the via, and a conductive layer Electrical contact is made with the conductive electrode. The above and other objects, features, and advantages of the present invention will become more apparent from the detailed description of the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; MODES OF THE INVENTION One embodiment of the present invention provides an electronic component package having an upper encapsulation layer in a liquid-solidified material layer, which is cured by a liquid material to form a transparent upper encapsulation layer. Another embodiment of the present invention further A package structure having a through via (TSV) is provided, and a conductive via outside the wafer and the package structure is formed by using a through via and a line Φ redistribution layer (RDL). The stages of the embodiment of the present invention will be represented by a pattern. In the drawings and the stipulations of the embodiments of the present invention, similar components will be labeled with similar labels. 1A-1D shows a series of process profiles of the electronic component package of the embodiment of the present invention. As shown in Fig. 1A, a substrate 100 comprising electronic components having a first surface 102 and an opposite second surface 104 is provided. The substrate 100 can be a germanium substrate, a semiconductor substrate, a compound. A semiconductor substrate, a semiconductor wafer, a sapphire substrate, or a combination thereof. φ The electronic component package of the embodiment of the present invention includes a wafer level package, which mainly refers to cutting into a separate package after the packaging step is completed at the wafer stage. However, in a particular embodiment, for example, redistributing the separated semiconductor wafer onto a carrier wafer and then performing a packaging process may also be referred to as a wafer level packaging process. It is suitable for arranging a plurality of wafers having an integrated circuit by a stack to form a package of a multi-layer integrated circuit device. In one embodiment, the substrate 100 has an electronic component 106 on the first surface 102 that is exposed to 9002-A33562T WF/jychen 6 201034132, which may be various optoelectronic components. For example, electronic component 106 can be a light sensing component, a solar cell, or a light emitting component or the like. The electronic component 106 can also be a micro electro mechanical system (MEMS), a micro fluidic system, or a physical sensor that is measured by physical changes such as heat, light, and pressure. RF circuits, accelerators, gyroscopes, micro actuators, surface acoustic wave components, pressure ❹ sensors, or ink printer heads . In order to protect the electronic component 106 from external contamination or damage, a transparent upper encapsulation layer is formed thereon to provide protection and allow light to enter and exit smoothly. Next, a characteristic step of an embodiment of the present invention is performed, which is liquid solidified directly on the first surface 102 to form a material layer having a substantially flat upper surface and having a light transmittance of greater than about 90 Å/〇. The liquid-cured material layer can be used as the upper encapsulation layer of the electronic component package of the embodiment of the present invention, and can replace the conventional glass substrate, adhesive, or bank structure. In one embodiment, no additional adhesive is present between the upper encapsulation layer and the first surface 102. Referring to Figure 1B-1C, there is shown the formation of a liquid-solidified upper encapsulation layer 108 in an embodiment of the present invention. As shown in Fig. 1B, the fluid material 10 8 a is directly applied to the first surface 102 of the substrate 1 ’. The coating property of the liquid material 108a itself is used to form a coating film which is substantially flat. The liquid material 108a can be directly applied to the first surface 102 by various wet coating methods, such as bar coating, spinning 9002-A33562TWF/jychen 7 201034132 spin coating, curtain coating Curtain coating, spray coating, and the like. The liquid material 108a comprises a polymer material which is transparent after curing, preferably a thermosetting polymer material, which allows the encapsulating layer 108 to have sufficient hardness (e.g., greater than about 100 degrees Rockwell) and heat resistance after curing. Suitable liquid materials 108a include, for example, but are not limited to, age-old epoxy resins such as Novolac phenol epoxy resin, CAS No. 28906-96-9. In other embodiments, a novolac epoxy resin can be used, for example, with Gamma Butyrolactone (CAS No.). 96-48-0) is mixed as a liquid material 108a. Alternatively, other additives such as triarylsulfonium hexafluoroantimonate salt (CAS No.) may be further added. 109037-75-4) or / and propylene carbonate (CAS No.) 108-32-7) and so on. In one embodiment, a polymer suitable for use as the liquid material 108a can be heated to a temperature greater than about its glass transition temperature to impart fluidity, and then a fluid material 10 8 a can be applied to the first surface 102. . In the first embodiment, the coating property of the liquid material 10 8a itself can be used to form a coating film which is substantially flat. Alternatively, the substrate 100 can be placed on a rotatable platform, and the liquid material 10a can be hooked over the first surface 102 by a spin-like coating, and has a substantially flat upper surface. Since the polymer material has a certain viscosity even at a temperature slightly higher than the glass transition temperature, it is not completely lost from the first surface. A barrier structure (not shown) may also be formed on the edge of the first surface 102 of the substrate 100 to avoid loss of the liquid material 108a prior to curing. Alternatively, a barrier structure (not shown) may be formed on the platform on which the substrate 1 is placed, with 9002-A33562TWF/jychen 8 201034132' to enclose the substrate 100. Further, a suitable solvent may be added to the liquid material 10a to adjust its coating properties. Next, for example, the ultraviolet light 10 may be irradiated over the liquid material 108a to cause the liquid material 10a to be crosslinked and solidified to form the upper encapsulation layer 108 (as shown in Fig. 1C). The upper encapsulation layer 108 may also retain a substantially flat upper surface after curing. Moreover, in one embodiment, the thickness of the upper encapsulating layer 108 solidified by the liquid is greater than about ΙΟμπι, preferably between about Ιμπι and 5μπι. Further, since the upper encapsulating layer is cured by the above method, since the thermal expansion rate of the upper encapsulating layer is small, the stability of the electronic component package can be ensured. In the above embodiment, the upper encapsulation layer 108 has a substantially flat upper surface, where the substantially flat means that the difference between the highest and lowest surfaces of the upper encapsulation layer 108 is small, without affecting the input or output of light. For example, in one embodiment, the height difference between the highest and lowest surfaces of the upper encapsulation layer 108 is less than about 3 μηη, preferably, the height difference is less than about 1 μηη. It should be noted that, depending on the wavelength of the transmitted light or the size and type of the package, the height difference of the surface of the upper package layer 108 may be different, and is not limited to the aforementioned range of height difference. Since the liquid-cured upper encapsulation layer 108 includes a transparent polymeric material and a substantially flat upper surface, the electronic component 106 can receive or output light through the transparent liquid-cured upper encapsulation layer 108 without causing refraction or Scattering and other issues. Further, other additives may be added to the upper encapsulating layer 108 which is solidified by the liquid. For example, a hardener or the like may be added, for example, it may be directly added to the liquid material 10 8 a. Further, a fluorescent material (e.g., phosphor powder) may be added to the liquid-solidified upper package layer 108, which may be used to modulate the output of the 9002-A33562TWF/jychen 9 201034132* or the wavelength of the input light. The phosphor material may be applied to the upper encapsulation layer 108 in addition to the upper encapsulation layer 108, e.g., a phosphor layer may be formed on the upper encapsulation layer. Further, the remaining various optical components may be formed on the electronic component 106 or on the liquid-cured upper encapsulation layer ι 8 to meet various needs. For example, 'micro-lens array structure, filter, anti-reflection layer, polarized light, dichr〇ic filter, optical grating, optical waveguide (optical wave guide) ) is equal to the electronic component 106.导电 Next, referring to FIG. 1D, a conductive structure 114, such as a winter conductive bump, may be formed on the second surface 104 of the substrate 1 各种 by various conventional techniques. A plurality of conductive paths (not shown) may be disposed between the conductive structure 114 and the electronic component 1', and may further include an insulating layer 11 and a solder resist 112 between the substrate and the substrate. In one embodiment, the conductive bumps 112 are patterned with conductive bumps to form a termination contact pad on the surface of the conductive via (not shown), followed by a patterned photoresist layer. The solder plating is either filled in the terminal contact pad opening by coating the solder by screen printing, and finally the seed layer or the photoresist layer is removed and reflowed to form a solder ball to complete the conductive bump process. The conductive structure 114' electrically connected to the electronic component 1〇6 serves as a signal communication bridge between the electronic component 1〇6 and an external circuit of the electronic component package. The material of the insulating layer 11 can be epoxy resin, solder resist material, or other suitable insulating material, such as inorganic material = yttrium oxide layer, tantalum nitride layer, yttrium oxynitride layer, metal oxide, or just a combination of the above; or a polyimine tree of an organic polymer material, a butylcycline butene, a parylene, or a parylene. Naphthalene polymer 9002-A33562TWF/jychen ^ 201034132 (polynaphthalenes) ' l Carbide (fluorocarbons), acrylic acid acrylates and the like. The manner in which the insulating layer 110 is formed may include a coating method such as spin coating, spray coating, or curtain coating ' or other suitable deposition method, for example, liquid deposition. , physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition, or atmospheric pressure chemical vapor deposition processes. In the foregoing embodiment, the liquid material l8a having fluidity is directly coated onto the first surface, but the manner of formation of the embodiment of the present invention is not limited thereto. Fig. 2A-2C is a cross-sectional view showing a series of processes of an electronic component package according to another embodiment of the present invention. As shown in Fig. 2, a solid granular material 丨〇 8b is spread on the first surface 102. Next, as shown in Fig. 2B, A? is irradiated onto the granular material 1 to emit infrared light 20 to heat the granular material 1?8b. When the temperature of the heated particulate material 108b is higher than its glass transition temperature, it will be converted into a liquid liquid material 108c (as shown in Fig. 2B). Next, similar to the embodiment described in Fig. 1B, the fluid liquid material i 〇 8 c is naturally flowed or transmitted through the rotating substrate 100 to have a substantially flat upper surface (as shown in Fig. 2C). In one embodiment, the structure shown in Figure 2B is placed on a rotatable platform (not shown) and rotated, at which point the infrared light 20 can be illuminated simultaneously. By adjusting the rotational speed of the rotatable platform and the wavelength and intensity of the infrared light, the surface state of the liquid material 108c can be adjusted to have a substantially flat upper surface (as in Figure 2C). For example, as the surface of the liquid material 1 〇 8c gradually flattens, the intensity of the infrared light 2 及 and/or the rotational speed of the rotatable platform can be gradually reduced to gradually reduce the fluidity of the liquid material 1 〇 8c by 9002-A33562TWF. /jychen 11 201034132 Low and shaped. Finally, as shown in FIG. 2C, the liquid material 108c may be irradiated with ultraviolet light 10 to be cured into a liquid-solidified upper encapsulation layer 108 as shown in FIG. 1C as an electronic component package of the embodiment of the present invention. Encapsulation layer. Similarly, in other embodiments, the fluidity of the liquid material can be adjusted by controlling the temperature to obtain a substantially overlying surface and a transparent overlying encapsulation layer. The subsequent process is the same as that shown in Fig. 1D, and the formation of the conductive structure can be performed, and will not be described herein. The embodiment of the present invention has many advantages, such as the first surface 1 〇 2 or the liquid-solidified upper encapsulation layer 1 〇 8 does not have a glass substrate, and the liquid-solidified upper encapsulation layer 1 〇 8 replaces the glass substrate, It can effectively avoid the influence of the adhesive on the light transmittance in the prior art, and can avoid the doubts about the reliability caused by the weaker cofferdam structure. In one embodiment of the present invention, the process of arranging the glass substrate on the first surface 1〇2 or the liquid-cured upper encapsulation layer 1〇8 is not required, and in addition to greatly reducing the cost, many process times can be saved. In some embodiments, a transparent thermosetting polymer is used as the upper encapsulation layer 〇8, which can have higher heat resistance, so that the upper sealing layer 1〇8 can maintain transparency even at a higher operating temperature. And it is generally flat. In addition, the liquid-cured upper encapsulating layer 1 〇 8 is much lighter than the glass substrate and is more suitable for various portable electronic products. The above-mentioned liquid-cured material layer or the upper encapsulating layer can be applied to various sealing structures. For convenience of description, the following is a package structure having a through-via through-hole V, but it should not be limited thereto. Referring to the following, the present invention implements a series of process profiles having a package structure through a through-hole through-hole (TSV). First, as shown in Fig. 3A, a carrier substrate 3 is provided having an upper surface 3(10) 9002-A33562TWF/jychen 12 201034132 and an opposite lower surface 304. The carrier substrate 300 can comprise a germanium substrate, a semiconductor substrate, a compound semiconductor substrate, a semiconductor wafer, a sapphire substrate, or a combination of the foregoing. Next, at least one recess 306 is formed in the upper surface 302 of the carrier substrate 300. It should be noted that in a preferred embodiment, the carrier substrate 300 is preferably a germanium wafer, and a plurality of recesses 306 are preferably formed. Several wafers can be placed in several recesses in the wafer, and after subsequent packaging and dicing processes, several electronic component packages are obtained. The recess 306 can be formed, for example, by a lithography and etching process. Referring next to Figure 3B, a wafer 308 having conductive electrodes is disposed in the recess 306, such as by, but not limited to, an adhesive layer 314 to secure the wafer 308 in the recess 306. In this embodiment, wafer 308 has conductive electrodes 310 and is covered by upper encapsulation layer 312, with upper encapsulation layer 312 being over conductive electrodes 310. The conductive electrode 310 can serve as a conductive path between the electronic component and the package in the wafer 308. For example, the conductive electrode 310 can be formed by a metal interconnection of the semiconductor wafer. Electronic components in wafer 10 308 may include, but are not limited to, microelectromechanical systems, microfluidic systems, or physical sensors, radio frequency components, accelerometers, gyroscopes, measured using physical variations such as heat, light, and pressure. Micro-brakes, surface acoustic wave components, pressure sensors, or inkjet heads. The upper encapsulation layer 312 can be used to protect electronic components in the wafer 308. When the electronic component to be protected is a photovoltaic element, for example, including a light emitting diode element, a light sensing element, and a photovoltaic cell, the upper encapsulating layer 312 is preferably made of a transparent material. For example, in one embodiment, the upper encapsulation layer 312 employs an upper encapsulation layer that is liquid cured in the embodiment of Figure 1C. In another embodiment of 9002-A33562TWF/jychen 13 201034132, the liquid-solidified upper seal layer has a substantially flat upper surface and has a light transmission of greater than about 90%. In yet another embodiment, the upper encapsulant layer 312 and the wafer 308 are free of an adhesive. Next, as shown in Fig. 3C, a filling layer 316 is formed on the carrier substrate 3A. The fill layer 316 fills the recess 3〇6 and surrounds the wafer 3〇8. The material of the filling layer 316 includes a polymer material such as an epoxy resin, a polyimide of an organic south molecular material, a butylcyclobutene (BCB, Dow Chemical Company), a silicone rubber, or the foregoing ruthenium. The combination. Next, as shown in Figs. 3D and 3E, the carrier substrate 300 is thinned from the lower surface 3〇4 to a predetermined depth. In this embodiment, the carrier substrate 3 is thinned to expose a portion of the wafer 308 and the thinned lower surface 304a of the carrier substrate 3A. Referring to FIG. 3D, in order to make the thinning of the carrier substrate 3 and the subsequent process can be completed smoothly, the carrier substrate 3 is preferably fixed on a recyclable auxiliary substrate 318. In one embodiment, the detachable adhesive layer ® 320 may be applied to the carrier substrate 300 or the auxiliary substrate 318. Next, the carrier substrate 3 is bonded to the auxiliary substrate 318 through the detachable adhesive layer 32. The detachable adhesive layer 32, for example, includes a detachable glue or tape. The detachable glue includes a heat-removing type, a light-removing type, or a solvent-washing type. Next, referring to FIG. 3E, with the auxiliary substrate 318 as a support, the carrier substrate 3 is thinned from the lower surface 304 of the carrier substrate 300 to a predetermined/woody degree to expose a portion of the wafer 308 and the thinned lower surface 3〇. 4a. The thinning of the carrier substrate 300 can be, for example, mechanical grinding or chemical mechanical polishing (CMP), etc., and after the thinning step, the exposed lower surface of the wafer can be directly connected to 9002-A33562TWF/jychen 14 - 201034132. The perforation step is performed without having to use a multi-pass etching process. In an embodiment, the thinned lower surface 304a may be further wet cleaned. Next, as shown in FIG. 3F, at least one via 322 is formed on the exposed wafer 308, and the via 322 may be located under the conductive electrode 310 in the wafer 308. The formation of the perforations 322 includes, for example, lithography and etching of a spear or laser perforation process. In one embodiment, the vias 322 expose at least a portion of the conductive electrodes 310. When a conductive germanium layer is formed on the sidewall of the via 322, the conductive layer can be further electrically connected to the conductive electrode 310 to form a bridge between the wafer 308 and an external circuit. As shown in FIG. 3G, in order to prevent the conductive layer from directly contacting the substrate in the wafer 308, a short circuit is caused, or the material of the conductive layer is prevented from diffusing into the electronic component in the wafer 308 to affect the operation, preferably before forming the conductive layer. An insulating layer 324 is formed on the sidewalls and the bottom of the via 322. The material of the insulating layer 324 may be an epoxy resin, a solder resist material, or other suitable insulating material, such as an oxidized strip layer of an inorganic material, a nitride layer, a cerium oxynitride layer, a metal oxide, or a combination thereof; Or it may be a polyimide resin of organic polymer materials, butylcyclobutene (BCB, Dow Chemical Company), parylene, polynaphthalenes, fluorine. Fluorocarbons, acrylates, and the like. The manner in which the insulating layer 324 is formed may include a coating method such as spin coating, spray coating, or curtain coating, or other suitable deposition method, for example, liquid. Phase deposition, physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor phase 9002-A33562TWF/jychen 201034132 * Deposition, rapid thermal chemical vapor deposition, or atmospheric chemical vapor deposition Process. After the insulating layer 324 is formed, a first opening 326 exposing the conductive electrode 310 is preferably formed on the insulating layer 324. The formation of the first opening 326 includes the use of an energy beam to remove portions of the insulating layer 324, such as using a laser, electron beam, ion beam, or the like. Alternatively, when the material of the insulating layer 324 is a photoresist material, the first opening 326 can be formed directly through the exposure and development process. Referring to Figure 3H, a conductive germanium layer 328 is formed on the sidewalls of the vias 322. Electrical contact is formed between conductive layer 328 and conductive electrode 310. In this embodiment, it is further extended to the thinned lower surface 304a of the carrier substrate 300. The material of the conductive layer 328 includes a metal material, a conductive polymer material, a conductive ceramic material, or a combination thereof, and the conductive layer 328 may be formed by a method such as physical vapor deposition, chemical vapor deposition, or electrochemical plating. In one embodiment, the conductive layer 328 is in contact with the conductive electrode 310, for example, through the pre-formed first opening 326 on the insulating layer 324. As a result, the electronic components in the wafer 308 can output or receive electronic signals through the power-up electrode 310 and the conductive layer 328. By extending the sidewalls of the vias 322 down to the conductive layer 328 on the thinned lower surface 304a, the layout of the interconnects within the package can be increased, reducing the density of the output/input connections (I/O). In addition, although the conductive layer 328 in the drawing is conformally deposited on the sidewall of the via 322, in other embodiments, the conductive layer 328 may also completely fill the via 322 and then pass through the trace layer. The conductive path extends onto the thinned lower surface 304a. Referring to Fig. 31, in an embodiment, a protective layer 33A may be selectively formed on the lower surface 304a and the conductive layer 328 after the thin 9002-A33562T WF/jychen 16 201034132. The material of the protective layer 330 is, for example, a polymer material. The formation of the protective layer 33 is, for example, a spray coating method, an ink jet method, a immersion plating method, a chemical vapor deposition, a printing method, or a combination thereof. Next, a portion of the protective layer 3 is removed to form at least one second opening 332. The removal of the protective layer 33 can be removed by any conventional method or by an energy beam. The second opening exposes a conductive layer 328 extending over the thinned lower surface 3〇4a to provide a contact area for connection to an external circuit. For example, in one embodiment, conductive structure 334 is formed in second opening 332 as shown in the figure. For example, a bumping process can be performed on the exposed conductive layer 328 to form solder balls (i.e., conductive structures 334). The formed electronic component package structure protects the wafers 3〇8 and provides a conductive path to the external circuitry. Then, as shown in Fig. 3K, the auxiliary substrate 318 and the detachable adhesive layer 320 are removed from the carrier substrate 3 to obtain an electronic package according to an embodiment of the present invention. In one embodiment, the carrier substrate 3 is crystalline and encapsulated with a plurality of wafers 308. In this embodiment, the carrier substrate 300 is further diced to separate at least one of the chip packages. Moreover, the step of cutting the carrier substrate 300 can be performed before or after the auxiliary substrate 318 is removed. For example, when the detachable tape is used as the adhesive layer 32, the carrier substrate 300 is preferably cut through the predetermined scribe line to the layer 320, but not completely cut away from the adhesive layer 32. Next, the auxiliary substrate 318 is again removed to obtain a plurality of chip packages, thus leaving a complete auxiliary substrate 318 and continuing to be recycled. In other embodiments, the auxiliary substrate 318 is first introduced. After the overall removal, the carrier substrate 300 is diced to separate a plurality of chip packages. ° 9002-A33562TWF/jychen 17 201034132 FIG. 3L shows an electronic component package 340 in an embodiment of the present invention. The electronic component package 34 includes a carrier substrate 3 having at least one opening 301'. The opening 301 extends downward from the upper surface 3〇2 of the carrier substrate 3〇〇. In this embodiment, the opening 301 extends from the upper surface 302 of the carrier substrate 3 to the opposite lower surface 3〇4a. The opening 3 is filled with a filling layer 316' and is provided with a wafer 308' in which the wafer 308 is surrounded by a filling layer 316. The wafer 308 has a conductive electrode 310 and at least one via 322 and is covered by an upper encapsulation layer 312. A conductive germanium layer 328 is formed on the sidewall of the via 322. The conductive layer 328 can further extend to the lower surface 3A and be electrically connected to the conductive electrode 310. As shown in FIG. 3L, the conductive layer 328 extends the conductive vias from the conductive electrodes 310 of the wafer 308 to the lower surface 304a of the carrier substrate 3, thereby increasing the layout area of the wiring within the package and enabling output/input connections ( The density of I/O) is reduced. As the size of the chip 3 〇 8 is continuously reduced, the method and structure provided by the embodiments of the present invention can effectively alleviate the layout of the conductive path which is too dense, and the manufacturing difficulty of the electronic component package is lowered and the yield is high. . ® 4A-4L shows a series of process cross-sectional views of a package structure having a through-hole through hole in another embodiment of the present invention. Different from the embodiment shown in Fig. 3, a through-hole is formed in the wafer. This embodiment forms a through-hole in the carrier substrate. In the embodiment of Fig. 4, like elements will be designated by like reference numerals. First, as shown in Figure 4A, a carrier substrate 400 is provided having an upper surface 402 and an opposite lower surface 404. The carrier substrate 4 can include a germanium substrate, a compound semiconductor substrate, a semiconductor wafer, and a blue. Gemstone substrate, or a combination of the foregoing. Next, at least one groove 406 is formed on the surface 402 of the carrier substrate 4, 9002-A33562TWF/jychen 18 201034132. As shown in FIG. 4B, a wafer 408 having conductive electrodes is disposed in the recess 406, such as by, but not limited to, an adhesive layer 414 to secure the wafer 408 in the recess 406. In this embodiment, wafer 408 has conductive electrodes 410 and is partially covered by upper encapsulation layer 412, which may be over conductive electrodes 410. The electronic components in wafer 408 may include, but are not limited to, a microelectromechanical system, a microfluidic system, or a physical sensor, radio frequency component, accelerometer, gyroscope, micro, measured using physical variations such as heat, light, and pressure. Brake, rake surface acoustic wave element, pressure sensor, or inkjet head. The upper encapsulation layer 412 can be used to protect electronic components in the wafer 408. When the electronic component to be protected is a photovoltaic element, for example, including a light emitting diode element, a light sensing element, and a photovoltaic cell, the upper encapsulating layer 412 is preferably made of a transparent material. For example, in one embodiment, the upper encapsulation layer 412 employs an upper encapsulation layer that is liquid cured in the embodiment of Figure 1C. In another embodiment, the liquid-cured upper encapsulation layer has a substantially flat upper surface and has a light transmission of greater than about 90%. In yet another embodiment, the upper encapsulation layer 412 and the wafer 408 are free of an adhesive. Next, as shown in Fig. 4C, a filling layer 416 is formed on the carrier substrate 400. Filler layer 416 surrounds wafer 408. Next, a circuit redistribution layer 417 is formed on the filling layer 416, and the circuit redistribution layer 417 is electrically connected to the conductive electrode 410 and extends onto the upper surface 402. The material of the circuit redistribution layer 417 includes a metal material, a conductive polymer material, a conductive ceramic material, or a combination thereof, and the circuit redistribution layer 417 may be formed by physical vapor deposition, chemical vapor deposition, or electrochemical plating. . Next, as shown in Figs. 4D and 4E, the substrate 400 is thinned from the lower surface 404 to a predetermined depth from the 9002-A33562TWF/jychen 19 201034132 substrate. In this embodiment, the thinned substrate 400 exposes a portion of the wafer 408 and the thinned lower surface 404a of the carrier substrate 400. Referring to Fig. 4d, in order to make the thinning of the carrier substrate 400 and subsequent processes more smoothly, the carrier substrate 4 is preferably fixed to the auxiliary substrate 418. In one embodiment, the detachable adhesive layer 42 can be applied prior to the carrier substrate 400 or the auxiliary substrate 4i8. Next, the carrier substrate 4 is bonded to the auxiliary substrate 418 through the adhesive layer 420. Adhesive layer 420 includes, for example, a detachable glue or tape. The detachable glue includes a heat-removing type, a light-removing type, or a solvent-washing type. Next, referring to Fig. 4E, with the auxiliary substrate 418 as a support, the carrier substrate 4 is thinned from the lower surface 4?4 of the carrier substrate 400 to the exposed portion of the wafer 408 and the thinned lower surface 4?4a. The thinning of the carrier substrate 4 can be, for example, mechanical grinding (Mechanical gridi polishing (CMP), etc. In the embodiment, it is possible to advance to the lower surface 404a. ❹ —— At least the perforation 422 is formed on the lower surface 4 of the Lutian after the binding. The formation of the perforation 422 is, for example, a name masking process or a laser etching process, etc. In the embodiment, the 422 is exposed at least partially. The circuit redistribution layer 417. When the conductive layer is formed on the sidewall of the via hole, the conductive layer can be stepped through (connected through the line redistribution layer 417) to form a bridge of the circuit 4: 电路 1 In order to avoid short circuit caused by the direct contact of the conductive layer with the substrate of the wafer, or to avoid the electrons of the lightning ram that enters the wafer 408, the electronic device is preferably operated at 9002-A33562TWF/jychen ^ ' Prior to the conductive layer of 201034132, an insulating layer 424 is formed on the sidewalls and the bottom of the via 422. After the insulating layer 424 is formed, a first opening 426 exposing the line redistribution layer 417 is preferably formed over the insulating layer 424. The first opening 426 Formation of A portion of the insulating layer 424 is removed by an energy beam, for example, using a laser, an electron beam, an ion beam, etc. Alternatively, when the material of the insulating layer 424 is a photoresist material, the first opening 426 can be formed directly through the exposure and development process. 〇G Next, referring to FIG. 4H, a conductive layer 428 is formed on the sidewall of the via 422. The conductive layer 428 is electrically connected to the conductive electrode 410 through the circuit redistribution layer 417, and can be extended to the thinned lower surface of the carrier substrate 400. The surface of the conductive layer 428 comprises a metal material, a conductive polymer material, a conductive ceramic material, or a combination thereof, and the conductive layer 428 may be formed by physical vapor deposition, chemical vapor deposition, or electrochemical plating. In one embodiment, the conductive layer 428 is in electrical contact with the line redistribution layer 417 and the conductive electrode 410, for example, through the first pre-formed opening 426 of the insulating layer 424. Thus, the electronic components in the wafer 408 are permeable. The conductive electrode 410, the line redistribution layer 417, and the conductive layer 428 output or receive an electronic signal. The guide is extended downward through the sidewall of the through hole 422 to the thinned lower surface 404a. The electrical layer 428 can increase the layout area of the wiring in the package to reduce the density of the output/input connection (I/O). Further, although the conductive layer 428 in the drawing is conformally deposited on the sidewall of the via 422. However, in other embodiments, the conductive layer 428 can also substantially completely fill the perforations 422. 9002-A33562TWF/jychen 21 201034132 After the image; in an embodiment, the chair can be selectively selected for a thin layer, for example, high Molecular material = (such as package t: coated r inkjet method, dip clock method, chemical ': = before; a combination. Next, remove some of the protective layer ‘how to know; method or: opening 432. Removal of the protective layer 430 can be removed using an energy beam. The second opening exposes the conductive layer 428 on the lower surface 404a after thinning
電=的接觸區。例如，在-實施例中，如第二: 不，苐一開口 432中形成導電結構434。例如，可於 出之導電層428上進行凸塊化製程而形成銲球(即導電锋 構434)。所形成之電子元件封裝結構可保護晶片術，並 可提供與外部電路間之導電通路。 接著，如帛4K _所示，將輔助基底418及黏著 自承載基底400上移除，而獲得本發明一實施例之電 子兀件封裝體。在—實施例中，承載基底400為晶圓， 其封裝有複數個晶片4G8。在此實施例中，更包括切割承 載基底4GG以分離出至少—晶片封裝體。此外，切割承 載基底400之步驟可於移除輔助基⑥418之前或之後進 行。例如，當以可脫離膠帶作為黏著層42〇時，較佳將 承載基底400沿預定之切割道切穿，但不整個切穿黏著 層420。接著，再一次移除辅助基底418而獲得數個晶片 封裝體，如此，可留下完整的輔助基底318並繼續回收 使用。在其，他實施例中，係先將輔助基底418整體移除 後，才切割承載基底400以分離出數個晶片封裝體。 9002-A33562TWF/jychen 22 201034132 第4L圖顯示本發明一實施例中之電子元件封裝體 440。電子元件封裝體440包括承載基底400，具有至少 一開口 401，開口 401係自承載基底400之上表面402向 下延伸。在此實施例中，開口 401自承載基底400之上 表面402貫穿至相反之下表面404a。開口 401中填有填 充層416’且設置有晶片408,其中晶片408被填充層416 圍繞。晶片408具有導電電極410，並由上封裝層412所 覆蓋。電子元件封裝體440還包括線路重佈層417，位於Contact area of electricity =. For example, in an embodiment, as in the second: no, a conductive structure 434 is formed in the first opening 432. For example, a bumping process can be performed on the conductive layer 428 to form a solder ball (i.e., conductive front 434). The resulting electronic component package structure protects the wafer and provides a conductive path to the external circuitry. Next, as shown in Fig. 4K, the auxiliary substrate 418 and the adhesive self-supporting substrate 400 are removed to obtain an electronic component package according to an embodiment of the present invention. In an embodiment, the carrier substrate 400 is a wafer that is packaged with a plurality of wafers 4G8. In this embodiment, the cutting carrier substrate 4GG is further included to separate at least the wafer package. Additionally, the step of cutting the carrier substrate 400 can be performed before or after the removal of the auxiliary substrate 6418. For example, when the detachable tape is used as the adhesive layer 42, the carrier substrate 400 is preferably cut through a predetermined scribe line, but not entirely through the adhesive layer 420. Next, the auxiliary substrate 418 is again removed to obtain a plurality of wafer packages, thus leaving a complete auxiliary substrate 318 and continuing to be recycled. In the embodiment, the auxiliary substrate 418 is removed as a whole before the carrier substrate 400 is cut to separate a plurality of chip packages. 9002-A33562TWF/jychen 22 201034132 FIG. 4L shows an electronic component package 440 in an embodiment of the present invention. The electronic component package 440 includes a carrier substrate 400 having at least one opening 401 extending downwardly from the upper surface 402 of the carrier substrate 400. In this embodiment, the opening 401 extends from the upper surface 402 of the carrier substrate 400 to the opposite lower surface 404a. The opening 401 is filled with a filling layer 416' and is provided with a wafer 408, wherein the wafer 408 is surrounded by a filling layer 416. Wafer 408 has conductive electrodes 410 and is covered by upper encapsulation layer 412. The electronic component package 440 also includes a line redistribution layer 417 located at
填充層416上且延伸至上表面402上。線路重佈層 與導電電極410電性相連。電子元件封裝體44〇還包括 穿孔422’穿孔422側壁上形成有導電層428,導電層 可進一步延伸至下表面404a上，且透過線路重佈層w 而電性連接至導電電極410。如第4L圖所示，遵_金θ 丨 ^ /f 42ί 將導電通路自晶片408之導電電極410延伸至承 4〇〇之下表面404a上，可增加封裝體内連線的佈 / 使輸出/輸入連接（I/O)之密度降低。隨著晶片4〇8 / ’ 斷地縮小化’本發明實施例所提供之方法及結構，、不 有效舒缓過於密集的導電通路佈局，使電子元 更可 之製作難度降低而有較高的良率。此外，還可二裝體 成上保護層於承載基底4〇〇上，如第4L 步用 晶片408為光電元件時，上保護層436較佳:。含 明的上封裝層412上，以使光線能順利進人或射覆羞於透 在^述使用穿承載基底之穿孔結構的實施°， 、不必對晶片進行穿孔製程，可以降彳 由 率。同時，由於只對承載基底進行穿孔，因::片另= 9002-A33 562TWF/jychen 只 201034132 " 施例中，薄化步驟可以省略或者實施薄化製程但並不需 要露出晶片408的部份表面，如第5圖所示之封裝體結 構，其中相同之元件採用與第4圖相同之標號。 本發明實施例具有許多優點，透過穿晶片或穿承載 基底之穿孔，可將導電通路導引至其他平面，可有效舒 緩過於密集的導電通路佈局。在其他實施例中，透過由 液態固化的上封裝層作為所封裝晶片之上封裝層，更可 使封裝體之結構更為穩固可靠。尤其對光電晶片之封 ❹ 裝，由液態固化的上封裝層更可提供所需的透光率。 雖然本發明已以數個較佳實施例揭露如上，然其並 非用以限定本發明，任何所屬技術領域中具有通常知識 者，在不脫離本發明之精神和範圍内，當可作任意之更 動與潤飾，因此本發明之保護範圍當視後附之申請專利 範圍所界定者為準。The fill layer 416 is over and extends onto the upper surface 402. The circuit redistribution layer is electrically connected to the conductive electrode 410. The electronic component package 44A further includes a via 422'. The via 422 has a conductive layer 428 formed on the sidewall thereof. The conductive layer may further extend onto the lower surface 404a and be electrically connected to the conductive electrode 410 through the wiring redistribution layer w. As shown in FIG. 4L, the conductive path extends from the conductive electrode 410 of the wafer 408 to the lower surface 404a of the substrate 408, thereby increasing the wiring of the package body/output. The density of the input connection (I/O) is reduced. The method and structure provided by the embodiment of the present invention are not effective in relieving the layout of the conductive path which is too dense, so that the electronic element can be made more difficult to manufacture and has a higher quality. rate. In addition, an upper protective layer may be further disposed on the carrier substrate 4, and when the 4L step wafer 408 is a photovoltaic element, the upper protective layer 436 is preferably: The upper encapsulation layer 412 is provided so that the light can be smoothly entered or shattered. The implementation of the perforated structure using the carrier substrate can be performed without puncturing the wafer. At the same time, since only the bearing substrate is perforated, because:: sheet = 9002-A33 562TWF/jychen only 201034132 " In the example, the thinning step can omit or implement the thinning process but does not need to expose the portion of the wafer 408 The surface, such as the package structure shown in Fig. 5, wherein the same elements are given the same reference numerals as in Fig. 4. Embodiments of the present invention have a number of advantages. By penetrating through the wafer or through the perforations of the carrier substrate, the conductive vias can be routed to other planes, which can effectively relieve the layout of the conductive channels that are too dense. In other embodiments, the upper encapsulation layer solidified by the liquid is used as the encapsulation layer on the packaged wafer, and the structure of the package is more stable and reliable. Especially for the mounting of photovoltaic wafers, the liquid-cured upper encapsulation layer provides the desired light transmittance. While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.
9002-A33562TWF/jychen 24 201034132 【圖式簡單說明】 第1A-1D圖顯示本發明實施例之電子元件封裝體的 一系列製程剖面圖。 第2A-2C圖顯示本發明另一實施例之電子元件封裝 體的一系列製程剖面圖。 第3A-3L圖顯示本發明實施例中具有穿矽通孔之封 裝結構的一系列製程剖面圖。 第4A-4L圖顯示本發明另一實施例中，具有穿矽通 ❿ 孔之封裝結構的一系列製程剖面圖。 第5圖顯示本發明另一實施例中，具有穿矽通孔之 封裝結構剖面圖。 102〜第一表面； 106〜電子元件； 108a、108c〜液態材料 114〜導電結構； 【主要元件符號說明】 100〜基底； 104〜第二表面； 108〜上封裝層；9002-A33562TWF/jychen 24 201034132 [Brief Description of the Drawings] Figs. 1A-1D are a series of process sectional views showing an electronic component package according to an embodiment of the present invention. Fig. 2A-2C is a cross-sectional view showing a series of processes of an electronic component package according to another embodiment of the present invention. 3A-3L is a cross-sectional view showing a series of processes having a package structure for passing through holes in the embodiment of the present invention. 4A-4L is a cross-sectional view showing a series of processes having a package structure through which a through hole is formed in another embodiment of the present invention. Fig. 5 is a cross-sectional view showing a package structure having a through-hole through hole in another embodiment of the present invention. 102~first surface; 106~electronic component; 108a, 108c~ liquid material 114~ conductive structure; [main component symbol description] 100~ substrate; 104~ second surface; 108~ upper encapsulation layer;
10〜紫外光； 110、324、424〜絕緣層； 112〜防銲層； 108b〜粒狀材料； 20〜釭外光； 300、400〜承載基底； 302、402〜上表面； 304、304a、404、404a〜下表面； 306、406〜凹槽； 308、408〜晶片； 314、320、414、420〜黏著層； 9002-A33562TWF/jychen 25 201034132 310、410〜導電電極； 312、412〜上封裝層； 316、416〜填充層； 318、418〜輔助基底； 322、422〜穿孑L ; 326、426〜第一開口； 328、428〜導電層； 330、430、436〜保護層； ❹ 332、432〜第二開口； 334、434〜導電結構； 340、440〜電子元件封裝體； 301、401~開口； 417〜線路重佈層。10~ultraviolet light; 110, 324, 424~ insulating layer; 112~ solder resist layer; 108b~ granular material; 20~釭 external light; 300, 400~ bearing substrate; 302, 402~ upper surface; 304, 304a, 404, 404a~lower surface; 306, 406~groove; 308, 408~ wafer; 314, 320, 414, 420~ adhesive layer; 9002-A33562TWF/jychen 25 201034132 310, 410~ conductive electrode; 312, 412~ Encapsulation layer; 316, 416~fill layer; 318, 418~ auxiliary substrate; 322, 422~through ;L; 326, 426~first opening; 328, 428~ conductive layer; 330, 430, 436~ protective layer; 332, 432~ second opening; 334, 434~ conductive structure; 340, 440~ electronic component package; 301, 401~ opening; 417~ line redistribution layer.
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