HK1186298A - Wire bond interposer package for cmos image sensor and method of making same - Google Patents

Description

Wire bond interposer package for CMOS image sensor and method of manufacturing the same

Technical Field

The present invention relates to packaging of microelectronic devices, and more particularly to packaging of optical semiconductor devices.

Background

The trend in semiconductor devices is for smaller Integrated Circuit (IC) devices (also referred to as chips) to be packaged in smaller packages that protect the chips while providing off-chip signal connectivity. One example is an image sensor, which is an IC device that includes a photodetector that converts incident light into an electrical signal, which accurately reflects the intensity and color information of the incident light with good spatial resolution.

There are different driving forces behind the development of wafer-level packaging schemes for image sensors. For example, a reduced form factor (i.e., increased density, to achieve the highest volume/volume ratio) overcomes space limitations and enables smaller camera module solutions. Increased electrical performance can be achieved with shorter interconnect lengths, which can improve electrical performance and hence device speed, and which greatly reduces chip power consumption. Heterogeneous integration allows integration of different functional layers (e.g., integration of high resolution and low resolution image sensors, integration of image sensors with their processors, etc.). Cost reduction per unit package can be achieved by packaging only those chips that are known to be good (i.e., packaging only the die-KGD that is known to be good).

Currently, chip-on-board (COB), in which a die is directly mounted on a printed circuit board, and sierra (Shellcase) wafer-level CSP, in which a wafer is laminated between two glass sheets, are mainstream packaging and assembly processes used to construct image sensor modules (e.g., for mobile device cameras, optical mice, etc.). However, with the use of higher pixel image sensors, COB and Shellcase WLCSP assembly becomes increasingly difficult due to capital expenditure, assembly limitations, size limitations (which is required for lower profile devices), and yield issues for packaging 8 and 12 inch image sensor wafers. For example, the Shellcase WLCSP technique involves packaging the image sensors on the wafer before the wafer is singulated into individual packaged chips, meaning that those chips from each wafer that are defective are still packaged (which drives up cost) before they can be tested. In addition, standard WLP packages are fan-in packages, where the chip area is equal to the package area, thus limiting the number of I/O connections. Finally, standard WLP packages are bare die packages, which can be complex in test handling, assembly, and SMT.

There is a need for improved packaging and packaging techniques for chips such as image sensors that have been singulated and tested, and which provide a cost-effective and reliable low-profile packaging solution (i.e., provide the necessary mechanical support and electrical connectivity).

Disclosure of Invention

In one aspect of the invention, an image sensor package includes a handler assembly, a sensor chip, and a substrate. The handler assembly includes a crystal handler having opposing first and second surfaces, wherein the crystal handler includes: a cavity formed into the first surface such that the cavity has a stepped sidewall defining at least one stepped surface extending inwardly into the cavity; and a plurality of conductive elements each extending from the at least one step surface to the second surface through the crystal handler. The sensor chip is disposed in the cavity and includes a substrate having front and back opposing surfaces, a plurality of photodetectors formed at the front surface, and a plurality of contact pads formed at the front surface electrically coupled to the photodetectors. A plurality of wires each extend between and electrically connect one of the contact pads and one of the conductive elements. A substrate is disposed on the cavity and mounted to the crystal handler, wherein the substrate is optically transparent to at least one range of light wavelengths.

Another aspect of the invention is a method of packaging a sensor chip that includes a substrate having front and back opposing surfaces, a plurality of photodetectors formed at the front surface, and a plurality of contact pads formed at the front surface that are electrically coupled to the photodetectors. The method comprises the following steps: providing a crystal handler having opposing first and second surfaces; forming a cavity into a first surface such that the cavity has a stepped sidewall defining at least one stepped surface extending inwardly into the cavity; forming a plurality of conductive elements each extending through the crystal handler from the at least one step surface to a second surface; inserting a sensor chip into the cavity; attaching a plurality of wires between the sensor chip and the plurality of conductive elements such that each wire extends between and electrically connects one of the contact pads and one of the conductive elements; and mounting the substrate to the crystal handler such that the substrate is disposed on the cavity, wherein the substrate is optically transparent to at least one range of light wavelengths.

Another aspect of the invention is a method of forming a plurality of image sensor packages by: providing a crystal handler having opposing first and second surfaces; forming a plurality of cavities into a first surface such that each of the cavities has a stepped sidewall defining at least one stepped surface extending inwardly into the cavity; for each of the cavities, forming a plurality of conductive elements each extending from the at least one step surface to the second surface through the crystal handler; inserting a sensor chip into each of the cavities (wherein each of the sensor chips includes a substrate having front and back opposing surfaces, a plurality of photodetectors formed at the front surface, and a plurality of contact pads formed at the front surface electrically coupled to the photodetectors); for each of the respective sensor chip and cavity, affixing a plurality of wires between the sensor chip and the plurality of conductive elements such that each wire extends between and electrically connects one of the contact pads and one of the conductive elements; mounting a substrate to a crystal handler such that the substrate is disposed on a cavity, wherein the substrate is optically transparent to at least one range of light wavelengths; and dicing the crystal handler and the substrate to form separate packages each including one of the cavities and one of the sensor chips therein.

Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.

Drawings

Fig. 1A-1E are cross-sectional side views illustrating in sequence the steps of forming a handler assembly.

Fig. 2A-2D are cross-sectional side views sequentially showing steps of singulating an image sensor chip.

Fig. 3A-3C are cross-sectional side views illustrating an integrated handler assembly and image sensor chip.

Fig. 4A is a cross-sectional side view of the handler assembly, transparent substrate and image sensor chip integrated prior to singulation.

Fig. 4B is a cross-sectional side view of the handler assembly, transparent substrate, and image sensor chip integrated after singulation.

Fig. 5 is a cross-sectional side view of an alternative embodiment of an integrated handler assembly, transparent substrate and image sensor chip, wherein the transparent substrate includes a lens integrally formed on its top surface.

Detailed Description

The invention is a package for microelectronic devices, especially image sensors. The present invention employs modularity of its components to increase yield, reduce cost, and improve yield. There are three main components for the package design, which are formed using wafer-level technology:

1. a handler assembly 2 having a pre-formed circuit;

2. a singulated image sensor chip 4;

3. an optically transparent substrate 60.

Each component was separately fabricated, separately stored and separately tested. Only known good components allow for integration of the package.

The formation of the handler assembly 2 is shown in fig. 1A-1E and begins with a crystal handler 10, which crystal handler 10 includes top and bottom surfaces 12 and 14, respectively, as shown in fig. 1A. First cavity 16 is formed into top surface 12 of handler 10. The cavity 16 may be formed by using a laser, by a plasma etching process, by a sand blasting process, by a mechanical grinding process, or by any other similar method. Preferably, the cavity 16 is formed by performing a photolithographic plasma etching process that removes selectively exposed portions of the handler 10. The plasma etch may be anisotropic, tapered, isotropic, or a combination thereof. The second cavity 18 is then formed into the bottom surface of the first cavity 16 using any of the techniques listed above for the first cavity 16. Preferably (but not necessarily) the depth of the second cavity 18 is equal to or greater than the thickness of the image sensor chip 4, so that the sensor chip 4 can be mostly or completely enclosed within the second cavity 18. The transverse dimensions (i.e., diameter, width, etc.) of the second cavity 18 are smaller than the transverse dimensions of the first cavity 16, resulting in a stepped sidewall 20. The stepped sidewall 20 includes a step 22, the step 22 extending laterally outward to the center of the cavity 16/18 to define a substantially laterally extending step surface 22a (i.e., the remainder of the bottom surface of the cavity 16), the step surface 22a terminating at a substantially vertically extending surface 22 b. Preferably, the step 22 is continuous around the circumference of the first cavity 16 (i.e. the step 22 is in the form of an annular shoulder defining the opening of the second cavity 18 at the bottom surface of the first cavity 16). However, a plurality of discrete steps 22 may be formed, the plurality of discrete steps 22 extending inwardly to the center of the first cavity 16 at discrete locations. The cavities 16 and 18 may be considered as a single cavity 19 formed into the top surface 12 (i.e., wherein the first cavity portion 16 is disposed higher than the step surface 22a and the second cavity portion 18 is disposed lower than the step surface 22 a), having a stepped sidewall defining at least one step surface 22a extending inwardly into the cavity. The resulting structure is shown in fig. 1B.

A through hole 24 is formed, the through hole 24 extending from the step surface 22a of the step 22 to the bottom surface 14 through the handler 10. The through-holes 24 may be formed by using a laser, by a plasma etching process, by a sand blasting process, by a mechanical grinding process, or by any other similar method. Preferably, vias 24 are formed by photolithographic plasma etching that includes forming a photoresist layer on handler 10, patterning the photoresist layer to expose select portions of handler 10, and then performing a plasma etch process (e.g., a BOSCH process, which utilizes SF)₆And C₄F₈A combination of gases) to remove the exposed portions of the handler 10 to form the through-holes 24. Preferably, each through-hole 24 has a diameter between 5 and 250 μm, and a sidewall angle of 45 to 90 degrees with respect to the bottom surface 14. An isolation (dielectric) layer 26 is then deposited on the exposed surfaces of the handler, including within the holes 24 and cavities 19. Dielectric layer 26 may be silicon oxide, silicon nitrideEpoxy, polyimide, resin, FR4, or any other suitable dielectric material. Preferably, dielectric layer 26 is at least 0.1 μm thick and is formed using any conventional dielectric layer deposition technique (which is well known in the art). The resulting structure is shown in fig. 1C.

A conductive material (e.g., Cu, Ti/Al, Cr/Cu, Cr/Al, and/or any other well-known conductive material) is deposited on dielectric layer 26, filling vias 24 with the conductive material or lining vias 24. The printing may be by sputtering, electroplating, dispensing printing, or a combination of sputtering, electroplating and dispensing printing. A photolithographic step is then used to remove portions of the conductive material on portions of the top and bottom surfaces 12/14 and inside the cavity 19, leaving conductive elements or traces 28 extending through the vias 24 and terminating in conductive pads 30a and 30b at the step surface 22a and surface 14, respectively. Conductive pads 30a and 30b have lateral dimensions that are greater than the lateral dimensions of conductive element 28 (to facilitate forming electrical connections thereto), and may optionally extend along step surfaces 22a and/or 14 to route connections to suit particular design requirements. The resulting structure is shown in fig. 1D.

An encapsulant (dielectric) layer 32 is then deposited on the bottom surface 14. Dielectric layer 32 may be epoxy-based, polyimide, resin, FR4, or any other suitable dielectric material. Preferably, dielectric layer 26 is at least 1.0 μm thick and is formed using any conventional deposition technique (which is well known to those skilled in the art). Portions of layer 32 over conductive pads 30b are then removed using a photolithographic process. SMT (surface mount) interconnects 34 are then formed on bottom surface 14 in such a way that they are in electrical contact with respective conductive pads 30 b. The SMT interconnect 34 may be of BGA type and may be formed using a screen printing process of solder alloy, or by a ball-planting process, or by an electroplating process. BGA (ball grid array) interconnects are circular conductors formed, typically by soldering or partially melting metal balls onto bond pads, for making physical and electrical contact with a counterpart conductor. Alternatively, the SMT interconnect 34 may be a conductive metal pillar (e.g., copper). The final handler assembly 2 structure is shown in fig. 1E.

The formation of the singulated image sensor chips 4 is shown in fig. 2A-2D and starts with a wafer 42 having a front surface 43 on which a plurality of sensors 44 have been formed. Each sensor includes a plurality of photodetectors 46 (and supporting circuitry), and contact pads 48. Photodetectors 46 (and supporting circuitry) and contact pads 48 are formed at the upward-facing (front) surface of wafer 42, as shown in fig. 2A. The contact pads 48 are electrically connected to the photo detector 46 (and/or their supporting circuitry) for providing chip signaling. Each photodetector 46 converts light energy into a voltage signal. Additional circuitry may be included to amplify the voltage and/or convert it to digital data. Color filters and/or microlenses 50 may be mounted on the photodetector 46. Sensors of this type are well known in the art and will not be described further herein.

Dicing tape 52 is mounted on the back side of the image sensor wafer 42. Dicing tape 52 may be any tape or carrier made of PVC, polyolefin, polyethylene, ceramic, or crystalline substrate material with an adhesive to hold the die in place. Dicing tape 52 is typically available in a variety of thicknesses (e.g., from 25 to 1000 μm) and a variety of adhesive strengths, which are designed for a variety of chip sizes and materials. A partial cut (pre-cut) of the shallow scribe line area (scribe lane) is then performed. Partial dicing includes cutting scribe lines 54 (i.e., trenches, channels, grooves, slits, etc.) into the front surface 43 of the wafer 42. The cutting step may be accomplished using a dicing saw, laser, or etching process. Preferably, the dicing step is accomplished with a dicing saw having a 25 to 50 μm wide cutting edge, wherein the depth of the scribe line 54 extends no more than 30% of the thickness of the wafer 42. The resulting structure is shown in fig. 2B.

A temporary (sacrificial) protective layer 56 is then mounted onto the front side of the wafer 42 and the dicing tape 52 is removed from the back side of the wafer 42, as shown in fig. 2C. Temporary protective layer 56 may be made of PVC, polyolefin, polyethylene, ceramic, or crystalline substrate material, with the die being held in place with an adhesive after the dicing tape is removed. The wafer 42 is then thinned from the back side, preferably using a wafer grinding and/or silicon etching process, until die separation has been completed (i.e., the sensors 44 are separated so that each is on its own die). The protective layer 56 is then removed, leaving the final image sensor chip 4, as shown in fig. 2D. The sensors 44 are then tested individually, so that only known good sensor chips 4 are packaged. Alternatively, the sensor 44 may be tested before the sensor chip 4 is removed from the protective layer 56, wherein only known good sensor chips 4 are removed from the protective layer 56 and placed in a tray for future assembly.

The separately formed handler assembly 2 and the known good image sensor chip 4 are then integrated together as shown in fig. 3A-3C, whereby the sensor chip 4 is placed in the cavity 19 and attached to the handler assembly 2. Any conventional die attach process (e.g., conventional pick and place techniques) may be used, whereby a die attach material 56 (e.g., a non-conductive adhesive film or epoxy, etc. having a nominal thickness of 1 to 25 microns and the ability to withstand curing temperatures of up to 250C) is used to affix the sensor chip 4 to the bottom surface of the second cavity 18, as shown in fig. 3A. Preferably, but not necessarily, the front surface 43 of the image sensor chip 4 is aligned (i.e., flush) with the step surface 22a to more facilitate wire bonding as described later. A wire bonding process is then performed in which wires 58 connect between contact pads 48 of image sensor chip 4 and corresponding conductive pads 30a of handler assembly 2 (and provide electrical connections between contact pads 48 of image sensor chip 4 and corresponding conductive pads 30a of handler assembly 2), as shown in fig. 3B. Wire 58 may be alloyed gold, copper, or any other suitable wire bonding material and is formed by utilizing any conventional wire bonding technique, which is well known in the art.

An optically transparent substrate 60 is mounted to the top surface 12 of the handler 10 such that the substrate 60 is disposed on the image sensor chip 4. Preferably, the substrate 60 seals the opening of the cavity 19. The substrate 60 may be made of polycrystalline ceramics (e.g., aluminum oxide ceramics, aluminum oxynitride, perovskites (perovskites), polycrystalline yttrium aluminum garnet, etc.), single crystal ceramics, amorphous materials (e.g., inorganic glasses and polymers), glass ceramics (e.g., silicate-based), etc., and is optically transparent to at least one range of light wavelengths. The substrate 60 may be attached to the top surface 12 using a bonding material 62. Bonding material 62 may be a metal matrix, epoxy, polyimide, resin, or any other suitable bonding material. The resulting structure is shown in fig. 3C.

The transparent substrate 60 and handler assembly 2 of the assembled package structure of fig. 3C provide protection for the sensor chip 4 and provide fan-out array electrical connections. During operation, the sensor 44 receives incident light through the transparent substrate 60. Off-chip conductivity is provided by each of the contact pads 48 on the image sensor chip 4 through the corresponding lines 58, the corresponding conductive pads 30a, the corresponding conductive traces 28, the corresponding conductive pads 30b, and finally through the corresponding surface mount interconnects 34. In order to ease fabrication and ensure that defective parts are removed prior to integration (i.e., only known good parts are preferably passed to final integration), each of the three major components (handler assembly 2, transparent substrate 60, and image sensor chip 4) are fabricated separately, thus increasing yield and yield, and reducing cost.

Preferably, multiple handler assemblies 2 are formed on a single crystal handler 10, and a single transparent substrate 60 is used for the multiple handler assemblies. The integration may thus be performed before or after the handler 10 and substrate 30 are singulated into separate assemblies. If the integration is performed prior to singulation, the pre-singulation structure is shown in FIG. 4A (and dicing tape 52 is mounted to transparent substrate 60). A wafer dicing process (e.g., using wafer dicing and/or laser equipment) is then performed to singulate the assembly, as shown in fig. 4B.

Fig. 5 shows an alternative embodiment in which the top surface 64 of the transparent substrate 60 is non-planar such that it acts as a lens for light entering the substrate 60. The distance between the lens substrate 60 and the active surface of the sensor 44 is fixed and can be optimized during assembly by varying the thickness of the bonding material 62.

It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of the appended claims. For example, reference herein to the invention is not intended to limit the scope of any claim or claim term, but instead merely to reference one or more features that may be covered by one or more claims. The above-described materials, processes, and numerical examples are illustrative only and should not be construed as limiting the claims. Moreover, it is apparent from the claims and specification that not all method steps must be performed in the exact order illustrated or claimed, but rather in any order, individually or simultaneously, that allows for the proper formation of the image sensor package of the present invention. A single layer of material may be formed as multiple layers of this or similar materials, and vice versa.

It should be noted that the terms "over" and "upper" as used herein, both inclusively include "directly on …" (with no intervening material, element, or space disposed therebetween) and "indirectly on …" (with an intervening material, element, or space disposed therebetween). Likewise, the term "adjacent" includes "directly adjacent" (no intermediate material, element, or space disposed therebetween) and "indirectly adjacent" (with intermediate material, element, or space disposed therebetween), "mounted to" includes "directly mounted to" (no intermediate material, element, or space disposed therebetween) and "indirectly mounted to" (with intermediate material, element, or space disposed therebetween), and "electrically coupled" includes "directly electrically coupled to" (no intermediate material or element therebetween that electrically connects the elements together) and "indirectly electrically coupled to" (intermediate material or element therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intervening materials/elements therebetween, or forming the element indirectly on the substrate with one or more intervening materials/elements therebetween.

Claims (26)

1. An image sensor package, comprising:

a handler assembly, the handler assembly comprising:

a crystal handler having opposing first and second surfaces, wherein the crystal handler includes a cavity formed into the first surface such that the cavity has a stepped sidewall defining at least one stepped surface extending inwardly into the cavity, and

a plurality of conductive elements each extending from the at least one step surface to a second surface through the crystal handler;

a sensor chip disposed in the cavity, wherein the sensor chip comprises:

a substrate having front and rear opposing surfaces,

a plurality of photodetectors formed at the front surface, an

A plurality of contact pads formed at the front surface that are electrically coupled to the photodetectors;

a plurality of wires each extending between and electrically connecting one of the contact pads and one of the conductive elements; and

a substrate disposed on the cavity and mounted to the crystal handler, wherein the substrate is optically transparent to at least one range of light wavelengths.

2. The image sensor package of claim 1, further comprising:

a plurality of surface mount interconnects each disposed on the second surface of the crystal handler and each electrically connected to one of the conductive elements.

3. The image sensor package of claim 2 wherein, for each conductive element:

the conductive element terminates at the at least one step surface in a first conductive pad, wherein one of the lines is connected to the first conductive pad; and

the conductive element terminates at a second surface in a second conductive pad, wherein one of the surface mount interconnects is connected to the second conductive pad;

wherein the first and second conductive pads each have a lateral dimension that is greater than a lateral dimension of the conductive element.

4. The image sensor package of claim 1, wherein the sensor chip further comprises:

a plurality of color filters and microlenses mounted on the photodetectors.

5. The image sensor package of claim 1 wherein the substrate has a surface that: a portion of the surface is disposed on the photodetector and is non-planar.

6. The image sensor package of claim 1 wherein the plurality of conductive elements are insulated from the crystal handler by a dielectric material.

7. The image sensor package of claim 1, wherein:

the cavity has a first portion disposed higher than the step surface and a second portion disposed lower than the step surface;

the second portion has a lateral dimension that is less than a lateral dimension of the first portion; and

the sensor chip is disposed in the second portion.

8. The image sensor package of claim 7 wherein the sensor chip is disposed entirely within the second portion.

9. A method of packaging a sensor chip, the image sensor including a substrate having front and back opposing surfaces, a plurality of photodetectors formed at the front surface, and a plurality of contact pads formed at the front surface that are electrically coupled to the photodetectors, the method comprising:

providing a crystal handler having opposing first and second surfaces;

forming a cavity into a first surface such that the cavity has a stepped sidewall defining at least one stepped surface extending inwardly into the cavity;

forming a plurality of conductive elements each extending through the crystal handler from the at least one step surface to a second surface;

inserting a sensor chip into the cavity;

attaching a plurality of wires between the sensor chip and the plurality of conductive elements such that each wire extends between and electrically connects one of the contact pads and one of the conductive elements; and

mounting a substrate to the crystal handler such that the substrate is disposed on the cavity, wherein the substrate is optically transparent to at least one range of light wavelengths.

10. The method of claim 9, further comprising:

a plurality of surface mount interconnects are formed, each disposed on the second surface of the crystal handler and each electrically connected to one of the conductive elements.

11. The method of claim 10, wherein each of the plurality of conductive elements is formed such that:

the conductive element terminates at the at least one step surface in a first conductive pad, wherein one of the lines is connected to the first conductive pad; and

the conductive element terminates at a second surface in a second conductive pad, wherein one of the surface mount interconnects is connected to the second conductive pad;

wherein the first and second conductive pads each have a lateral dimension that is greater than a lateral dimension of the conductive element.

12. The method of claim 9, wherein the substrate has a surface that: a portion of the surface is disposed on the photodetector and is non-planar.

13. The method of claim 9, further comprising:

a dielectric material is formed between the plurality of conductive elements and the crystal handler.

14. The method of claim 9, wherein forming a cavity comprises:

forming a first portion of the cavity into the first surface, wherein the first portion has a first lateral dimension and a bottom surface;

forming a second portion of the cavity into the bottom surface of the first portion, wherein the second portion has a second lateral dimension that is smaller than the first lateral dimension, wherein at least a portion of the bottom surface remains after forming the second portion and which constitutes the at least one step surface.

15. The method of claim 14, wherein inserting the sensor chip into the cavity comprises inserting the sensor chip into the second portion of the cavity.

16. The method of claim 14, wherein inserting the sensor chip into the cavity comprises inserting the sensor chip fully within the second portion of the cavity.

17. The method of claim 9, wherein forming each of the conductive elements comprises:

forming a hole extending from the at least one step surface to the second surface;

forming an insulating material along sidewalls of the hole; and

a conductive material is deposited in the holes.

18. A method of forming a plurality of image sensor packages, comprising:

providing a crystal handler having opposing first and second surfaces;

forming a plurality of cavities into a first surface such that each of the cavities has a stepped sidewall defining at least one stepped surface extending inwardly into the cavity;

for each of the cavities, forming a plurality of conductive elements each extending from the at least one step surface to the second surface through the crystal handler;

inserting a sensor chip into each of the cavities, wherein each of the sensor chips comprises:

a substrate having front and rear opposing surfaces,

a plurality of photodetectors formed at the front surface, an

A plurality of contact pads formed at the front surface, the plurality of contact pads electrically coupled to the photodetector;

for each of the respective sensor chip and cavity, affixing a plurality of wires between the sensor chip and the plurality of conductive elements such that each wire extends between and electrically connects one of the contact pads and one of the conductive elements;

mounting a substrate to a crystal handler such that the substrate is disposed on a cavity, wherein the substrate is optically transparent to at least one range of light wavelengths; and

the crystal handler and the substrate are diced to form separate packages each including one of the cavities and one of the sensor chips therein.

19. The method of claim 18, further comprising:

a plurality of surface mount interconnects are formed, each disposed on the second surface of the crystal handler and each electrically connected to one of the conductive elements.

20. The method of claim 18, wherein the portion of the top surface of the substrate disposed on the sensor chip is non-planar, wherein the substrate has a surface that: portions of the surface are each disposed on one of the photodetectors and are non-planar.

21. The method of claim 18, wherein for each of the cavities, each of the plurality of conductive elements is formed such that:

the conductive element terminates at the at least one step surface in a first conductive pad, wherein one of the lines is connected to the first conductive pad; and

the conductive element terminates at a second surface in a second conductive pad, wherein one of the surface mount interconnects is connected to the second conductive pad;

wherein the first and second conductive pads each have a lateral dimension that is greater than a lateral dimension of the conductive element.

22. The method of claim 18, further comprising:

a dielectric material is formed between the plurality of conductive elements and the crystal handler.

23. The method of claim 18, wherein forming each of the cavities comprises:

forming a first portion of the cavity into the first surface, wherein the first portion has a first lateral dimension and a bottom surface;

forming a second portion of the cavity into the bottom surface of the first portion, wherein the second portion has a second lateral dimension that is smaller than the first lateral dimension, and wherein at least a portion of the bottom surface remains after forming the second portion and constitutes the at least one step surface.

24. The method of claim 23, wherein inserting the sensor chip into the cavity comprises inserting the sensor chip into the second portion of the cavity.

25. The method of claim 23, wherein inserting the sensor chip into the cavity comprises inserting the sensor chip fully within the second portion of the cavity.

26. The method of claim 18, wherein for each of the cavities, forming each of the conductive elements comprises:

forming a hole extending from the at least one step surface to the second surface;

forming an insulating material along sidewalls of the hole; and

a conductive material is deposited in the holes.