200950046 .* 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電子元件封裝體（electronics package)，特別是有關於一種利用晶圓級封裝（wafer scale package; WSP)製程製作之電子元件封裝體及其製作方 法。 【先前技術】 ❿ 光感測積體電路在擷取影像的光感測元件中係扮演 著重要的角色，這些積體電路元件均已廣泛地應用於例 如是數位相機（digital camera; DC)、數位攝錄像機（digital recorder)和手機（cell phone)等的消費電子元件和攜帶型 電子元件中。 第1圖顯示一種習知之影像感測元件（image sensor) 封裝體1的剖面圖。在第1圖中，一基底2,其上方形 成有感光元件4及接合墊6,以及一蓋板8設置於上述基 ❹底2的上方。又如第1圖所示，一承載板9貼合至基底2, 以及一銲球12設置於此承載板9的背面上，且藉由一導 電層10電性連接接合墊6。上述感光元件4可藉由其正 面感應穿過蓋板8的光，以產生一訊號，且藉由導電層 10將此訊號傳遞至銲球12及一外部電路。 【發明内容】 本發明之一實施例係提供一種電子元件封裝體。上 述電子元件封裝體，包含：一半導體晶片，具有一第一 9002-A33417TWF/X07-056/yungchieh 5 200950046 -* 基底、一與此第一基底間隔一既定距離之支撐塊，以及 一接合墊，具有一表面，其橫跨於第一基底與支樓塊上。 在另一實施例中，上述第一基底，具有一第一表面及一 相對之第二表面，其中此第二表面作為一受光面，而第 一表面作為一背光面，且_包含一感光元件區。上述電子 元件封裝體，可更包含：一第二基底，接合至第一基底 的背光面；一第一封裝層，覆蓋上述第一基底之受光面； 一第二封裝層，覆蓋上述第二基底；一導線層，形成於 ❹上述第二封裝層上，且延伸至接合墊及支撐塊的側面 上，以電性連接接合墊；以及一導電凸塊，設置於上述 第二封裝層上，且電性連接上述導線層。 在上述電子元件封裝體中，由於，在支撐塊與第一 基底之間會有一絕緣層，藉此以隔離支撐塊與第一基 底，並且上述接合墊會橫跨於此絕緣層上。因此，形成 於支撐塊側面上的導線層並不會影響感光元件。再者， 由於，上述電子元件具有支撐塊，其可增加導線層與接 ® 合墊間的結構強度（τ接觸的結構強度）。藉此，可增強上 述電子元件封裝體整體的結構強度。 本發明另一實施例係提供一種電子元件封裝體的製 作方法。上述電子元件封裝體的製作方法，包含：提供 一晶圓，其具有包含多個晶粒區之基底，以承載或形成 多顆半導體晶片，且多個接合墊形成於此基底上，以及 對此基底進行一晶圓級封裝製程，包含：圖案化此基底， 以在每個晶粒區隔離出一支撐塊，使此支撐塊與基底間 9002-A33417TWF/X07-056/yungchieh 6 200950046 ， 隔一既定距離，並暴露接合墊。上述製作方法更包含藉 由上述圖案化步驟，形成一圖案開口於基底之中，以暴 露接合墊。 在上述製作方法中，半導體晶片包含光電元件，且 晶圓級封裝製程，更包含：以此基底為第一基底，其具 有一第一表面及一相對之第二表面，其中第一表面作為 背光面，而第二表面作為出光面或受光面；設置一第一 封裝層，以覆蓋上述第一基底之出光面或受光面；接合 ⑩ 此第一基底之背光面至一第二基底；以及，沿著兩晶粒 區間之預定切割道的位置，分離此第二基底，以形成多 個對應晶粒區之承載板。 在上述製作方法中，晶圓級封裝製程，更包含：形 成一絕緣層，以至少包覆上述承載板的侧面；設置一第 二封裝層，以覆蓋此第二基底及絕緣層；在兩晶粒區間 之預定切割道的位置，形成一通道凹口，並暴露第一封 裝層的表面；形成一導線層於上述第二封裝層上，且沿 ® 著上述通道凹口，延伸至接合墊與支撐塊的側面上，以 電性連接接合墊；設置一導電凸塊於上述第二封裝層 上，且電性連接導線層；以及沿上述預定切割道，分離 第一封裝層。 在上述電子元件封裝體的製作方法中，由於，上述 圖案開口可同時隔離光電元件及提供檢測光電元件之開 口，因而不需要額外的隔離或製作開口的步驟，因此， 可縮短及簡化製作流程。 9002-A33417TWF/X07-056/yungchieh 7 200950046 【實施方式】 接下來’藉由實施例配合圖式，以詳細說明本發明 概念及具體貫施的方式。在圖式或描述中，相似或相同 部份之元件係使用相同之符號。此外，在圖式中，實施 例之元件的形狀或厚度可擴大，以簡化或是方便標示。 可以了解的是’未繪示或描述之元件，可以是具有各種 熟習該項技藝者所知的形式。 β 本發明係以一製作影像感測元件封裝體（image sensor package)，例如是背後感光式（back side illumination; BSI)之感測元件的實施例作為說明。然而， 可以了解的是，在本發明之封裝體實施例中，其可應用 於各種包含主動元件或被動元件（active or passive elements)、數位電路或類比電路（digital or analog circuits) 等積體電路的電子元件（electronic components)，例如是 有關於光電元件（opto electronic devices)、微機電系統 ❹（Micro Electro Mechanical System; MEMS)、微流體系統 (micro fluidic systems)、或利用熱、光線及壓力等物理量 變化來測量的物理感測器（Physical Sensor)。特別是可選 擇使用晶圓級封裝（wafer scale package; WSP)製程對影 像感測元件、發光二極體（light-emitting diodes; LEDs)、 太陽能電池（solar cells)、射頻元件（RF circuits)、加速計 (accelerators)、陀螺儀（gyroscopes)、微制動器（micro actuators)、表面聲波元件（surface acoustic wave 9002-A33417TWF/X07-056/yungchieh 8 200950046 • devices)、壓力感測器（process sens〇rs)或喷墨頭（ink printer heads)等半導體晶片進行封裝。 其中上述晶圓級封裝製程主要係指在晶圓階段完成 封裝步驟後，再予以切割成獨立的封裝體，然而，在一 特定實施例中，例如將已分離之半導體晶片重新分布在 一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封 裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊 (stack)方式安排具有積體電路之多片晶圓，以形成多層積 ❹體電路（multi-layer integrated circuit devices)之電子元件 封裝體。 第2-11圖顯示根據本發明一實施例之製作影像感測 元件封裝體的示意圖。第12圖顯示根據本發明實施例製 作影像感測元件封裝體的流程圖。 如第2圖所示，提供一晶圓（wafer)或稱晶圓基板 (wafer substrate)，其包含一上方形成有感光元件 (photosensitive devices)102 之第一基底 100，且在此第一 ⑩基底100上方形成有多個接合塾（bonding pads)l 04。其中 上述感光元件102電性連接上述接合墊104,藉此傳遞訊 號至一終端接觸墊（terminal contacts)(未顯示）。接著，形 成一保護層（passivation lay er)l 10於上述第一基底1〇〇 上，且覆蓋接合墊104及感光元件102。 在第2圖中，上述第一基底100可劃分為多個感光 元件區（photosensitive regions)l06及非感光元件區 (non-photo- sensitive regions)108。上述感光元件區 106 9002-A33417TWF/X07-056/yungchieh 9 200950046 - 係指形成有上述感光元件102的區域，而非感光元件區 108係指未形成感光元件102的區域（或兩感光元件區間 的位置），且此非感光元件區108也可稱為預定切割道 (predetermined scribe line)，用以定義後續欲切割出個別 獨立之晶粒的位置。此外，上述非感光元件區108係圍 繞感光元件區106。另外，上述感光元件區106也可稱作 晶粒區。 在一實施例中，上述第一基底100可以是石夕或其它 ❿適合的半導體基材。上述感光元件102可以是互補式金 氧半導體元件（CMOS)或電荷輕合元件（charge-couple device; CCD)，用以感測或擷取影像或圖像。此外，上述 接合墊104也可以稱為延伸接合墊（extension pad)或導電 墊（conductive pad)，且較佳可以銅（copper; Cu)、銘 (aluminum; A1)或其它合適的金屬材料。 如第3圖所示，提供一例如是矽或其它適合之半導 體基材的第二基底112,接著，將上述第一基底100翻轉， ® 且接合至第二基底112的表面上，使得感光元件102可 介於第一、第二基底100及112之間。之後，藉由例如 是钱刻（etching)、銑削（milling)、磨削（grinding)或研磨 (polishing)的方式，從第一基底100的背面，薄化第一基 底100至一適當的厚度，使得上述感光元件102可感應 經由第一基底100背面入射的光。也就是說，上述第一 基底100係被薄化至一可允許足夠的光通過的厚度，使 得發光元件102可感應此入射的光，進而產生訊號。據 9002-A33417TWF/X07-056/yungchieh 10 200950046 • 此，上述研磨後之第一基底100的厚度只要能允許足夠 的光通過，且使得感光元件102產生訊號即可，在此並 不加以限定。 上述第一基底100的正面，係指形成接合墊104或 感光元件102的表面，可稱為一背光面（light back surface)，而其相對的表面（第一基底100的背面），亦可 稱為一受光面（light incident surface)。值得一提的是，在 另一例如是發光二極體之光電元件的實施例中，上述第 ⑩一基底100的背面也可稱作出光面（light-emitting surface)。 第4圖顯示在進行一圖案化步驟後，第一基底100 的局部上視圖。如第4圖所示，在完成薄化步驟後，藉 由微影/#;刻（photolithography/etching)製程，圖案化第一 基底100，以形成一圖案開口（patterned opening) 114於第 一基底100之中，以暴露部分上述接合墊104。且，同時 藉由此圖案開口 114可隔離在上述感光元件區106内的 ® 第一基底100及在非感光元件區108内的第一基底100， 後續稱為隔離之第一基底101。此外，在此圖案化步驟 後，第一基底100或晶圓會被隔離出多顆半導體晶片 (chip) ° 在第4圖中，上述圖案開口 114可以包含一第一開 口 114a、一第二開口 114b及一連通第一開口 114a及第 二開口 114b的溝槽114c。上述第一開口 114a係大體上 暴露部分的接合墊104,以提供檢測感光元件區106内之 9002-A33417TWF/X07-056/yungchieh 11 200950046 感光元件102的開口。上诚筮一 „ π ”〆 、苐一開口 114b係大體上對應 :上述"口 U4a設置，且第二開口⑽具 二2大體上與第一開口 U4a的長度相同。而，上述i ；C位於感光元件區106及非感光元件區1〇8或稱預 疋切割道之間，用以隔離感光元件區1()6内 、 ❹200950046 .* IX. Description of the Invention: [Technical Field] The present invention relates to an electronic package, and more particularly to a wafer scale package (WSP) process. Electronic component package and method of fabricating the same. [Prior Art] ❿ The light sensing integrated circuit plays an important role in the light sensing element that captures images, and these integrated circuit components have been widely used, for example, in digital cameras (DC), In consumer electronic components and portable electronic components such as digital recorders and cell phones. Figure 1 shows a cross-sectional view of a conventional image sensor package 1. In Fig. 1, a substrate 2 having a photosensitive member 4 and a bonding pad 6 formed thereon is formed, and a cover 8 is disposed above the base 2 of the base. As shown in FIG. 1, a carrier board 9 is attached to the substrate 2, and a solder ball 12 is disposed on the back surface of the carrier board 9, and the bonding pad 6 is electrically connected by a conductive layer 10. The photosensitive element 4 can sense light passing through the cover 8 by its front surface to generate a signal, and the signal is transmitted to the solder ball 12 and an external circuit through the conductive layer 10. SUMMARY OF THE INVENTION One embodiment of the present invention provides an electronic component package. The electronic component package includes: a semiconductor wafer having a first 9002-A33417TWF/X07-056/yungchieh 5 200950046-* substrate, a support block spaced apart from the first substrate by a predetermined distance, and a bonding pad. There is a surface that spans the first substrate and the branch block. In another embodiment, the first substrate has a first surface and an opposite second surface, wherein the second surface serves as a light receiving surface, and the first surface serves as a backlight surface, and includes a photosensitive element Area. The electronic component package may further include: a second substrate bonded to the backlight surface of the first substrate; a first encapsulation layer covering the light receiving surface of the first substrate; and a second encapsulation layer covering the second substrate a wire layer formed on the second encapsulation layer and extending to the side of the bonding pad and the support block to electrically connect the bonding pad; and a conductive bump disposed on the second encapsulation layer, and Electrically connecting the above wire layers. In the above electronic component package, since an insulating layer is provided between the support block and the first substrate, the support block and the first substrate are isolated, and the bonding pad may straddle the insulating layer. Therefore, the wiring layer formed on the side of the support block does not affect the photosensitive member. Furthermore, since the above electronic component has a support block, it can increase the structural strength between the wire layer and the bonding pad (the structural strength of the τ contact). Thereby, the structural strength of the entire electronic component package can be enhanced. Another embodiment of the present invention provides a method of fabricating an electronic component package. The manufacturing method of the electronic component package includes: providing a wafer having a substrate including a plurality of die regions to carry or form a plurality of semiconductor wafers, and a plurality of bonding pads are formed on the substrate, and The substrate is subjected to a wafer level packaging process, comprising: patterning the substrate to isolate a support block in each of the die regions, such that the support block and the substrate are 9002-A33417TWF/X07-056/yungchieh 6 200950046, one by one Set the distance and expose the bond pads. The above manufacturing method further comprises forming a pattern opening in the substrate by the patterning step to expose the bonding pad. In the above manufacturing method, the semiconductor wafer includes a photovoltaic element, and the wafer level packaging process further includes: the substrate is a first substrate having a first surface and an opposite second surface, wherein the first surface serves as a backlight a second surface as a light emitting surface or a light receiving surface; a first encapsulating layer disposed to cover the light emitting surface or the light receiving surface of the first substrate; bonding 10 the backlight surface of the first substrate to a second substrate; The second substrate is separated along a predetermined scribe line location of the two die sections to form a plurality of carrier plates corresponding to the die regions. In the above manufacturing method, the wafer level packaging process further includes: forming an insulating layer to cover at least the side surface of the carrier plate; and providing a second encapsulation layer to cover the second substrate and the insulating layer; Positioning the predetermined scribe line of the grain interval to form a channel recess and exposing the surface of the first encapsulation layer; forming a wire layer on the second encapsulation layer, and extending along the channel recess to the bonding pad and a bonding pad is electrically connected to the side of the supporting block; a conductive bump is disposed on the second encapsulation layer, and the wire layer is electrically connected; and the first encapsulation layer is separated along the predetermined cutting channel. In the above method of fabricating the electronic component package, since the pattern opening can simultaneously isolate the photovoltaic element and provide the opening for detecting the photovoltaic element, the step of additionally isolating or making the opening is not required, so that the manufacturing process can be shortened and simplified. 9002-A33417TWF/X07-056/yungchieh 7 200950046 [Embodiment] Next, the concept of the present invention and the specific manner of the present invention will be described in detail by way of embodiments with reference to the drawings. In the drawings or the description, the same or similar components are used in the same symbols. Moreover, in the drawings, the shape or thickness of the elements of the embodiments may be expanded to simplify or facilitate the marking. It will be appreciated that elements that are not shown or described may be in a variety of forms known to those skilled in the art. The present invention is described by way of an embodiment in which an image sensor package, such as a back side illumination (BSI) sensing element, is fabricated. However, it can be understood that in the package embodiment of the present invention, it can be applied to various integrated circuits including active or passive elements, digital circuits or analog circuits. Electronic components, such as opto electronic devices, microelectro mechanical systems (MEMS), micro fluidic systems, or the use of heat, light and pressure, etc. A physical sensor that measures physical quantities to measure. In particular, a wafer scale package (WSP) process can be selected for image sensing components, light-emitting diodes (LEDs), solar cells, RF circuits, Accelerators, gyroscopes, micro actuators, surface acoustic wave components (surface acoustic wave 9002-A33417TWF/X07-056/yungchieh 8 200950046 • devices), pressure sensors (process sens〇rs) Or semiconductor wafers such as ink printer heads are packaged. The above wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in a supporting crystal. On the circle, the encapsulation process can also be called a wafer level packaging process. In addition, the above wafer level packaging process is also applicable to an electronic component package in which a plurality of wafers having integrated circuits are arranged by a stack to form multi-layer integrated circuit devices. 2-11 are schematic views showing the fabrication of an image sensing device package in accordance with an embodiment of the present invention. Figure 12 is a flow chart showing the fabrication of an image sensing device package in accordance with an embodiment of the present invention. As shown in FIG. 2, a wafer or a wafer substrate is provided, which includes a first substrate 100 on which photosensitive elements 102 are formed, and here a first 10 substrate A plurality of bonding pads 104 are formed above 100. The photosensitive element 102 is electrically connected to the bonding pad 104, thereby transmitting a signal to a terminal contact (not shown). Next, a passivation layer 10 is formed on the first substrate 1 , and covers the bonding pad 104 and the photosensitive element 102. In Fig. 2, the first substrate 100 may be divided into a plurality of photosensitive regions 106 and non-photo-sensitive regions 108. The above-mentioned photosensitive element region 106 9002-A33417TWF/X07-056/yungchieh 9 200950046 - refers to a region in which the above-mentioned photosensitive member 102 is formed, and the non-photosensitive device region 108 refers to a region in which the photosensitive member 102 is not formed (or two photosensitive member regions) Position), and this non-photosensitive element region 108 may also be referred to as a predetermined scribe line for defining a position to subsequently cut individual independent dies. Further, the above-described non-photosensitive element region 108 surrounds the photosensitive element region 106. Further, the above-mentioned photosensitive element region 106 may also be referred to as a crystal grain region. In one embodiment, the first substrate 100 may be a suitable semiconductor substrate. The photosensitive element 102 may be a complementary metal oxide semiconductor (CMOS) or a charge-couple device (CCD) for sensing or capturing an image or image. In addition, the bonding pad 104 may also be referred to as an extension pad or a conductive pad, and may preferably be copper (copper), aluminum (A1) or other suitable metal material. As shown in FIG. 3, a second substrate 112, such as a germanium or other suitable semiconductor substrate, is provided, and then the first substrate 100 is flipped over, and bonded to the surface of the second substrate 112 such that the photosensitive member 102 may be interposed between the first and second substrates 100 and 112. Thereafter, the first substrate 100 is thinned to a suitable thickness from the back side of the first substrate 100 by, for example, etching, milling, grinding, or polishing. The photosensitive element 102 is made to sense light incident through the back surface of the first substrate 100. That is, the first substrate 100 is thinned to a thickness that allows sufficient light to pass through, so that the light-emitting element 102 can sense the incident light, thereby generating a signal. According to 9002-A33417TWF/X07-056/yungchieh 10 200950046, the thickness of the first substrate 100 after the above grinding is not limited as long as it allows sufficient light to pass through and causes the photosensitive element 102 to generate a signal. The front surface of the first substrate 100 refers to the surface on which the bonding pad 104 or the photosensitive element 102 is formed, which may be referred to as a light back surface, and the opposite surface (the back surface of the first substrate 100) may also be referred to as It is a light incident surface. It is worth mentioning that in another embodiment of the photovoltaic element such as a light-emitting diode, the back surface of the above-mentioned 10th substrate 100 may also be referred to as a light-emitting surface. Figure 4 shows a partial top view of the first substrate 100 after a patterning step. As shown in FIG. 4, after the thinning step is completed, the first substrate 100 is patterned by a photolithography/etching process to form a patterned opening 114 on the first substrate. 100 is formed to expose a portion of the bonding pad 104 described above. Moreover, the first substrate 100 in the photosensitive element region 106 and the first substrate 100 in the non-photosensitive element region 108, which is hereinafter referred to as the isolated first substrate 101, can be isolated by the pattern opening 114. In addition, after the patterning step, the first substrate 100 or the wafer is separated from a plurality of semiconductor chips. In FIG. 4, the pattern opening 114 may include a first opening 114a and a second opening. 114b and a groove 114c connecting the first opening 114a and the second opening 114b. The first opening 114a is a substantially exposed portion of the bond pad 104 to provide an opening for detecting the 9002-A33417TWF/X07-056/yungchieh 11 200950046 photosensitive element 102 in the photosensitive element region 106. The upper 筮 π π 〆 , 苐 an opening 114 b substantially corresponds to: the above " mouth U4a is set, and the second opening (10) has two 2 substantially the same length as the first opening U4a. The above i; C is located between the photosensitive element region 106 and the non-photosensitive element region 1〇8 or the pre-cutting scribe line for isolating the photosensitive element region 1()6, ❹
，及非感光元件㈣8内的第一基底1〇1。可以了；: 疋’上34®案開D 114可以是任何形狀的設計，只要能 夠同時暴露接合墊，及隔離形成元件區即可，因此，上 返圖^開口的⑤計及第4圖所示並不用來限制本發明。 从第5圖顯示如第4圖所示之影像感測元件封裝體沿 著j-A切線的剖面圖。如第5圖所示，形成圖案開口 ！ μ 於第—基底100之中，以暴露部分接合墊104。此外，藉 由上述圖案開D 114可將第一基底1〇〇與第一基底ι〇ι 彼此隔離。由於，圖案開口 Π4可同時暴露接合墊104 及隔離感光元件區1〇6,因此，可不需進行額外的隔離或 形成供檢測開口的步驟。 如第6圖所示，形成一彩色濾光片116於第一基底 100的背面上，且對應上述感光元件102。接著，設置一 微透鏡(miCr〇-lens) 118於上述彩色濾光片116上。在一實 施例中，上述微透鏡118較佳可以是酚醛樹脂（phenolic reSin)、二聚氰胺（melamine resin)、環氧樹脂（epoxy)或其 它合適的材質。 如第7圖所示’設置一上封裝層（Upper packaging 一er)12〇或稱為蓋板（covering plate)於第一基底100的背 9002-A33417TWF/X07-056/yungchieh 12 200950046 面上。在一實施例中，首先，提供上述上封裝層120，接 著，在此上封裝層120上形成一間隔層（spacer) 122。之 後，形成一接合層（bonding layer)124於間隔層122上， 且將上封裝層120接合至第一基底100,以覆蓋此第一基 底100的背面。上述上封裝層120可以是例如玻璃、石 英（quartz)、蛋白石（opal)、塑膠或其它任何可供光線進出 的透明基板。值得一提的是，也可以選擇性地形成濾光 片（filter)及/或抗反射層（anti-reflective layer)於上封裝層 ❿上。 上述間隔層122可以是環氧樹脂（epoxy)、防銲層 (solder mask)或其它適合之絕緣物質，例如無機材料之氧 化矽層、氮化矽層、氮氧化矽層、金屬氧化物或其組合， 或者是有機局分材料之聚酸亞胺樹脂（polyiniide; PI)、苯 環丁稀（butylcyclobutene; BCB)、聚對二甲苯(parylene)、 萘聚合物（polynaphthalenes)、氟碳化物（fluorocarbons)、 丙稀酸酯（accrylates)等，且此間隔層122可以是利用塗佈 方式，例如旋轉塗佈（spin coating)、喷塗（spray coating) 或淋幕塗佈（curtain coating)，或者是其它適合之沈積方 式，例如液相沈積（liquid phase deposition)、物理氣相沈 積（physical vapor deposition; PVD)、化學氣相沈積 (chemical vapor deposition; CVD)、低壓化學氣相沈積 (low pressure chemical vapor deposition; LPCVD)、電漿增 強式化學氣相沈積（plasma enhanced chemical vapor deposition; PECVD)、快速熱化學氣相沈積（rapid 9002-A33417TWF/X07-056/yungchieh 13 200950046 :thermal-CVD; RTCVD)或常壓化學氣相沈積（atmospheric pressure chemical vapor deposition; APCVD)的方式形 成，以隔絕環境污染或避免水氣侵入。 而’上述接合層124可以是包含高分子膜或者是一 或多種黏著劑，例如環氧化樹脂或聚氨基曱酸酯 (polyurenthane)’且用以將上封裝層120及間隔層Π2接 合至第一基底100。另外，值得注意的是’雖然在圖式中 並未繪示’上述彩色濾光片116、接合層124或間隔層 參 122可填入上述圖案開口 114中，以作為隔離第一基底 100與弟一基底101的絕緣層（insulator)。 如第8圖所示’在完成上述步驟後，藉由一微影/蝕 刻製程，在在沿著各別感光元件區（或稱晶粒區）間之預定 切割道的位置’形成一凹口（notch) 126於第二基底112之 中’以分離此第二基底112,且形成多個對應感光元件區 的承載板。接著’形成一絕緣層（insulating layer) 128，以 包覆第二基底112的侧面及其背面，且設置一下封裝声 應 曰 W (lower packaging layer)130 於第二基底 112 的背面上，以 覆蓋第二基底112及絕緣層128。 在一實施例中，上述絕緣層128可以是是環氧樹脂、 防銲層或其它適合之絕緣物質，例如無機材料之氧化石夕 層、氮化矽層、氮氧化矽層、金屬氧化物或其組合，或 者是有機高分材料之聚醯亞胺樹脂、苯環丁烯、聚對二 甲苯、萘聚合物、氟碳化物、丙烯酸酯等，且此間隔層 122可以是利用塗佈方式，例如旋轉塗佈、喷塗或淋幕塗 9002-A334] 7TWF/X07-056/yungchieh 14 200950046 - 佈，或者是其它適合之沈積方式，例如液相沈積、物理 氣相沈積、化學氣相沈積、低壓化學氣相沈積、電漿增 強式化學氣相沈積、快速熱化學氣相沈積或常壓化學氣 相沈積的方式形成，以隔離第二基底112與後續形成之 導線層。 上述下封裝層130可用來承載第一基底100及第二 基底112,且此下封裝層130可以是具有高導熱能力的基 板，例如石夕基板或金屬基板，但並不以此為限。 © 如第9圖所示，在設置上述下封裝層130後，選擇 性地形成一絕緣層132於此下封裝層130上。之後，進 行一刻痕步驟，以形成一通道凹口（channel notch) 134及 一支樓塊（supporting brick) 101 a。在一實施例中，藉由例 如是刻痕裝置（notching equipment)，沿著預定切割道的位 置，進行刻痕步驟，以形成通道凹口 134，並暴露出上封 裝層120的表面。由於，在切割道的位置會有隔離的第 一基底101(如第8圖所示），當進行刻痕步驟時，第一基 ® 底101會被切割，使得部分的第一基底101會被移除， 且餘留部分的第一基底101，即上述支摟塊101a。 值得注意的是，由於在切割走道會有第一基底101， 當進行刻痕步驟時，可增加封裝體的結構強度，進而避 免此刻痕步驟所引起的損傷，例如元件的龜裂等。此外， 上述支撐塊l〇la的材質並不以矽為限，其材質可以是與 第一基底100的材質相似。 如第10圖所示，形成一導線層（conductive trace 9002-A3 3417TWF/X07-056/yungchieh 15 200950046 -layer) 136於上述下封裝層130的背面上，日、、儿 且，口者通道凹 口 134,延伸至接合塾104及支撐塊i〇la的側面，以電 性連接接合墊104。在一實施例中，藉由例如是電鑛 (electroplating)或濺鍍（sputtering)的方式，順應性地六^^ 例如是銅、鋁、銀（silver; Ag)、鎳（nickel;犯）或其人公的 導電材料層於下封裝層130上’且此導電材料層伸 於下封裝層130、絕緣層128、接合墊1〇4及 久叉存塊1 〇 1 a 的側面上，至通道凹口 134的底部，以電性連接接人塾 Ο 104。之後’藉由例如是微影/蝕刻製程 (photolithography/etching)，圖案化上述導電材料層，以 形成導線層136。 值得一提的是，藉由上述圖案化導電材料層的步 驟’可重新分佈後續形成之導電凸塊的位置，例如可將 導電凸塊從下封裝層的周邊區域擴展到整個下封裝層的 背面，故此導線層136亦可稱為重佈線路層（redistdbuticm layer)。此外，在另一實施例中，上述導線層136可以是 ❹摻雜多晶石夕（doped polysilicon)、單晶石夕或導電玻璃層等 材料，或者是鈦、钥、鉻或鈦鎮之退火金屬材料的沈積 層。 再者，上述支樓塊101 a係藉由填充有絕緣層之圖案 開口 114以與第一基底100隔離，因此，形成於支撐塊 l〇la侧面上的導線層136並不會影響感光元件。 在第10圖中，接著，塗佈一例如是防銲材料（s〇lder mask)的保護層138於導線層136上，且形成—導電凸塊 9002-A33417TWF/X〇7-〇56/yungchieh 16 200950046 (conductive bump)140於下封裝層13〇上，且電性連接導 線層136。在一實施例中，在形成上述保護層138後，圖 案化此保護層138，以形成一暴露部分導線層丨36的開 口，接著，藉由電錢或網版印刷（screen printing)的方式， 將一録料（solder)填入於上述開口中，且進行一迴銲 (re-flow)製程，以形成例如是鋒球（solder ball)或銲塾 (solder paste)的導電凸塊140。在完成上述步驟後，接著， 利用一切割刀，沿預定切割道分離上封裝層120,以切割 © 出一影像感測元件封裝體150，如第11圖所示。 第11圖顯示根據本發明實施例之一影像感測元件封 裝體150的剖面圖。在第11圖中，一半導體晶片，其具 有一第一基底1〇〇、一與此第一基底1〇〇間隔一既定距離 的支撐塊l〇la，以及一接合墊104，具有一表面，其橫 跨於第一基底100及支撐塊l〇la上。又如第11圖所示， 上述第一基底100具有一第一表面及一相對的第二表 面，且一感光元件102製作於第一基底100的第一表面。 ❹一第二基底112接合至第一基底100的第一表面，以及 一上封裝層120及一下封裝層130分別覆蓋第一基底1〇〇 的第二表面及第二基底112。請參閱第11圖所示，一導 線層136形成於下封裝層130的背面上，且延伸至上述 接合墊104及支撐墊101a的側面上，以電性連接接合墊 104，以及一導電凸塊140設置於下封裴層13〇的背面 上，並電性連接此導線層136。 在一實施例中’上述第一基底100的第二表面可作 9002-A33417TWF/X07-056/yungchieh 17 200950046 *' 為一受光面，而形成有感光元件102之第一表面可作為 背光面。外界的光可穿過受光面而至上述感光元件102， 使得感光元件102可感應此穿過第一基底100的光，並 產生一訊號，接著，此訊號可經由接合墊104及導線層 136傳遞至導電凸塊140。 值得注意的是，上述支撐塊與第一基底係呈一共平 面，且一絕緣層形成於支撐塊與第一基底之間，以隔離 支撐塊與第一基底，並且上述接合墊會橫跨於此絕緣層 ® 上。因此，形成於支撐塊側面上的導線層並不會影響感 光元件。此外，由於，支撐塊係設置於接合墊上（T接觸 的位置），因此，可增加導線層與接合墊間的結構強度（或 T接觸的結構強度），進而增強影像感測元件封裝體的整 體結構強度。 第12圖顯示根據本發明一實施例之製作影像感測元 件封裝體的流程圖。如第12圖所示，首先，提供一晶圓， 其包含具有多個感光元件區的一第一基底，且多個接合 ® 墊形成於此第一基底上，如步驟S5。接著，將此第一基 底接合至一第二基底，如步驟S10。之後，薄化上述第一 基底，如步驟S15。待薄化後，形成一圖案開口於上述第 一基底之中，以從第一基底隔離出一支撐塊，並暴露部 分接合墊，如步驟S20。接著，依序形成彩色濾光片及微 透鏡於上述第一基底的背面上，如步驟S25。之後，設置 一上封裝層於第一基底的上方，且形成一凹口於第二基 底之中，以分離第二基底，如步驟S30及S35。然後，設 9002-A33417TWF/X07-056/yungchieh 18 200950046 Λ -- 置一下封裝層於上述第二基底的背面上，如步驟S35所 示。 在完成上述步驟，進行一刻痕步驟，形成一通道凹 口，以暴露上封裝層的表面，如步驟‘ S45。之後，形成一 導線層於上述下封裝層的背面上，且沿著上述通道凹 口，延伸至上述支撐塊與接合墊的侧面，並電性連接接 合墊，如步驟S50。接著，設置一導電凸塊於下封裝層的 背面上，且電性連接上述導線層，如步驟S55。然後，進 © 行一切割步驟，如步驟S60，以完成影像感測元件封裝體 的製作。 由於，上述圖案開口可同時達到暴露接合墊，用以 提供檢測感光元件，以及隔離形成感光元件區域之第一 基底的目的，因此，可縮短及簡化製作流程。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍内，當可作此許之更動與潤飾，因此本發明 ® 之保護範圍當視後附之申請專利範圍所界定為準。 9002-A33417TWF/X07-056/yungchieh 19 200950046 【圖式簡單說明】 弟1圖顯示一m l. 圖； 〇之影像感測元件封裝體的剖面 件封=發明實施例之製作影像感測元 封裝本發㈣施例之製作影像感測元件And the first substrate 1〇1 in the non-photosensitive element (4) 8. Yes;: 疋 '上34® Case D 114 can be any shape design, as long as the bonding pad can be exposed at the same time, and the component area can be isolated. Therefore, the top 5 of the opening and the 4th figure The illustrations are not intended to limit the invention. Fig. 5 is a cross-sectional view showing the image sensing element package as shown in Fig. 4 taken along the line j-A. As shown in Figure 5, form a pattern opening! μ is in the first substrate 100 to expose a portion of the bonding pad 104. Further, the first substrate 1 〇〇 and the first substrate ι 〇 are separated from each other by the above-described pattern opening D 114. Since the pattern opening Π4 can simultaneously expose the bonding pad 104 and the isolation photosensitive element region 1〇6, it is not necessary to perform additional isolation or to form a step for detecting the opening. As shown in Fig. 6, a color filter 116 is formed on the back surface of the first substrate 100 and corresponds to the photosensitive member 102. Next, a microlens (miCr〇-lens) 118 is disposed on the color filter 116 described above. In one embodiment, the microlens 118 may preferably be a phenolic resin, a melamine resin, an epoxy or other suitable material. As shown in Fig. 7, an upper packaging layer 12 or a covering plate is provided on the back surface of the first substrate 100, 9002-A33417TWF/X07-056/yungchieh 12 200950046. In one embodiment, first, the upper encapsulation layer 120 is provided, and then a spacer 122 is formed on the encapsulation layer 120. Thereafter, a bonding layer 124 is formed on the spacer layer 122, and the upper encapsulation layer 120 is bonded to the first substrate 100 to cover the back surface of the first substrate 100. The upper encapsulation layer 120 may be, for example, glass, quartz, opal, plastic or any other transparent substrate that allows light to enter and exit. It is worth mentioning that a filter and/or an anti-reflective layer may be selectively formed on the upper encapsulation layer. The spacer layer 122 may be an epoxy, a solder mask or other suitable insulating material, such as a cerium oxide layer of an inorganic material, a cerium nitride layer, a cerium oxynitride layer, a metal oxide or Combination, or polyiside resin (polyiniide; PI), butylcyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons ), accrylates, etc., and the spacer layer 122 may be by a coating method such as spin coating, spray coating or curtain coating, or Other suitable deposition methods, such as liquid phase deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (low pressure chemical vapor deposition) Deposition; LPCVD), plasma enhanced chemical vapor deposition (PECVD), rapid thermal chemical vapor deposition (rapid 9002-A33) 417TWF/X07-056/yungchieh 13 200950046: thermal-CVD; RTCVD) or atmospheric pressure chemical vapor deposition (APCVD) is formed to isolate environmental pollution or prevent moisture intrusion. The above bonding layer 124 may be a polymer film or one or more adhesives, such as an epoxidized resin or a polyurenthane, and is used to bond the upper encapsulation layer 120 and the spacer layer 至2 to the first Substrate 100. In addition, it is worth noting that although the color filter 116, the bonding layer 124 or the spacer layer 122 may not be filled in the pattern opening 114, the first substrate 100 is isolated from the first substrate 100. An insulator of a substrate 101. As shown in Fig. 8, after the above steps are completed, a notch is formed at a position along a predetermined scribe line between the respective photosensitive element regions (or die regions) by a lithography/etching process. A notch 126 is formed in the second substrate 112 to separate the second substrate 112, and a plurality of carrier plates corresponding to the photosensitive element regions are formed. Then, an insulating layer 128 is formed to cover the side surface of the second substrate 112 and the back surface thereof, and a lower packaging layer 130 is disposed on the back surface of the second substrate 112 to cover The second substrate 112 and the insulating layer 128. In an embodiment, the insulating layer 128 may be an epoxy resin, a solder resist layer or other suitable insulating material, such as an oxidized stone layer of an inorganic material, a tantalum nitride layer, a hafnium oxynitride layer, a metal oxide or The combination thereof is a polyimine resin, an organic high-molecular material, a benzocyclobutene, a parylene, a naphthalene polymer, a fluorocarbon, an acrylate, or the like, and the spacer layer 122 may be coated. For example, spin coating, spray coating or curtain coating 9002-A334] 7TWF/X07-056/yungchieh 14 200950046 - cloth, or other suitable deposition methods, such as liquid deposition, physical vapor deposition, chemical vapor deposition, Low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition, or atmospheric pressure chemical vapor deposition is formed to isolate the second substrate 112 from the subsequently formed wire layer. The lower encapsulation layer 130 can be used to carry the first substrate 100 and the second substrate 112, and the lower encapsulation layer 130 can be a substrate with high thermal conductivity, such as a stone substrate or a metal substrate, but is not limited thereto. © As shown in Fig. 9, after the lower encapsulation layer 130 is provided, an insulating layer 132 is selectively formed on the lower encapsulation layer 130. Thereafter, a scoring step is performed to form a channel notch 134 and a supporting brick 101a. In one embodiment, the scoring step is performed along the predetermined scribe line location by, for example, notching equipment to form the channel recess 134 and expose the surface of the upper package layer 120. Since there is an isolated first substrate 101 at the position of the dicing street (as shown in Fig. 8), when the scoring step is performed, the first base substrate 101 is cut so that part of the first substrate 101 is The first substrate 101, which is the remaining portion, is removed, that is, the above-described support block 101a. It is worth noting that since there is a first substrate 101 in the cutting walkway, the structural strength of the package can be increased when the scoring step is performed, thereby avoiding damage caused by the scoring step, such as cracking of the component. In addition, the material of the support block 10a is not limited to 矽, and the material thereof may be similar to that of the first substrate 100. As shown in FIG. 10, a conductive trace (conductive trace 9002-A3 3417TWF/X07-056/yungchieh 15 200950046 -layer) 136 is formed on the back surface of the lower package layer 130, and the mouth is concave. The port 134 extends to the side of the joint 104 and the support block i〇la to electrically connect the bond pads 104. In one embodiment, by way of, for example, electroplating or sputtering, compliant, for example, copper, aluminum, silver (silver; Ag), nickel (nickel) or The conductive material layer of the human body is on the lower encapsulation layer 130' and the conductive material layer extends on the side of the lower encapsulation layer 130, the insulating layer 128, the bonding pad 1〇4, and the long-term memory block 1 〇1 a to the channel The bottom of the recess 134 is electrically connected to the receiver 104. Thereafter, the above-mentioned conductive material layer is patterned by, for example, photolithography/etching to form a wiring layer 136. It is worth mentioning that the step of patterning the conductive material layer can redistribute the position of the subsequently formed conductive bumps, for example, the conductive bumps can be extended from the peripheral region of the lower package layer to the back of the entire lower package layer. Therefore, the wire layer 136 can also be referred to as a redistdbuticm layer. In addition, in another embodiment, the wire layer 136 may be a doped polysilicon, a single crystal or a conductive glass layer, or annealed by titanium, molybdenum, chromium or titanium. A deposited layer of metallic material. Further, the above-mentioned branch block 101a is separated from the first substrate 100 by the pattern opening 114 filled with the insulating layer, and therefore, the wire layer 136 formed on the side of the support block 10a does not affect the photosensitive member. In Fig. 10, a protective layer 138, such as a solder mask, is applied over the wire layer 136 and formed - conductive bumps 9002-A33417TWF/X〇7-〇56/yungchieh 16 200950046 (conductive bump) 140 is on the lower encapsulation layer 13 and electrically connected to the wiring layer 136. In an embodiment, after the protective layer 138 is formed, the protective layer 138 is patterned to form an opening exposing a portion of the wire layer , 36, and then, by means of electricity money or screen printing, A solder is filled in the opening and a re-flow process is performed to form a conductive bump 140 such as a solder ball or a solder paste. After the above steps are completed, the upper encapsulation layer 120 is then separated along the predetermined dicing street by a dicing blade to cut out an image sensing element package 150 as shown in FIG. Figure 11 is a cross-sectional view showing an image sensing element package 150 in accordance with an embodiment of the present invention. In FIG. 11, a semiconductor wafer having a first substrate 1A, a support block 10a spaced apart from the first substrate 1 by a predetermined distance, and a bonding pad 104 having a surface. It spans over the first substrate 100 and the support block 10a. As shown in FIG. 11, the first substrate 100 has a first surface and an opposite second surface, and a photosensitive element 102 is formed on the first surface of the first substrate 100. The second substrate 112 is bonded to the first surface of the first substrate 100, and the upper and lower encapsulation layers 120 and 130 respectively cover the second surface of the first substrate 1 and the second substrate 112. Referring to FIG. 11 , a wire layer 136 is formed on the back surface of the lower package layer 130 and extends to the side of the bonding pad 104 and the support pad 101 a to electrically connect the bonding pad 104 and a conductive bump. The 140 is disposed on the back surface of the lower sealing layer 13 , and electrically connected to the wiring layer 136. In an embodiment, the second surface of the first substrate 100 may be 9002-A33417TWF/X07-056/yungchieh 17 200950046*' as a light receiving surface, and the first surface on which the photosensitive element 102 is formed may serve as a backlight surface. The external light can pass through the light receiving surface to the photosensitive element 102, so that the photosensitive element 102 can sense the light passing through the first substrate 100 and generate a signal, and then the signal can be transmitted through the bonding pad 104 and the wire layer 136. To the conductive bumps 140. It is noted that the support block is coplanar with the first substrate, and an insulating layer is formed between the support block and the first substrate to isolate the support block from the first substrate, and the bonding pad is spanned therethrough. On the insulation layer®. Therefore, the wiring layer formed on the side of the support block does not affect the photosensitive element. In addition, since the support block is disposed on the bonding pad (the position where the T contacts), the structural strength between the wire layer and the bonding pad (or the structural strength of the T contact) can be increased, thereby enhancing the overall image sensing device package. Structural strength. Figure 12 is a flow chart showing the fabrication of an image sensing element package in accordance with an embodiment of the present invention. As shown in Fig. 12, first, a wafer is provided which includes a first substrate having a plurality of photosensitive element regions, and a plurality of bonding pads are formed on the first substrate, as by step S5. Next, the first substrate is bonded to a second substrate as by step S10. Thereafter, the first substrate is thinned as by step S15. After being thinned, a pattern opening is formed in the first substrate to isolate a support block from the first substrate and expose a portion of the bonding pad, as by step S20. Next, color filters and microlenses are sequentially formed on the back surface of the first substrate, as by step S25. Thereafter, an upper encapsulation layer is disposed over the first substrate, and a recess is formed in the second substrate to separate the second substrate, as in steps S30 and S35. Then, set 9002-A33417TWF/X07-056/yungchieh 18 200950046 Λ -- Place the encapsulation layer on the back surface of the above second substrate as shown in step S35. Upon completion of the above steps, a scoring step is performed to form a channel recess to expose the surface of the upper encapsulation layer, as in step 'S45. Then, a wire layer is formed on the back surface of the lower package layer, and extends along the channel recess to the side of the support block and the bonding pad, and electrically connected to the bonding pad, as in step S50. Then, a conductive bump is disposed on the back surface of the lower package layer, and the above-mentioned wire layer is electrically connected, as in step S55. Then, a cutting step is performed, such as step S60, to complete the fabrication of the image sensing device package. Since the pattern opening can simultaneously reach the exposed bonding pad for providing the purpose of detecting the photosensitive element and isolating the first substrate forming the photosensitive element region, the manufacturing process can be shortened and simplified. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is to be understood that the present invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection of the invention is defined in the scope of the patent application. 9002-A33417TWF/X07-056/yungchieh 19 200950046 [Simple description of the drawing] Figure 1 shows a m l. Figure; Sectional image of the image sensing device package of the = = Image sensor package of the invention example (4) The production of image sensing components
【主要元件符號說明】 1〜影像感測元件封裝體 2〜基底； > 4〜感光元件； 6〜接合墊； 8〜蓋板； 9〜承載板； 10〜導電層； 12〜鲜球； 101〜隔離之第一基底； 1〇〇〜第一基底； 101a〜支撐塊； 102〜感光元件； 104〜接合塾； 106〜感光元件區； 108〜非感光元件區； 110〜保護層； 112〜第二基底； 114〜圖案開口； 114 a〜第一開口； 114b〜第二開口； 114c〜溝槽； Π6〜彩色濾光片； 118〜微透鏡； 120〜上封裝層； 122〜間隔層； 124〜接合層； 126~凹口； 128〜絕緣層； 9002-Α33417TWF/X07-056/yungchieh 20 200950046[Main component symbol description] 1 to image sensing device package 2 to substrate; > 4 to photosensitive member; 6 to bonding pad; 8 to cover; 9 to carrier plate; 10 to conductive layer; 12 to fresh ball; 101~isolated first substrate; 1〇〇~first substrate; 101a~support block; 102~photosensitive element; 104~joining 塾; 106~photosensitive element area; 108~non-sensitive element area; 110~protective layer; ~ second substrate; 114 ~ pattern opening; 114 a ~ first opening; 114b ~ second opening; 114c ~ groove; Π 6 ~ color filter; 118 ~ microlens; 120 ~ upper encapsulation layer; 122 ~ spacer layer ; 124~ bonding layer; 126~ notch; 128~insulation layer; 9002-Α33417TWF/X07-056/yungchieh 20 200950046
130〜下封裝層； 132〜絕緣層； 134〜通道凹口； 136〜導線層； 138〜保護層； 140〜導電凸塊； 150〜影像感測元件封裝體。 9002-A33417TWF/X07-056/yungchieh 21130~lower encapsulation layer; 132~insulation layer; 134~channel recess; 136~wire layer; 138~protective layer; 140~conductive bump; 150~ image sensing element package. 9002-A33417TWF/X07-056/yungchieh 21