TW201009369A - Test apparatus and semiconductor device - Google Patents

Abstract

A semiconductor device (DUT200) includes an interface circuit (202) connected to an ATE 100 through a test control bus BUS3 which differs from main buses BUS1 and BUS2, to receive control signal SCNT output from the ATE100, and to control the multiple BIST circuits BIST1-BIST5 based on the control signal SCNT. Further, the configuration of DUT200 allows the ATE100 to read out the test result SR assigned by the control signal SCNT via the test control bus BUS3. A BISI synchronous control unit 22 generates a first control signal for controlling individual BIST circuit of the multiple BIST circuits in the DUT200, and a second control signal for reading out the test result signal generated by the BIST circuit via an interface circuit in the semiconductor device, and to supply the first and second control signals to DUT200 via the test control bus BUS3.

Description

201009369 31916pif VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a testing technique for a semiconductor element. [Prior Art] In order to test a semiconductor element at low cost, a Built-In Self Test (BIST) circuit is utilized. If the BIST circuit is used, the device under test (hereinafter referred to as DUT (Device Under Test) can be used at a low speed even without using an expensive semiconductor automatic test device (hereinafter referred to as ate ❹ (aut〇mated testequipment)). ) Read and write, limited input and output signals to diagnose or determine the fault location. In particular, BIST has accumulated a lot of experience or research results on memory circuits or logic circuits, and has been practically used for mass production testing. In 1990, the so-called IEEE1149.1 specification was elaborated by the Joint Test Action Group (J〇int Test Acti〇n Group 'JTAG), which tested the boundary scan (b〇undary scan).

The way is consistent with the input and output signals required for the boundary scan test. JTAG specification (also referred to as JTAG) is input TDI (Test Data Input), test data output TD〇 (Test Data 〇utpm), test clock TCK (Test Clock), test mode selection TMS (Test_Mode)

Select), test the TRST (Test Rese〇) 5-bit input and output signal, and access it in the BIST circuit loaded into the DUT to perform the boundary scan test specification. For memory or logic Most BFD tests performed in the BIST of a circuit are as follows, that is, a flip-flop (flip f|〇P) or a latch connected to a certain boundary portion of the circuit is connected in series, shape 5 201009369 31916pif The daisy chain is used to read the 埠 料 埠 埠 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 port port port port port port port port port port port port port port dai In the case of only the data series, the resources of the period signal (Shishi), when the 'as a coffee model device or an electronic computer (45::= the side by side of the small rule, however, most of the bribes in order to ensure quality, not only must Performing the BIST test' and having to perform the DC coffee (10), (10) test or the input leakage test, it has not been able to achieve the test without using ATE at all. Therefore, several inputs and outputs of the ate for performing the Dc test, etc. Will be assigned to; DU T's; rTAG帛埠 (_ is the test access 埠 TAP), which can perform both BIST test and DC test in one ATE. In general, the more expensive the ATE can perform higher-speed signal input and output, the more expensive it is. The test cost increases. Therefore, when only the BIST and the specified DC test are performed, the minimum quality required is ensured, and when the component is shipped, an inexpensive ATE that can only generate a low-speed signal is used. In the current situation, the BIST is used most. BIST tester, etc. The effectiveness of BIST is well proven in logic or memory circuits. Therefore, try to extend BIST to analog circuits to implement digital analog-to-digital hybrid circuits (Large). Scale Integration, LSI) Synthetic BIST. A high-speed I/F circuit that has been used as one of the analog circuit blocks. There is a lot of research in the BIST method called loopback test. The mass production test has also been put into practical use. 'analog/digital (A/D) converter or digital/analog (D/A) converter, etc.

Ο 201009369 The BIST of the 31916pif digital block and the boundary part of the analog block, or the BIST of the wireless communication LSI, such as the end or the back end, will also be put into practical use. In view of this situation, in the near future, memory, logic, analog, A/D conversion, D/A conversion, high-speed I/F, etc. can be made into a single-chip system on a chip (SoC) or system level. In a System in a Package 'SiP, a single DUT may carry multiple BISTs. Due to the miniaturization of the semiconductor process, it is negligible to increase the circuit area (burden (.magnetic ead)) by setting the BBT circuit. The more test items that can be verified by BIST, the larger the bist circuit can be installed. . Further, as an advantage of BIST, it can be exemplified that the circuit state can be known from the outside: For the case of two 70 pieces that make a plurality of functions integrated, 5, & will be extremely effective for poor analysis or improvement of yield. In this case, the inventors studied the test of legs with multiple bist (4). We reach the problem of understanding town. Control command ======= = 2 source fee (four) complex 5 贞. This situation will lead to an increase in test time or measurement. 2. When the BIST circuits are linked to each other, m is also required to spread the bribe circuits, so that the materials section (> view access (TeSt 7 201009369 31916pif 3. In the future, It may be necessary to have multiple BISTs tested with the usual input rounds of the normal DUTs for access). ===Unexplained linkages between the bribes and the usual tests: [Invention] The present invention is in view of such circumstances. Developed, a way to control multiple BIST circuits in an integrated manner. A certain aspect of the invention is (4) a semiconductor device. As a semiconductor component of the device under test (DUT), the star energy region Block, multiple leg circuits, and interface circuits. Multiple functions are input and output of signals via the main bus (mam bus) = fixed dragon processing. Multiple BIST circuits are for the parent-work area of multiple functional blocks. The block device 'make the corresponding Wei block into a digital test result corresponding to the test result. The interface circuit is controlled by the main bus bar with different test control bus bars and the test device and the control signal outputted from the test device. .interface The circuit configuration, = control of a plurality of BIST circuits based on the control signal, and the test result signal specified by the = signal can be read by the test device via the test control bus. The test device is provided with a test unit and a control unit. The test order is performed by the main bus bar and the signal is received by the semiconductor component to enable at least one functional block to perform the specified money processing. The control unit ίίΪ 1 control signal and the second control key, and control the convergence via the test = The second control second control money is supplied to the semiconductor element, and the first (four) information system controls the semiconductor element_the plurality of 8 201009369 31916pit BIST circuits individually, and the second control signal is used for The test result signal generated by the BIST circuit is read out from the interface circuit in the semiconductor component. According to the aspect, the interfaces of the plurality of BIST circuits can be unified, and the BIST circuit disposed in the DUT can be controlled and obtained. The test result signal generated by each BIST circuit. The "test result signal" is both y and the quality of the function block to be inspected. The result may also be intermediate data obtained during the test. Moreover, the term “receiving and receiving” means at least one of transmission and reception. The first control signal generated by the control unit may include at least The BIST circuit of the BIST circuit is a selection signal for setting the active circuit. At least one of the plurality of BIST circuits is configured to be switchable into a plurality of modes. The selection signal may include mode data of the setting mode. A third control signal 'including a test pattern to be supplied to each BIST circuit' can be generated and supplied to the semiconductor element via the (4) trial control ship. At this time, the functional block can be supplied by the test farmer. The generated test pattern is set to obtain the result of processing the test pattern. The control unit may further generate a fourth control signal indicating the start and stop of the test of the BIST circuit, and supply the fourth control signal to the semiconductor element via the test control bus. The control unit 7L can generate an option (GptiGn) signal for inherent control of at least one of the plurality of BIST circuits. Test 201009369 Control bus, which can include other signal lines that are used to transmit option signals and are different from the first and second control signals. Because the option signal is set, the designer of the DUT 200 can assign an option signal to the BIST circuit that is required to transmit multiple bits. In a state in which the test unit and the semiconductor component perform signal transmission and reception, and at least one functional block performs predetermined signal processing, the control unit may make the BIST circuit corresponding to the at least one functional block into an active circuit, and at least one functional block. carry out testing. At this time, the internal self-test (BIST) can be performed using signals transmitted and received via the main bus. The test device may further comprise a synchronization control unit that receives the control signal generated by the control unit and outputs the control signal in synchronization with the test rate of the test unit. Perform an internal self test (BIST). The same is true in multiple BIST circuits. At this time, the test rate can be changed in real time because the control 彳§ is synchronously supplied to the DUT. The BIST circuit of the synchronous function can be calibrated. ) With the vine at this time,

The resulting correction signal is used to correct the sharing between the functional blocks. At least one BIST circuit, which outputs a test result signal generated by the result of input/generation of the correction signal, is generated to correct the BIST circuit 201009369 31916pif BIST circuit. Another aspect of the invention is a semiconductor component. The body has a function block, multiple BISTs, and a user circuit. Multiple

Signal input and output are performed by the flow line, and the processing is performed. A plurality of BIST circuits are configured for each of the plurality of functional blocks, and the corresponding Wei series is tested to generate a digital test result signal corresponding to: ★, the result. The interface circuit receives the control i» number output from the test device via the main control bus and the main control bus. The interface circuit is configured to (1) control a plurality of BIST circuits based on the control signal, and (2) the test result signal specified by the control signal can be read by the test device via the test control bus. According to this aspect, the interfaces of the plurality of BIST circuits can be unified, and the plurality of BIS T circuits disposed in the DUT can be integrated and controlled by the testing device, and the test result signals generated by the BIST circuits can be self-tested. Read out in the device. The control signal may include at least: a selection signal for setting whether any BIST circuit of the plurality of B js τ circuits is an active circuit; and a test data input # number, including a test to be supplied to the BIST circuit set as the active circuit pattern. The BIST circuit set to the active circuit by selecting the signal can receive the test data input signal to test the corresponding functional block. At least one of the plurality of BIST circuits may be configured to be switchable in a plurality of modes. The interface circuit can set the mode of the BIST circuit based on the mode data contained in the selection signal. The BIST circuit set as the active circuit by selecting the signal can be used to start or stop the test according to the start-stop signal included in the control signal.

The BIST circuit corresponding to the at least one functional block may test at least two functional blocks in a state where the at least one work flb block performs the prescribed signal processing. V The msT circuit with the same function in multiple BIST circuits can be shared among functional blocks. At least one BIST circuit can be input and corrected by the calibration ❿ L. The BIST circuit can output the result of processing the correction signal as the test result k number. =, any combination of the above constituent elements or the effective form of the invention of the method, device, etc. &β丌 is the [effect of the invention] According to the present invention, a technique for integrated control of a plurality of msTs is provided. The above features and advantages of the present invention can be more clearly understood. (IV) Understand the following specific examples, and the following description will be described in detail with reference to the accompanying drawings. [Embodiment] The cut-and-face is based on a preferred embodiment and refers to the drawings, the surface-mounted elements, the structure #2_, or the equivalent composition. And a, the same reference numerals are given to the same symbols, and the description is omitted as appropriate. The features, or combinations thereof, are not necessarily the essence of the invention. 12 201009369 31916pit Sexual content. In the figure, each element disclosed as a functional block for performing various processes can be represented by a central processing unit (CPU), a memory, or other large scale integration. In the case of 'LSI,' software can be realized by a program downloaded in a memory or the like. Thus, those skilled in the art can understand that the functional blocks can be implemented in various forms only by hardware or only by software ' or a combination of the same, and are not necessarily limited to any of them. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a test system 3A including a semiconductor automatic test apparatus (hereinafter referred to as ATE) 100 and a DUT 200 according to an embodiment. Fig. 1 shows only the components associated with the present invention, thereby omitting signal lines or blocks which are not related to the essence of the invention, such as power supply. The ATE 100 of the present embodiment is constructed on the premise of the DUT 200 having an embodiment having no prior characteristics, and similarly, the DUT 200 of the embodiment is constructed on the premise that the ATE is not previously characterized. That is, the present invention installs a novel architecture different from the previous one in both ATE1〇〇 and DUT2〇〇, and performs simple control on multiple BIST circuits, and the present invention aims to implement the previous JTAG. Various test methods that have not been implemented. First, the configuration of the DUT 200 will be described. Next, the configuration of the ATE1〇〇 will be described. The DUT 200 includes a plurality of functional blocks FB1 to FB5, a plurality of BIST circuits BIST1 to BIST5, a BISI control circuit 202, an input/output buffer 204, and an input/output buffer 208. 13 201009369 31916pif Multiple function blocks FBI~; FB5 and input/output buffers 2〇8, f are normally operated (ie, installed in the component), via digital main bus BUS1, analog main bus BUS2, and The signal is transmitted and received with the external circuit, and the predetermined signal processing is performed while synchronizing and coordinating. The content of the signal processing is not particularly limited, and any LSI is assumed to be the DUT 200. Hereinafter, in order to facilitate understanding, a case where the DUT 200 is an integrated circuit in which analog digital mixing is performed will be described. The DUT 200 transmits and receives digital signals via a digital main bus BUS1 connected to a digital input/output (Input/Outpm, I/O) 埠 P4, and is connected via an analog main bus BUS2 ' connected to the analog I/O 埠 P5. And the analog signal is sent and received. The digital signals transmitted via the digital main bus BUS1 are Transistor Transfer Logic (TTL), Diode-Transistor Logic (DTL), and Emitter Coupled (Emitter Coupled). Logic, ECL), cuiTent Mode Logic (CML) Complementary Metal Oxide Semiconductor (CMOS), Stub Series Terminated Logic (SSTL), > (Low Voltage Differential Signaling 'LVDS), etc. The binary signal of the previous standard logic I/O. The digital signal via the digital main bus BUS1 can be transmitted by the input/output 现有 (digit 1/〇埠P1) of the existing ATE100. In contrast, the analog signals transmitted via the analog main bus BUS2 are high-speed I/F input/output signals, optical signals, multi-value modulated signals (ASK, 201009369 31916ρΐί FSK, PSK), radio frequency (RF). Analog signal (amplitude modulation, frequency modulation, phase modulation), wireless signal, not a simple binary digital signal. When analog signal In the case of an optical signal, the analog main bus BUS2 is an optical fiber. When the analog signal is an RF analog signal, the analog main bus BUS2 is a cable or a transmission line having a specified characteristic impedance (50 Ω or 75 Ω), when the analog signal For the wireless signal, the analog main bus BUS2 is air. Therefore, the analog bus BUS2 ' in this specification should be based on the general concept of wired and wireless to grasp the analog signal for the transceiver. ATE100 has the digit 1/〇.埠pi different analog I/O埠P2. The digital bus BUS is analogous to the bus bar width (number of bits) of the main bus BUS2. The ordinary analog digital mixing circuit is roughly divided into digital blocks 214, analogy Block 216. In order to facilitate understanding, the function block FBI is set as the memory circuit, FB2 is set as the logic circuit, FBL3 is set as the D/AA/D conversion circuit, FB4. It is set as the analog circuit, and fB5 is set to analogy 1/ The input/output buffer 208 is used for buffering the input and output of data between the external circuit connected to the digital main bus BUS1. The logic circuit FB2 is buffered via the output = output 208 received from the externally input digital signal, performs predetermined signal processing by the memory circuit FBI can access the logic circuit FB2, and retain various data. That is, the input/output buffer 208, the memory circuit FB1, the logic 'path FB2, and a part of the d/aa/d converter FB3 belong to the digital block 15 201009369 31916pif analog I/O circuit FB5 via the analog main bus BUS2 Input and output of data between connected external circuits. It is conceivable that the analog I/O circuit FB5 is a low-definition multimedia interface (j^gh Definition).

A high-speed I/F circuit for signals of the Multimedia Interface' HDMI), an optical I/O circuit for receiving a light-emitting signal, and a 1/() circuit for transmitting and receiving a multi-value modulated signal. Alternatively, the analog I/O circuit FB5 may be an antenna or a wireless interface that receives a wireless signal. Analog circuit FB4 includes RF transceiver circuit, quadrature modulation and demodulation circuit, multi-value modulation and demodulation circuit, Fast Fourier transform (FFT) circuit, fast Fourier transform (IFFT) circuit, filtering A number of circuits corresponding to the functions of the DUT 200 in the oscillator, oscillator, equalizer, mixer, power supply circuit, bandgap regulator, and the like. The analog circuit FB4, the analog I/O circuit FB5, and a portion of the D/A.A/D converter FB3 belong to the analog block 216. The D/A converter of the D/A*A/D converter FB3 converts the digital signal generated on the side of the logic circuit FB2 into an analog signal and supplies it to the analog block ❹. Further, the A/D converter of the D/A.A/D converter FB3 converts the analog signal generated on the analog block side into a digital signal and supplies it to the digital block. That is, the D/A.A/D converter FB3 functions as an interface between the digital block 214 and the analog block 216. A plurality of BIST circuits BIST1 to BIST5 are provided for each of the functional blocks FB1 to FB5. Each BIST circuit tests the corresponding functional block. 'Generates the digital test result corresponding to the test result. 16 201009369 31916pif The signal SR ° "test result signal" can be the result of the determination of the quality of the function block FB to be inspected. It can be the intermediate data obtained during the test. The test items or contents of the BIST circuit are determined according to the signal processing contents of the function blocks FB1 to FB5. In other words, the designer of the DUT 200 designs each BIST circuit to ensure proper operation of the corresponding functional block or to find a faulty location. A portion of the BIST circuits BIST1, BIST2, and BIST3 称作 is referred to as a digital BIST group 210, and a portion of the BIST circuit BIST3 and BIST4, BIST5 are referred to as an analog BIST group 212. Specifically, since the BIST circuits BIST1 and BIST2 are circuits for testing the memory circuit FB and the logic circuit FB2, the previous boundary scan test circuit can be constructed. Moreover, the control of the BIST circuits BIST1, BIST2 can be designed according to the JTAG specification. On the other hand, the test object D/A of the BIST circuit BIST3 to BIST5, the A/D converter FB3, the analog circuit FB4, and the analog I/O circuit FB5 cannot apply the boundary scan test. That is, it is not possible to perform charge control based on the JTAG specification, and it is necessary to perform a higher degree of control than the boundary scan test. The details will be described later, but the BIST circuit corresponding to the analog circuit can be regarded as a circuit that integrates a so-called measuring device such as a mixer circuit, an arbitrary waveform generator, or a digitizer. Thus, from this point of view, a BIST circuit (also referred to as an analog BIST circuit) corresponding to an analog circuit can utilize an assembly analyzer (Built-in Instruments, built-in instrument). Furthermore, the round-in output buffer 208 is a simple buffer, especially since it does not require a BIST test and is not provided in an individual BIST circuit. 17 201009369 31916pif DUT2〇〇 has a different test control sink than the main bus BUS 1 and BUS2, and the test for BUS3 connection is 1/0槔P6. The input/output buffer 204 is provided for inputting a binary digital signal input via the test I/O 埠 P6. The interface circuit 202 receives the first control signal SCNT1 and the second control signal SCNT2 outputted from the ATE1〇() via the test control bus BUS3. The interface circuit 202 controls the plurality of BIST circuits BIST1 to BIST5 based on the first control signal SCNT1. Further, the interface circuit 202 is configured to output the test result signal SR delimited by the second control SCNT2 in the test result signal SR generated by the bbt circuit to the sleek side via the test control bus line Bus3. ^ Interface circuit 202 not only performs control on the previous memory BIST, logical bist, and analog BIST. By means of the interface circuit 2〇2, the input number or the control command* is the same as the multiple circuits' to provide the assembly between the thin 100 and the dut2〇〇: 疋^ >ib © ( Built-in Instruments Standard =re's built-in instrument standard interface, hereinafter referred to as bisi). From this point of view, the interface circuit 202 is also referred to as a BISI control circuit. By providing the brain control circuit 2G2, 岐(10) = 〇 linkage operation and synchronization operation, it is possible to provide a plurality of job environments that can be simultaneously executed. The operation of the _BISI control circuit (10) will be described later. The ATP time t is a configuration of DU1·. Next, the configuration of the ATE 100 of the test DUT 200 will be described. 18 201009369 31916pif ATElOO is provided with a test program 1, a BISI command control unit 12, a function cell 14, an RF test unit 16, an optical I/O test unit 18, a DC test early = 20, and a BISI synchronization control unit 22. The test program 1 is the sequence of the test process that is pre-programmed by the user. Interest • Test the DUT200 according to the sequence of the oil city 10. The digit 1/0埠P1 of the ATE100 is connected via the digital main bus BUS1 and the digital I/O埠P4 of the DUT200. ATE100's analog I/O埠P2 is analogous to the main bus BUS2 and dut2〇〇 analogy ι/〇埠p5, and then 'ATE100's test with 1/〇埠p3 via test control bus BUS3 and DUT200 The test is connected with 1/〇埠p6. The ATE100 and the DUT 200 perform digital transmission and reception via the digital main bus BUS1. That is, the ATE 100 can output (write) data to the DUT 200 or read data from the DUT 200. Moreover, the ATE100 and the DUT 200 perform analog signal transmission and reception via the analog main bus BUS2. That is, ATE1〇〇 provides a ❹ analog signal to DUT2〇〇 or an analog signal received from DUT200. The function test unit 14 performs functional testing of the DUT 200 via at least one of the digital main bus BUS1 and the analog main bus BUS2. The following form is exemplified as a functional test. Functional Test 1. The function test unit 14 outputs a predetermined pattern data via the digital main bus BUS1 and writes it into the memory circuit FBI of the DUT 2 . Then, the written data is read from the memory circuit FBI via the digital main bus BUS1, and it is determined whether the expected value is a 19 201009369 31916pif. The result 'determines whether the data access function of the memory circuit FBI is normal. Lunar Test 2. The power monthly test unit 14 rotates the data based on the digital main bus BU S1 and processes the signal. The X ^ (4) of the signal processing result is obtained by the « ^ . sink > claw row BUS1 which is made by the digital master 11, and the determination and the expected value are determined. As a result, it is determined whether or not the logic circuit FB2 functions normally. Fruit ~ Logic ❿ 仓 · t · Test 3. Functional test list & 14 via the analog main bus 脱 ΓΓ ΓΓ ΓΓ 规定 规定 规定 规定 规定 规定 规定 规定 规定 规定 规定 规定 规定 规定 规定 规定 赖 赖 赖 赖 赖 赖 赖 赖 赖By the memory circuit FB1 ~ analog I / O Lei Zheng π 妹 虑 搜 从 从 从 从 从 从 从 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 从 执行 执行 执行 执行 执行 执行 执行 执行 执行 从 从 从Existence = Flow Row BUS2 and Output of Analog Signal to ΑΤΕ1(8) = The unit η compares the result of the signal processing of mrnoo with the expectation that the DUT 200 as a whole functions normally. At this time, it can also be controlled by the signal line of the digital bus BUS1 (four) logic circuit. The heartbeat set DC test list S 20 is DC required m. The % test passes the coordinated action of the test unit 20 and the functional test unit η to perform. The function test unit 14 generates a predetermined pattern data or command and supplies it to the logic circuit fb2 via the bit main bus BUS1. The seven waters take the analog test unit 14 to generate a modulated analog data of the specified pattern data. Provided to the analog circuit FB4 via the analog main bus BUS2, the logic circuit FB2 is set to a predetermined state, and the digits 1/〇埠''I 20 201009369 31916pif generate a fixed signal level (high level or low 20 In this state, the cover is generated at the digital I/〇3 (10) level or current level) = the measured potential is lower than the specified threshold ('Although the position I/O埠P4 should be low level' It is bad if the potential measured by the Dc test element 20 is higher than the threshold level VL.

Or, the result of providing a prescribed pattern to mmoo is such that the analogy ι/〇 circuit FB5 is set to a prescribed state, and a fixed signal level is generated in the _1/〇 bee p5. 1C test unit 2 〇 状态 〇 The DC signal level is measured and judged whether it is good or not. 'And' the DC test unit 2 提供 provides a predetermined voltage for the digit 1/0埠P4 or the analog 1/〇埠 P5, and measures the Dc leakage current flowing to the side of the DUT2 to determine whether the DUT 200 is good or not. Furthermore, in FIG. 1, the digital main bus BUS1 or the analog main bus BUS2 only indicates one, but when a plurality of signal lines are provided, all the signal lines, that is, a plurality of digits 1/〇埠DC test with P4 or analog 1/〇埠p5. The RF test unit 16 is attacked when the DUT 200 processes the RF signal. The RF test unit 16 has a function of generating an RF signal that should be supplied to the DUT2. Moreover, the RF test unit 16 has a function of receiving an rf signal (analog signal) output from the DUT 200, demodulating the RF signal, extracting a symbol, or measuring an eye pattem and The aperture ratio is measured to determine the spectrum, 21 201009369 31916pif or to consconiiati〇n mapping. Further, the 'RF test unit 16 is also used in the above-described functional test to convert the predetermined pattern data generated by the function test unit 14 into an RF signal' to be outputted to the dUT2 via the analog main bus BUS2. The optical I/O test unit 18 is set when the DUT 200 processes the optical signal. The optical I/O test unit 18 has a function of receiving an optical signal (analog signal) output from the DUT 200, demodulating and extracting symbols, or performing various tests. Moreover, the optical I/O test unit 18 is also used in the above-mentioned functional test, using the prescribed pattern data generated by the functional test unit 14 for optical modulation, and via the analog main bus (fiber cable) BUS2. Output to the DUT200. The BISI command control unit 生成2 generates the first control signal SCNT1 to the fourth control signal SCNT4 in response to the command ' in the test program 使用者 of the user. The first control signal SCNT1 is a signal for controlling a plurality of BIST circuits BIST1 to BIST5 in the DUT 200. The second control signal; § (: \112 is a signal for obtaining the test result signal SR. The third control signal 8〇13 13 ❿ 疋 contains signals to be supplied to the test pattern in each BIST circuit. The fourth control signal SCNT4 It is a start/stop signal START/STOP indicating that the BIST circuit starts and stops the test. The control signals SCNT1 to SCNT4 (hereinafter, also simply referred to as control signals SCNT) are retimated by the BISI synchronization control unit 22 described below. And output to the BISI control circuit 202 via the test control bus BUS3. 22 201009369 31916pif The following describes the relationship between the format of the control signal SCNT and the test control bus BUS3. FIG. 2 shows the control via the test. A diagram of the format of the control signal SCNT transmitted by the bus. The test control bus BUS3 includes the test data input line DATA-IN, the test data output line DATA-OUT, the clock line CLOCK, the BIST selection line BIST-SEL, and the start stop. Line START/STOP, and option extension line Option-Ι~Option_N. Control signals SCNT1~SCNT4 are transmitted via these signal lines. The BIST circuit that performs the test operation in BIST1 to BIST5 performs the specified bist selection signal BIST-SEL, and is transmitted via the BIST selection line BIST-SEL. The BIST selection signal BIST-SEL is a part of the above-described first control signal SCNT1. The selection signal BIST-SEL includes the BIST address ADRS_B and the mode data MD. The BIST address ADRS-B is allocated in each BIST circuit. When each BIST circuit can only switch the presence or absence of the action, the mode data MD becomes the instruction action. (determination) or 〇❹ (negative) 2-bit 1-bit data indicating the stop operation. The BISI command control unit 12' writes the pattern data MD to the BIST addresses ADRS_B of the plurality of BIST circuits BIST1 to BIST5. For example, when the first and second BIST circuits BIST and BIST2 are active circuits, and the BIST circuits BIST3 to BIST5 are inactive, the BIST address of the first BIST circuit BIST1 and the BIST address of the second BIST circuit BIST2 are used. In the BIST address of the other bist circuits BIST3 to BIST5, the mode value is written in the BIST address of the other bist circuits BIST3 to BIST5, and the mode is 23, 201009369 31916pif.招·^ Each BIST f way can execute multiple test items; when the mode is used, the mode data can also be used as the ^ switch mode handle, analogous to BIST Thunder inch 97 width. For example, ' 楛 分别 可以 第 第 第 第 = = = 分别 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The number of any of the values in 11) can also be different in each BIST circuit. Mode = as 'When the address of the first side τ circuit Cong 3 is written to the module (1 〇) 'Write the mode data to the BIST address of the 4th BIST circuit BIST4 (〇1), and for other muscle T circuits When the BIST address is written to the mode data (〇〇), the 3rd BIST circuit BIST3 is set to the second mode, the 4th BIST circuit BIST4 is set to the first mode, and the other BIST circuits are the inactive circuits. The test data output line DATA-OUT is used to transfer the data of the BIST result from the DUT 200 to the ATE 100. The second control signal SCNT2 for obtaining the test result signal SR is sent from the ATE 100 to the DUT 200 via the test data output line DATA-OUT. In this manner, the test result signal SR will be transmitted from the DUT 200 to the ATE 100 via the test data output line DATA-OUT, and the second control signal SCNT2 will be represented as the address data ADRS_R. ATE100 uses the address data ADRS_R to specify the address of the memory or scratchpad set on the DUT200 side of the DUT200. The test result signal SR stored in the designated address is transmitted to the ATE 100 as the read data RD. The third control signal SCNT3' including the test pattern to be supplied to each BIST circuit is supplied from the ATEn to the DUT 200 via the test data input line DATA-IN. The third control signal SCNT3 includes the address data ADRS_W of the BIST circuit indicating the transmission destination of the test pattern, and the test data supplied to the BIST circuit, that is, the write data %^^" 经由 via the s data input line The data transmission of DATA-IN and test data output line DATA-OUT can be installed as a single line of bidirectional transmission as I2C bus, or can be installed by two separate lines. The clock of the data transmission of the purchase data, the test data output line DATA-OUT, and the BIST selection line BIST_SEL is transmitted via the clock line CL〇CK. The start time 'the fourth control signal stop signal of the stop time' is stopped by the start. The signal line ^TART/STOP is simplified. If the start stop recording STart/st setting' is set to the BIST circuit of the active circuit, the BIST start stop signal START/STOP is negative, then the BIST stop/option extension line 〇pti〇ni ~0pti〇n_N, used for the inherent control of each b ίτΪτ. The option extension line can be used as a wheel 珲 for the height and complexity of the analog circuit required as = for self-like to become available every Clock ( The test rate) is the operating frequency of 25 201009369 31916pif. For example, the _ 〇 - period is operated at a rate, and the certain period is operated at the normal = action clock (half rate). On Tuesday, the data sent and received between jobs is also freely changed by the test program 10. In this case, the BISI synchronization control unit 22 synchronizes the data transmitted via the test control bus BUS3 with the test cycle. The DATA-IN is the data generated by the BISI command control unit 12, and is synchronized with the predetermined clock signal CLOCK. The BISI synchronization control unit 22 receives/receives the test data input signal DATA_IN synchronized with the clock CLOCK and causes it to Synchronized with the test cycle CYC_TEST. The synchronized test data input signal DATA-IN_SYNC is supplied to the DUT 200 via the test control bus BUS3. The above is the overall configuration of the ATE 100. Figure 4 shows the inclusion of multiple functional blocks FB and A block diagram of a specific configuration example of the DUT 200 of a plurality of BIST circuits. The DUT 200 of FIG. 4 is a superheterodyne type receiving circuit. The DUT 200 includes a memory circuit 30. Baseband circuit 32, A/D converter 34, Low-Pass Filter (LPF) 36, mixer 38, local oscillator 40, image removal filter, waver 42, low A Noise Amplifier (LNA) 44, a Band-Pass Filter (BPF) 46, a memory BIST circuit 50 for testing the same, a logic BIST circuit 52, and an analog BIST circuit 26 201009369 31916pif 54, 56, 58, 60, 62, 64. The input I/O埠P5 has an input RF signal input. The BPF 46 filters the RF signal (RFin) around the carrier frequency. The LNA 44 amplifies the filtered 'wave' RF signal rf 1 to generate a signal 2 at the signal. The image removing filter 42' generates the RF signal RF3 by causing the image frequency to be reduced without causing image crosstalk due to the subsequent downconversion. The local oscillator 4 oscillates at the same local frequency as the rf frequency (carrier frequency). The mixer 38 mixes the output RF3 of the image removing filter 42 with the local signal LO and performs down-conversion. When the input RF signal RFin is quadrature modulated, the orthogonal component BB-Q of the in-phase component BB_I of the analog fundamental signal is output from the mixer. The analog baseband signal BB is filtered by the LPF 36 and converted to a digital value by the A/D converter 34. The output of the A/D converter 34 is input to the baseband circuit 32 for demodulation processing. The memory circuit 3〇 and the base frequency circuit of FIG. 4 correspond to the memory circuit FBI and the logic circuit FB2 of FIG. Further, the ® A/D converter 34 of Fig. 4 corresponds to the D/A.A/D converter FB3 of Fig. 1 . The LPF 36, the mixer 38, the local oscillator 40, the image removing filter 42, the LNA 44, and the BPF 46 of Fig. 4 are respectively shown in the figure! The analog circuit FB4 corresponds to. The memory BIST circuit 5 is a BIST circuit for testing the memory circuit 30, and the logic BIST circuit 52 is a BIST circuit for testing the base frequency circuit 32. The memory BIST circuit 5 〇 and the logic BIST circuit 52 perform, for example, a boundary scan test. The analog BIST circuits 54, 56, 58, 60, 62, 64 and the class 27 201009369 31916pif of FIG. 1 correspond to the BIST group 212. The analogy bribe circuit 54 is an arbitrary waveform generator that supplies an analog waveform to the input terminal of a 34. When the analog msT circuit μ == change ^ converts the analog waveform to whether the digital device 34 is operating normally. Alternatively, the baseband circuit 32 does not "=", and the digital value is output from the digital I/O 崞Ρ 4 to the ατ ει not), and the 良100 determines whether the quality is good or not. Φ The bist by the analog BIST circuits 56, 58, 6, 、, 62, 64 is executed in a state where the RP signal is supplied to the analog I/O 埠 P5. The analog BIST circuit 64 is provided for testing the BPF 46. The analog BIST circuit 64 includes, for example, a spectrum analyzer ((10) analyzer) and an A/D converter. When tested by analog BIST circuit 64, ATE 100 (not shown) provides a defined RF signal for analog 1/cause. The spectrum analyzer of the analog BIST circuit 64 converts the intensity in the per-band of the RF signal RF1 pulsed by the BPF 46 into a digital value. After comparing the spectral data thus obtained with the expected value, the analog BIST circuit 64 determines the BpF46. Good or not. Alternatively, the spectral data is output as a test data output signal DATA-OUT by the interface circuit 202. The analog BIST circuit 62 is provided for testing the LNA 44, which is, for example, a digitizer. The analog BIST circuit 62 digitizes the signal output from the LNA 44 in a state where the Rp signal is supplied to the analog 1/〇埠 P5 to determine the amplitude level of the RF signal RF2. The amplitude level is output as a test data output signal DATA-OUT to ATE100 28 201009369 31916pif ' ATE100 is based on the waveform level to determine whether the LNA 44 operates in accordance with f. Further, the analog BIST circuit 60 and the analog BIST circuit 58 are provided for testing the image removing filter 42 and the local oscillator 40, respectively, and the configuration and operation thereof are the same as those of the analog BIST circuit 64. Therefore, the circuits of the analog BIST circuits 6G, 58, and 64 can be connected, and the analog circuit of the measurement target can be switched in accordance with the above mode. The analog BIST circuit 56 is provided for testing the LPF 36, and its construction and operation are the same as those of the analog BIST circuit 62. The analog BIST circuits %, 62 can also be constructed as a single circuit. The analog BIST circuit is essentially 骇n ’, but it can be easily configured as long as it can test the corresponding functional block. For example, in the case of a spectrum analyzer, in a general-purpose spectrum analyzer, a high-frequency resolution user is required to be used in a wide frequency band (from DC to several GHz), but an analog ΒΙ & circuit can only be input to the DUT 200. It is only necessary to measure the predetermined range in the center band, and it is therefore possible to confirm the normal operation of the corresponding analog circuit, and the resolution may be low. For example, when the bandwidth of the RF signal is expressed as a time, the frequency resolution can be Af/n (η is 1 〇 or a real number of 1 〇 or less). Moreover, the digitizer or A/D converter and D/A converter can also be designed with sufficient precision required to verify the corresponding functional blocks. The BIST circuit is a circuit that is not required when the DUT 200 actually operates. Therefore, the circuit should be greatly shrinkled. However, in order to accurately test the various types of specific circuit blocks of the DUT2, it is sometimes necessary to perform calibration (calibrati). 29 201009369 31916pif In particular, when the measurement circuit realized by the miniaturization process requires high accuracy and high precision, the correction function is required to compensate for errors in process variation or temperature fluctuation. Hereinafter, the correction mechanism of the analog BIST circuit of the DUT 200 will be described. FIG. 5 is a block diagram showing a configuration of a DUT 200 having an analog BIST circuit correction function. As described above, in the DUT 200 of Fig. 5, a single analog BIST circuit 58 is shared by a plurality of analog circuits 40, 42, 46. Correction is set in the DUT200! >7, and the correction signal CAL of the test unit (RF test unit 16 in Fig. 5) from ATE1〇〇 is input via the correction bus BUS4. Furthermore, the correction bus BUS4 and the analog main bus BUS2 can be shared. A switch matrix 70 is provided between the plurality of analog circuits 40, 42, 46 and the analog BIST circuit 58. A plurality of input terminals of the switch matrix 7A are connected to output terminals of the various types of ratio circuits 4, 42, 46 and a correction block P7. The output terminal of the switch matrix 7A is connected to the analog BIST circuit 58. The state of the switch matrix 70 is controlled based on the mode data MD, ❿ of the BIST selection signal BIST-SEL. ▲ η According to the above configuration, the known correction code CAL can be input to the analog bist circuit 58 via the switch matrix 7A. The self-classing BIST circuit 58 rotates the measurement data D1 corresponding to the correction signal CAL. Measurement data = 10 is output to ATm〇〇 via BISI control circuit 2〇2*. ATE1〇〇 is based on the relationship between the correction signal CAL and the measurement data mG to correct the analog BIST path 58. The correction can be performed by the test program 1 30 30

The processor (CPU) of 201009369 31916pif is executed, and is also used to execute the test unit of the analog BIST circuit 58. As the test data input signal Da = corrected correction control signal D12, DUT200 towel. It is rotated from ATE100 to way 58 by correcting the control. The machine corrects the analogy with Dl2; for example, when the analog BIST t RF test unit 16 will have the function of the known j-spectrum analyzer, the positive signal CAL is supplied to the corrected 信号 signal as the calibration spectrum pure money CAL _ The control signal D12 of the circuit 58 corrects the analog circuit knife %. For the first time, the specific example of the right-hand job achieved by correcting M by the ATE1(K) and the job 2 of the embodiment is implemented. The circuit (the job 2) performs the boundary scan test of the memory power and logic circuit FB2, and the first pass of the τ circuit is performed. The test of the A/D converter FB3 can be described by changing the three modes. Test Example 1. When the boundary scan test of the memory circuit Fm is performed by the first BIST circuit BIST1, first, the first BIST circuit BIST1 is set as the active circuit by the 6181 selection signal bist_sel. That is, the BISI command control unit 12 generates the BIST selection signal BIST-SEL by writing 1 ' to the BIST address of the first BIST circuit BIST and 0 to the other BIST address. Next, the BISI command control unit 12 determines the start stop signal 31 201009369 31916pif START/STOP. Upon receiving the start/stop signal START/ST〇p, the pattern generator (false random pattern generator) built into the BIST circuit BIST1 starts generating a prescribed test pattern. The test pattern will pass through a daisy chain of flip-flops or latches formed in the memory circuit FBI. The BIST circuit BIST1 ' compares the input pattern of the daisy chain with the output pattern and determines that it is consistent and inconsistent. As a result, it is determined whether or not the memory circuit FB1 is good or not, and the data indicating the result of the determination is stored in a predetermined address of the memory area (memory or scratchpad) in the DUT2. Then, the BISI command control unit 12 specifies the address of the data indicating the determination result by the test data output signal DATA-OUT', and reads the data indicating the result of the determination. Test Example 2. The first BIST circuit BIST1 can also operate in another mode (second mode). In the second mode, instead of using the pattern generator built in the DUT 200, a pattern generator built in the ATE1 is used to generate a predetermined pattern, and is supplied to the ATE 100 as a test material input signal D ATA _ in. * Ο At this time, first, the first BIST circuit BIST1 is set to the second mode by the BIST selection signal BIST-SEL. Then, the start/stop signal START/STOP is determined, and the predetermined pattern ' is supplied to the first BIST circuit BIST1 via the test control bus BUS3 by the test data input signal DATA-IN. The test pattern is stored in a predetermined address of a memory area (memory or scratchpad) in the DUT 200 via a daisy chain ' in the memory circuit FBI. 32 201009369 31916pif Next, the BISI command control unit 12 specifies a predetermined address by reading the data output signal DATA-OUT and reads the data. The test pattern of the daisy chain is passed through the test control bus BUS3 as a test data output k number DATA-OUT is returned to the ATE 100. The ATE 100 compares the test pattern supplied to the DUT 200 with the returned test pattern to determine whether the DUT 200 is good or not. The same test as in Test Example 1 and Test Example 2 can be realized by the second BIST circuit with respect to the logic circuit FB2'. Test Example 3. The 3BIST circuit BIST3 performs a test by connecting a D/A converter and an A/D converter in series in a certain mode (first and second modes). In this mode, if the digital signal 01 is supplied to the input of the D/A converter, the digital signal D1 is converted into the analog signal A1, and the analog signal A1 is converted into a digital signal by the A/D converter. In the first mode, the digital value D1 is generated by a pattern generator built in the DUT 200. The 3rd BIST circuit BIST3 compares the digital value D1 with D2. The data indicating the comparison result is output to the ATE1〇〇 as the test data output signal DATA-OUT. In the second mode, the digital value D1 input to the D/A converter is supplied from the ATE 100 by the test data input signal DATA-IN. The digital value d2 outputted from the A/D converter is returned to the ATE 100 as the test data output signal DATA-0UT. The ATE 100 compares the test pattern supplied to the DUT 200 with the returned test pattern to determine whether the DUT 200 is good or not. 33 201009369 31916pif In the third mode, the A/D converter is separated from the D/A converter. As shown in Fig. 4, an arbitrary waveform generator is mounted as the analog BIST circuit BIST3' and a known analog waveform from the arbitrary waveform generator is supplied to the input of the a/d converter. The digital signal generated by the A/D converter is tested by the analog BIST circuit BIST3 itself or by comparing the expected value by ATE1 ’ to test the A/D converter. The present invention has been described in terms of embodiments, but the embodiments are merely illustrative of the principles and applications of the present invention, without departing from the scope of the claims.

In the scope of the inventive concept, many modifications and arrangements can be made to the embodiment. Fig. 6 is a block diagram showing a configuration of a DUT 2A according to a modification. The DUT 200 of Fig. 2 has a configuration in which a plurality of bisT circuits BIST1 to BIST5 are connected in a tree shape to the BISI control circuit 202. On the other hand, in the modified example, the plurality of BIST circuits BIST1 to BIST5 and the magic control circuit 2〇2 can be connected via the ring bus. [Industrial Applicability] The present invention can be applied to test technology. While the present invention has been described above by way of example, the invention is not intended to be limited to the scope of the present invention, and may be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a test system including an ATE and a DUT according to an embodiment. ' 34 201009369 31916pit Figure 2 is a diagram showing the control of the bus bar format via test. Timing diagram of the operation of the control signal that is input = the two-step control unit. Fig. 4 is a block diagram showing an example of the specific configuration of a plurality of functional blocks 4 and a plurality of bist electrical DUTs. Figure 5A is a block diagram showing the construction of a DUT having an analog BIST circuit correction function.

Fig. 6 is a block diagram showing a configuration of a DUT according to a modification. [Main component symbol description]

100 : ATE P1 : Digital I/O 埠 P2 : Analog I/O 埠 P3 : Test I/O 埠 P4 : Digital I/O 埠 P5 : Analog I/O 埠 P6 : Test I/O 埠 P7 : Correction埠BUS 1 : Digital main bus BUS2 : Analog main bus BUS3 : Test control bus BUS4 : Correction bus 10 : Test program 12 : BISI command control unit 14 · Functional test unit 35 201009369 31916pif

16: RF test unit 18: Optical I/O test unit 20: DC test unit 22: BISI synchronization control unit 200: DUT 202: BISI control circuit (interface circuit) 204: Input/output buffer 208: Input/output buffer FBI: Memory circuit FB2: logic circuit FB3: D/AA/D converter FB4: analog circuit FB5: analog I/O circuit 210: digital BIST group 212: analog BIST group 214: digital block 216: analog block 30: memory Body circuit 32: base frequency circuit FBLK1~FBLK5: function block 34: A/D converter

36 : LPF 38 : Mixer 40 : Local oscillator 201009369 jiyiopu

42: Image removal filter 44: LNA 46: BPF 50: Memory BIST circuit 52: Logic BIST circuit 54: Analog BIST circuit 56: Analog BIST circuit 58 · Analog BIST circuit 60: Analog BIST circuit 62: Analog BIST circuit 64 : Analog BIST Circuit 70: Switch Matrix 300: Test System

37

Claims (1)

201009369 31916pif VII. Application for patent circle: The test device is a test of semiconductor components: the material of the conductor is pure: μ, the characteristic is out, ίΓίΓ, the block is input and output through the main m stream. The signal processing of the 仃 疋 ; ; ; ; ; ; ; 多个 多个 多个 多个 多个 多个 多个 多个 多个 多个 多个 多个 多个 多个 多个 多个 多个 多个 多个 多个 多个 多个 多个 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号... The interface Wei is connected to the upper device via a different control bus that is different from the above-mentioned main slave, receives the control signal from the top, and is based on the above (4) trusting the plurality of controls] and is designated by the above-mentioned controller The test result letter ' can be read by the above test device via the above test control bus bar. The above test device includes: a beta 'y test unit via which the semiconductor component is fed through the main bus bar Transmitting and receiving a line signal, causing at least one of the functional blocks to perform the predetermined signal processing; and the control unit generating a first control signal and a second control signal, and the first control signal is coupled to the test control bus The second control signal is supplied to the semiconductor element, wherein the first control signal is individually controlled by the plurality of BIST circuits in the semiconductor element, and the second control signal is used by the BIST circuit The above test result signal is electrically read from the interface in the above semiconductor element. A 38 201009369 31916pif By the above control, it is characterized in that whether or not the first control signal is included in the tenth or fourteenth first control signal, at least one of the τ circuits in the setting circuit is active, and a plurality of L: Test device, wherein the above The above-described plurality of modes can be switched, and the selection field includes the mode data of the setting mode. The third control signal of the circuit is exhausted and the third control signal is: L; =: the control test piece 5 is set to the test test list as described in any of the first to third aspects of the patent scope. Further, a fourth control signal indicating the start and stop of the BIST circuit is generated, and the correction control is supplied to the semiconductor element via the test control. The test control unit generates an option signal according to any one of the items 1 to 3 of the patent application, which is inherent to at least one of the plurality of BIST circuits. Control, the test control bus bar includes another signal line for transmitting the option signal and different from the first and second control signals. 7. The test apparatus according to claim 2, wherein the test unit transmits and receives a signal to the semiconductor element, and the at least one functional block performs the predetermined signal processing. The control unit is configured to make the above-mentioned at least one functional block corresponding to the at least one functional block as the active circuit and perform the test on the at least one functional block as described in item 7 of the patent application scope. And a device, wherein the above-mentioned (4) synchronous lay-up 'four-step (four) unit receives the above-mentioned control money generated by 23170, and outputs the control signal in synchronization with the test rate of the test unit. The test circuit described in paragraphs 1 to 3 of the patent specification (4) is shared between multiple functional blocks. (4) The test device is input into the school according to the flow chart described in item 1 to item 3 of the profit range. The above-mentioned shortcut circuit can be determined by using the calibration method. The test unit is configured to generate the calibration unit, obtain the BIST circuit to perform the test result of the calibration, and generate a 11.-type swivel element for correcting the TM circuit according to the above== The method is characterized in that: ", input and output of signals via the main bus, "signal processing execution of the lamp", and energy path, for each of the plurality of functional blocks : the digital test, and generate and test the 201009369 · 31916pif 'interface circuit, receive the control signal that is rotated from the test device via the test control production line different from the above main bus, and based on the above control signal A plurality of BIST circuits are controlled, and the test result signal specified by the control signal can be read by the test shake via the test control bus. 12. The semiconductor device of claim 5, wherein the control signal comprises at least: 〃 ❹ selecting (4), setting whether to enable any one of the plurality of BIST circuits to be an active circuit; and testing a data input signal And including the test pattern to be supplied to the BIST circuit set as the active circuit; and the BIST circuit set to be the active circuit by the selection signal receives the test data input signal, and tests the corresponding functional block. 13. The semiconductor device according to claim 12, wherein at least one of the plurality of BIST circuits is configured to be switched in a plurality of modes, wherein the interface circuit is based on mode data included in the chat towel. To set the mode of the above BIST circuit. 14. The semiconductor device according to claim 12, wherein the BIST circuit set as the active circuit by the selection signal causes the test to be stopped based on the start-stop signal included in the control signal. The semiconductor device according to claim 11, wherein the at least one functional block performs the above-described predetermined signal processing in a state of 41 201009369 31916pif, corresponding to the at least one functional block The BIST circuit tests at least one of the above functional blocks. 16. The semiconductor device according to claim 11, wherein the BIST circuit having the same function among the plurality of BIST circuits is shared between the plurality of functional blocks. 17. The semiconductor device according to claim 11, wherein at least one of the BIST circuits is input with a correction signal via a calibration bus, and the BIST circuit uses the result of the correction signal processing as the test result signal. And the output. 42