JP2008102081A - Semiconductor inspection system, inspection device, semiconductor integrated circuit - Google Patents

Abstract

The number of probes required for inspection is reduced.
A signal superimposing circuit is disposed in an inspection apparatus and a clock signal is superimposed on a power source from a signal generator and output as a power source after being superimposed. The system LSI 100 extracts the clock signal in the signal extraction circuit 102, outputs the extraction signal 125, and operates the inspection control circuit 104 to inspect the circuit under measurement 101. By transmitting the inspection result to the determination device 205 of the measuring apparatus 200, it is possible to perform inspection with the present inspection system. As a result, it is not necessary to connect a probe to the clock terminal 113 that has been conventionally required, and the number of probes can be reduced.
[Selection] Figure 1

Description

  The present invention relates to a system for inspecting a semiconductor integrated circuit using an inspection apparatus.

  In recent years, the miniaturization of semiconductor processes and the integration of semiconductor devices have progressed, and the development of system LSIs has become mainstream. In the system LSI, integrated circuits having various functions are contained in one chip or one package.

  An important point for accurately guaranteeing the various functions in the inspection process is improvement of observability and controllability of the system LSI. In order to efficiently perform the observability and controllability described above, from the viewpoint of controllability, a control terminal for controlling the system LSI and an input signal terminal for supplying data to the system LSI are provided. From the viewpoint of observability, an output signal terminal for monitoring the state of the system LSI is necessary.

  In the manufacturing process of a semiconductor integrated circuit, as the miniaturization and integration progress, the number of chips that can be taken from one wafer continues to increase, and the trend has become more prominent with the arrival of 300 mm wafers in recent years. Therefore, in the manufacturing process of a semiconductor integrated circuit that is mass-produced, it becomes a problem how efficiently the inspection and burn-in can be realized at a low cost.

  One of the most effective means for solving the problem is a large number of simultaneous inspections. In particular, in recent years, an increasing number of cases apply wafer level burn-in in which burn-in is performed at the wafer level. If wafer level burn-in is applied, stress can be applied in batches on a wafer basis, so that the effect is increased in terms of efficiency and cost.

Similarly, in the probe inspection, if the number of samples is increased, the inspection time required for one wafer becomes enormous. Therefore, high efficiency can be achieved by inspecting a plurality of semiconductor integrated circuits such as 8, 16, 32, etc. at the same time. And reducing inspection costs.
JP 05-291368 A

  However, the issue here is the number of probes. In particular, in wafer level burn-in, the number of probes that can be connected per chip is limited due to the limitations of the apparatus, and therefore it is impossible to apply probes to all pads of the system LSI at the same time. Needless to say, the impact of this issue increases as the number of harvests increases.

  In addition, as described above, in the system LSI, since there are a large number of power supply terminals, GND terminals, control terminals, input signal terminals, output signal terminals, etc., the number of pads that require probes during wafer level burn-in tends to increase. The problem of the number of probes has become a more serious problem.

  The semiconductor inspection system according to the present invention is a system for inspecting a semiconductor integrated circuit using an inspection apparatus. The inspection apparatus includes a power supply device that generates power to be supplied to the semiconductor integrated circuit, a first probe for supplying the power generated by the power supply device to the semiconductor integrated circuit, and a signal for inspecting the semiconductor integrated circuit. A first signal generator to be generated, and a first signal superimposing circuit that superimposes the signal generated by the first signal generator on the power generated by the power supply device and supplies the signal to the first probe. The semiconductor integrated circuit includes: a first power supply terminal that receives power supply from the first probe; a first signal extraction circuit that extracts a signal superimposed on the power supply supplied to the first power supply terminal; And an inspection control circuit for inspecting the circuit under measurement based on the signal extracted by the signal extraction circuit.

  In the semiconductor inspection system, an inspection signal (for example, a clock signal or a control signal) of the semiconductor integrated circuit is superimposed on the power supply and supplied to the first power supply terminal of the semiconductor integrated circuit through the first probe. In the conventional inspection apparatus, the probe for supplying the inspection signal to the semiconductor integrated circuit and the probe for supplying the power are provided separately. However, according to the semiconductor inspection system, the inspection signal is supplied. The number of probes for doing so can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, substantially the same parts are denoted by the same reference numerals, and the description thereof will not be repeated.
<< First Embodiment >>
FIG. 1 is a block diagram showing the configuration of the semiconductor inspection system according to the first embodiment of the present invention.

  In FIG. 1, an inspection apparatus 200 is an apparatus for inspecting a system LSI 100, and includes power supply apparatuses 201 and 202, signal generators 203 and 204, a determination apparatus 205, a signal superimposing circuit 206, and probes P1 to P1. P4.

  The power supply device 201 generates a power supply voltage (VDD) and transmits it to the power supply line 221. The power supply device 202 generates a ground voltage (GND) and transmits it to the GND line 222. The GND line 222 is connected to the probe P2, and the ground voltage (GND) generated by the power supply device 202 is supplied to the GND terminal 112 of the system LSI 100 through the probe P2.

  The signal generator 203 is a device that generates a signal and transmits the signal to the signal line 223, and is generally called a pattern generator, and can generate an arbitrary signal at an arbitrary timing. In the present embodiment, the signal generator 203 generates a clock signal to be given to the system LSI 100.

  The signal generator 204 is a device that generates a signal and transmits the signal to the control signal bus 224, and is configured by arranging the same configuration as the signal generator 203 in parallel. In the first embodiment of the present invention, the signal generator 204 generates various control signals for controlling the system LSI 100. The control signal bus 224 is connected to the probe P4, and the signal generated by the signal generator 204 is supplied to the control terminal 115 of the system LSI 100 through the probe P4.

  The determination device 205 is a device that makes a determination by comparing a FLAG signal 225 that is an output signal from the inspection control circuit 104 of the system LSI 100 with a predetermined arbitrary value. The FLAG signal from the inspection control circuit 104 of the system LSI 100 is output to the FLAG terminal 114 and further supplied to the determination device 205 through the probe P3 of the inspection device 200. Further, in the inspection apparatus 200 of the present embodiment, the determination apparatus 205 and the signal generators 203 and 204 are synchronized, and an arbitrary expected value and the system LSI 100 are determined according to the output timing of the signal generators 203 and 204. The system LSI 100 is inspected by comparing with the output of.

  The signal superimposing circuit 206 superimposes the output signal 223 output from the signal generator 203 on the power supply line 221 that receives the power supply voltage (VDD) output from the power supply apparatus 201, and the superimposed result is a power supply after signal superimposition. A circuit 231 supplies the probe P1. For example, as shown in FIG. 1, the signal superimposing circuit 206 AC-couples the output signal 223 of the signal generator 203 to the power supply line 221, so that the AC component of the output signal 223 of the signal generator 203 and the power supply device are coupled. A power source 231 having a DC component of the power source line 221 from 201 is formed. It should be noted that a circuit capable of attenuating / amplifying the output signal 223 as necessary is preferably provided before the AC coupling.

  The system LSI 100 includes a circuit under test 101, a signal extraction circuit 102, a noise removal circuit 103, a test control circuit 104, a VDD terminal 111, a GND terminal 112, a clock terminal 113, a FLAG terminal 114, and a control terminal. 115.

  The circuit under test 101 is a circuit to be inspected in the system LSI 100.

  The inspection control circuit 104 is a circuit that performs control related to the inspection of the system LSI 100. For example, the inspection control circuit 104 generates control and control signals for the circuit under measurement 101 at the time of inspection, generates and inputs / outputs signals (data, clocks, etc.) given to the circuit under measurement 101, and controls signals given to the circuit under measurement 101. It has a function of determining a test result of the circuit under test 101, a function of generating a determination signal for the test result and outputting the same to the outside, and corresponds to a BIST circuit which is generally called.

  The signal extraction circuit 102 has a function of extracting a specific signal from the power supplied to the VDD terminal 111. For example, if the signal extraction circuit 102 is configured with a high-pass filter, a high-frequency component determined by the cutoff frequency of the high-pass filter is extracted, and the extracted signal is output as the extraction signal 125. It is further desirable to have a function of amplifying or attenuating the amplitude of the extracted signal as necessary and outputting it as the extracted signal 125.

  The noise removal circuit 103 is a circuit for removing a noise component superimposed on the power supplied to the VDD terminal 111 and supplying power to the system LSI 100. For example, the noise removal circuit 103 is configured by a low-pass filter or the like for removing a specific frequency component. By passing through the noise removal circuit 103, the noise component superimposed on the power supply can be removed. Then, the power supply from which noise has been removed is supplied to the system LSI 100 as the power supply 131 after noise removal.

  Next, a system combining the system LSI 100 and the inspection apparatus 200 will be described.

  First, the signal generator 203 of the inspection apparatus 200 generates a clock signal used in the system LSI 100 and transmits it as an output signal 223 to the signal superimposing circuit 206. Next, the signal superimposing circuit 206 superimposes the output signal 223 on the power supply line 221 to generate a power source 231 after signal superimposition. The power 231 after signal superimposition is supplied to the VDD terminal 111 of the system LSI 100 by the probe P1. The ground voltage (GND) generated by the power supply device 202 is supplied to the GND terminal 112 of the system LSI 100 by the probe P2, and the signal generated by the signal generator 204 is supplied to the control terminal 115 of the system LSI 100 through the probe P4. The In this way, the power supply 231 after signal superposition, the ground voltage (GND), and the control signal are transmitted from the inspection apparatus 200 to the system LSI 100.

  On the other hand, the system LSI 100 distributes the signal superimposed power source 231 supplied to the VDD terminal 111 to the signal extraction circuit 102 and the noise removal circuit 103. In the signal extraction circuit 102, the clock signal superimposed on the power source 231 after signal superimposition is extracted and transmitted to the inspection control circuit 104 as an extraction signal 125. Further, the noise removal circuit 103 supplies the noise-removed power supply 131 from which the superimposed clock signal, which is a noise component of the power supply, has been removed, as the power supply for the system LSI 100. The inspection control circuit 104 generates a clock signal 121, a control signal 122, and an input data signal 123 according to the contents of the control signal supplied to the control terminal 115, and transmits them to the circuit under test 101. The operation is performed according to the signal.

  An output data signal 124 is output to the inspection control circuit 104 as an operation result of the circuit under test 101. The inspection control circuit 104 determines the output data signal 124, generates a FLAG signal as a determination result, and outputs the FLAG signal to the FLAG terminal 114. The FLAG signal supplied to the FLAG terminal 114 is transmitted to the determination device 205 of the inspection device 200 by the probe P3.

  The determination device 205 of the inspection device 200 can inspect the system LSI 100 by comparing the content of the FLAG signal 225 with the expected value.

  Thus, according to the present system, it is not necessary to supply a clock directly to the clock terminal 113 of the system LSI 100 using a probe or the like, so that the number of probes can be reduced.

  Although an example in which the output signal 223 of the signal generator 203 is superimposed on the power supply line 221 is shown here, the output signal 223 of the signal generator 203 may be superimposed on the GND line 222. In this case, the signal superimposing circuit 206 superimposes the output signal 223 output from the signal generator 203 on the GND line 222 that receives the ground voltage (GND) output from the power supply device 202, and probes the superimposed result. The circuit is configured to be supplied to P2. On the system LSI 100 side, the signal extraction circuit 102 is configured as a circuit that extracts a specific signal from the ground voltage supplied to the GND terminal 112, and the noise removal circuit 103 is configured as a ground supplied to the GND terminal 112. The circuit is configured as a circuit for removing a noise component superimposed on the voltage and supplying a ground voltage to the system LSI 100.

  Further, although the signal extraction circuit 102 has been described with the configuration of a high-pass filter, the extraction signal 125 may be generated using a configuration of a band-pass filter. In this case, since the frequency component of the necessary signal can be specified, the reliability of the extracted signal is increased.

Although the description has been made on the premise of the BIST circuit using the SCAN circuit, other inspections can be performed according to the control signal. For example, a temperature measurement circuit can be built in the inspection control circuit 104 to make a determination on temperature, and a current measurement circuit can be built in the inspection control circuit 104 to measure current. Similarly, it is possible to perform voltage measurement by incorporating a voltage measurement circuit, and it is also possible to perform various inspections, such as enabling frequency measurement by incorporating a frequency measurement circuit. It becomes possible.
<< Second Embodiment >>
FIG. 2 is a block diagram showing a configuration of a semiconductor inspection system according to the second embodiment of the present invention. The difference between FIG. 2 and FIG. 1 is that the configuration of the system LSI 100 is different. Hereinafter, the second embodiment will be described focusing on the differences from the first embodiment.

  In the system of FIG. 2, the inspection control circuit 104 is configured as a plurality of independent BIST circuits BIST_A, BIST_B, and BIST_C. Each of the BIST circuits BIST_A to C is a circuit that performs control related to the inspection of the circuit blocks A, B, and C corresponding to the circuit under test 101. Each BIST circuit BIST_A-C generates clock signals 121A-C, control signals 122A-C, and input data signals 123A-C according to the contents of the control signals from the BIST control circuit, and transmits them to the circuit blocks A-C. The circuit blocks A to C operate according to these signals. Output data signals 124A to 124C are output to the BIST circuits BIST_A to C as the operation results of the circuit blocks A to C, respectively. Each BIST circuit BIST_A to C performs determination on the output data signals 124A to 124C, and outputs the determination result to the BIST control circuit. The BIST control circuit generates a FLAG signal based on the determination result from each BIST circuit BIST_A to C, and outputs it to the FLAG terminal 114. In the inspection control circuit 104 configured as described above, if only an arbitrary BIST circuit is operated in accordance with the contents of the control signal bus 224, the power supply current at the time of inspection can be reduced. In other words, since power supply noise can be reduced, the reliability of signals superimposed on the system LSI 100 is improved.

  In the system of FIG. 2, by providing a frequency conversion circuit, the clock signals 121A to 121C for operating the circuit under test 101 are signals having a frequency component different from that of the extraction signal 125 generated by the signal extraction circuit 102. . For example, by inputting a clock obtained by dividing the extracted signal 125 or a clock multiplied by a PLL as the clock signals 121A to 121C, the frequency components of the power supply noise and the frequency components of the clock signals 121A to 121C are different. . As a result, the reliability of the superimposed signal (here, the clock signals 121A to 121C) is increased.

  In the system of FIG. 2, the signal extraction circuit 102 is configured using a plurality of bandpass filters having different frequency bands so that signals of a plurality of frequency bands can be extracted. Similarly, with respect to the frequency of the signal to be superimposed by the signal superimposing circuit 206, a circuit that superimposes signals of different frequency bands from a plurality of signal generators 203 is configured in accordance with the signal extraction circuit 102 and transmitted to the system LSI 100.

  The signal extraction circuit 102 can extract a plurality of signals having different frequency bands. By transmitting the signal to the inspection control circuit 104, the inspection control circuit 104 can handle signals having a plurality of frequencies. Thereby, an actual operation test of the circuit under test 101 can be performed by assigning a frequency according to the circuit under test 101.

  In addition, a plurality of independent BIST circuits BIST_A to C can be operated at respective frequencies. In this case, the frequency components of power supply noise are diffused because they operate with signals having different frequency bands.

Further, since signals having a plurality of arbitrary frequencies are input to the inspection control circuit 104, it can be understood that signals having an arbitrary frequency are correctly input by providing the inspection control circuit 104 with a frequency detection function. In other words, since a plurality of arbitrary frequency signals are not input in a state other than the inspection, the inspection control circuit 104 can recognize that it is in the inspection state. As a result, it is possible to reduce the number of signals of the control signal bus 224 input from the control terminal 115, which is necessary for recognizing the inspection state.
<< Third Embodiment >>
FIG. 3 is a block diagram showing a configuration of a semiconductor inspection system according to the third embodiment of the present invention. The difference between FIG. 3 and FIG. 1 is that the configuration of the system LSI 100 is different, and that the clock generation circuit 108 is arranged at the subsequent stage of the signal extraction circuit 102. Further, the signal content of the post-signal superimposing power supply 231 output from the inspection apparatus 200 is different from the first embodiment. Hereinafter, the third embodiment will be described with a focus on differences from the first embodiment.

  First, in the inspection apparatus 200, a synchronization pattern output from the signal generator 203 at an arbitrary fixed cycle is output as the output signal 223, and the synchronization pattern is superimposed by the signal superimposing circuit 206. In addition, the format of the synchronization pattern of the output signal 223 has an arbitrarily determined pattern configuration.

  Next, in the system LSI 100, the clock generation circuit 108 is a circuit that generates a clock based on a synchronization pattern that is output at an arbitrary fixed period, and includes, for example, a PLL circuit and a synchronization pattern detection circuit.

  In the system of FIG. 3, a signal superimposed power source 231 on which a synchronization pattern output at an arbitrary fixed period is superimposed is transmitted from the inspection apparatus 200 to the system LSI 100.

  In the system LSI 100, the extraction signal 125 from the signal extraction circuit 102 is input to the clock generation circuit 108. The synchronization pattern detection circuit of the clock generation circuit 108 detects the synchronization timing output by the synchronization pattern by comparing the input synchronization pattern with any predetermined pattern configuration, and transmits it to the PLL circuit. In the PLL circuit, an arbitrary multiplied clock is generated based on the synchronization timing obtained there, and is transmitted to the inspection control circuit 105 as the main clock 142. The inspection control circuit 104 uses the clock 142 to inspect the circuit under test 101 and transmits the result to the inspection apparatus 200.

In the third embodiment, the use of the synchronization signal eliminates the need to operate the signal for times other than the synchronization pattern. For example, when a 10 MHz clock is required, the first embodiment always has to superimpose the clock signal by the signal superimposing circuit 206, but in the third embodiment, the synchronization pattern is a low-speed cycle, In addition, by setting the duty ratio of the synchronization pattern to 999: 1 or the like, the time that the power source 231 is touched after signal superimposition is two thousandths, so that it is possible to reduce the power noise caused by superimposing the signal. It becomes.
<< Fourth Embodiment >>
FIG. 4 is a block diagram showing a configuration of a semiconductor inspection system according to the fourth embodiment of the present invention. 4 differs from FIG. 3 in that a delay circuit 210 is provided in the inspection apparatus 200 and an OR circuit 160 is provided in the system LSI 100. FIG. Hereinafter, the fourth embodiment will be described focusing on differences from the third embodiment.

In the system of FIG. 4, the extraction signal 125 is output from the FLAG terminal 114 of the system LSI 100. Control is performed by the OR circuit 160 subsequent to the inspection control circuit 104 so as to output when the inspection status by the inspection control circuit 104 is OK, and not output when the inspection status is NG, and input to the determination device 205. . The output signal 223 of the signal generator 203 is input to the determination device 205 after passing through the delay circuit 210 (for synchronization with the LSI 100). As a result, the signal 223 generated by the signal generator 203 is the same as the signal 225 output from the FLAG terminal 114 of the LSI 100 (in this case, the output signal of the signal generator 203), so that comparison can be performed. Become. This operation improves the reliability of the signal generated by the signal generator 203 and the reliability of the determination result.
<< Fifth Embodiment >>
FIG. 5 is a block diagram showing a configuration of a semiconductor inspection system according to the fifth embodiment of the present invention. The difference between FIG. 5 and FIG. 3 is that the configuration of the inspection apparatus 200 is different, a signal extraction circuit 207 is newly provided, the signal extraction circuit 207 is connected to the power supply 231 after signal superimposition, and is arranged in the previous stage of the determination apparatus 205. It is a point. Further, in the system LSI 100, the encoding circuit 150 is disposed at the subsequent stage of the inspection control circuit 104, the signal superimposing circuit 151 is disposed at the subsequent stage of the encoding circuit 150, and the signal is superimposed on the power source 231 after signal superimposition, The decoding circuit 110 is disposed at the subsequent stage of the signal extraction circuit 102, and the chip ID circuit 109 is disposed at the subsequent stage of the inspection control circuit 104. The decoding circuit 110 is a circuit that decodes a signal input in a predetermined format.

  An example of the data format is shown in FIG. The timing of the data format is predetermined. A reference synchronization signal is detected, and the clock generation circuit 108 generates a clock between the synchronization signal and the next synchronization signal. Here, it is 10,000 CLOCK. This clock cycle is defined as 1T. The input data is sampled using this clock. The output data is also output in synchronization with this clock. The pulse width used for the synchronization signal is configured with a pulse width that is not used in the subsequent control signal, chip ID data, input data, and output data. In order to prevent erroneous detection, reliability is improved by combining the minimum pulse width (here, 3T) and the maximum pulse width (here, 11T) into a synchronization signal.

  Next, a system combining the system LSI 100 and the inspection apparatus 200 will be described.

  First, the signal composed of the synchronization pattern, the control signal area, the chip ID code area, and the data area in the above-described format is superimposed on the post-superimposition power source 231 output from the inspection apparatus 200.

  The signal extraction circuit 102 has a filter configuration that can extract data from 3T to 11T having different frequency components, and outputs a signal extraction signal 125 composed of a synchronization pattern, a control signal region, a chip ID code region, and a data region. , To the clock generation circuit 108 and the decoding circuit 110.

  The decoding circuit 110 receives the extraction signal 125 from the signal extraction circuit 102 and the main clock 142 generated by the clock generation circuit 108, and receives the synchronization pattern and other areas (control signal area, chip ID code area, data area). And the signals in the control signal area, chip ID code area, and data area are extracted. The extracted control signal area, chip ID code area, and data area signals are transmitted to the inspection control circuit 104 as a decoded signal 143.

  In the inspection control circuit 104, the circuit under test 101 is inspected and determined using the decoded signal 143 and the main clock 142. In the third embodiment, the circuit under test 101 is inspected and determined using only the main clock 142. However, according to the present embodiment, the amount of data is larger than in the third embodiment, so that the device under test is measured. The controllability of the circuit 101 is increased. The inspection control circuit 104 outputs the determination result as an output signal 145 to the encoding circuit 150 and transmits the output control signal 144 to the encoding circuit 150. The encoding circuit 150 performs encoding according to a predetermined format based on the output signal 145 and the output control signal 144, and outputs an encoded signal 146. The signal superimposing circuit 151 includes the same elements as the signal superimposing circuit 206, and superimposes a signal on the power source 231 after signal superimposition according to the encoded signal 146.

  As described above, in this embodiment, the control signal area is provided in the data format, and the operation of the inspection control circuit 104 is controlled using the data in the control signal area. For example, a circuit that decodes data in the control signal area is built in the inspection control circuit 104, and inspection control is performed according to the decoding result. As a result, the number of dedicated probes P4 for supplying control signals to the system LSI 100 can be reduced.

  In the inspection apparatus 200, the signal extraction circuit 207 extracts the data of the encoded signal 146 from the power supply 231 after signal superimposition, generates a FLAG signal 225, transmits it to the determination apparatus 205, and determines the FLAG signal 225 by the determination apparatus 205. . The signal extraction circuit 207 includes the same elements as the signal extraction circuit 102.

  Thus, in this embodiment, since the contents of the FLAG signal 225 are superimposed on the power supply 231 after signal superimposition, the number of probes P3 for obtaining the FLAG signal 225 from the FLAG terminal 114 of the system LSI 100 can be reduced. It becomes possible.

  Also, by giving the input / output polarity to the signal format superimposed on the power source 231 after signal superimposition, it is possible to distinguish the input / output polarity of the signal, thereby reducing the probability of erroneous determination occurrence of the determination device 205. . For example, the inspection apparatus 200 first outputs a signal to the system LSI 100 including a synchronization pattern, a data area, a control signal area, and a chip ID code area, and then includes a synchronization pattern and an output data area. Receive a signal. By repeating this, bidirectional communication can be performed in a time-sharing manner, so that the input / output polarities of the signals can be distinguished, and the probability of occurrence of erroneous determination by the determination device 205 can be reduced. In this case, the main pattern 142 of the system LSI 100 is more stable in this inspection system when the synchronization pattern is always output from the inspection apparatus 200 and the output data area and the chip ID code area are output from the system LSI 100 accordingly. Therefore it is desirable.

  Further, in this embodiment, a chip ID code area is provided in the data format, a chip ID circuit 109 is disposed after the inspection control circuit 104, and the data in the chip ID code area and the data of the chip ID circuit 109 are inspected. Comparison is made at 104. As a result, for example, when a plurality of system LSIs 100 are inspected at once, control of an arbitrary system LSI 100 can be performed by combining the data in the chip ID code area and the data in the control signal area. .

  FIG. 7 shows an example in which the chip ID circuit 109 is used when a plurality of system LSIs 100a and 100b are inspected collectively. In FIG. 7, only main components are shown, and some components are omitted. The inspection control circuit 104 generates a necessary signal to be supplied to the circuit under test 101. By using the chip ID, the chip ID placed on the signal and the ID number assigned to each of the system LSIs 100a and 100b are used as an ID decoder. It becomes possible to collate and control with. For example, when an instruction for outputting a test result is input to the chip 100a having the ID number 0000, the test result having the ID number 0000 can be enabled and output by the tri-state buffer. At this time, since the chip 100b with ID number 0001 is not its own number, the tri-state buffer is disabled and the inspection result is not output. As a result, the chips can be individually controlled. Similarly, it is possible to control whether or not the input given to the circuit under test 101 is operated according to the ID.

  In this embodiment, since the control signal area issues an output command for the output control of the FLAG signal 225 and the system LSI 100 is specified by the data in the chip ID code area, only the specified system LSI 100 can output the FLAG signal 225. It becomes. This eliminates the need to prepare a plurality of determination devices 205 that receive a plurality of FLAG signals 225.

  Further, by interpolating the chip ID code into the output signal 145, the system LSI 100 can be identified based on the chip ID code even when a plurality of system LSIs 100 are inspected collectively. Thereby, since the power source 231 after signal superposition can be shared by a plurality of system LSIs, the configuration of the inspection apparatus 200 can be simplified.

The above-described format is composed of a synchronization pattern, a data area, a control signal area, and a chip ID code area. However, adding a redundant code area, the decoding circuit 110 performs error detection based on the redundant code or By having an error correction function, it is possible to detect or correct that there is an error in the received data, and the reliability of the data of the decoded signal 143 is increased. In addition, a redundant code is interpolated in the encoded signal 146 output from the encoding circuit 150, and the determination device 205 is provided with a function of performing error detection or error correction based on the redundant code. The probability of determination occurrence can be reduced.
<< Sixth Embodiment >>
FIG. 8 is a block diagram showing a configuration of a semiconductor inspection system according to the sixth embodiment of the present invention. The difference between FIG. 8 and FIG. 1 is that the configuration of the inspection apparatus 200 is different. First, the differential signal superimposing circuit 406 is arranged at the subsequent stage of the power supply line 221 output from the power supply apparatus 201 and the GND line 222 output from the power supply apparatus 202. The output signal 223 output from the signal generator 203 is superimposed as a differential signal to generate a differential power supply signal 232 and a differential GND signal 233.

  The system LSI 100 includes a differential signal extraction circuit 302 that extracts signals from the differential power supply signal 232 and the differential GND signal 233, extracts a signal, and transmits the signal to the inspection control circuit 104. In addition, since the differential signal is superimposed on the power supply and GND, it is configured with a noise removal circuit 103 for removing each superimposed signal.

  An example of the circuit configuration of the differential signal superimposing circuit 406 includes a differential output amplifier and the signal superimposing circuit 206. The output signal 223 is first converted into a differential signal by the differential output amplifier. The signal superimposing circuit 206 superimposes the signal using the differential signal superimposed on the power supply, and outputs it as a differential power supply signal 232. Similarly, the output signal 223 is converted into a differential signal by a differential amplifier, the signal is superimposed by the signal superimposing circuit 206 using the differential signal superimposed on the GND line 222 and GND, and the differential GND signal 233 is output. .

  An example of the circuit configuration of the differential signal extraction circuit 302 includes an offset voltage removal circuit, a differential input amplifier, and the signal extraction circuit 106. The differential power supply signal 232 and the differential GND signal 233 are respectively converted into offset voltages. Input to the removal circuit to remove the DC component. The differential signal after offset removal is received on the + side and − side of the differential input amplifier, a signal is generated based on the voltage difference of the differential signal, and is transmitted to the signal extraction circuit 106. The signal extraction circuit 106 generates an output clock signal 124 and transmits it to the inspection control circuit 106.

  A semiconductor inspection system according to the sixth embodiment of the present invention can perform a semiconductor inspection in the same manner as in the first embodiment by combining the inspection apparatus 200 and the system LSI 100.

  In the sixth embodiment of the present invention, a signal is obtained from both the power supply side and the GND side by using a differential signal as a signal to be superimposed. Therefore, the signal superimposed power source 231 of the first embodiment is used. The reliability of the signal is further improved. Since the signal amplitude level to be superimposed can be lowered by improving the reliability of the signal, an effect of reducing power supply noise accompanying the signal superposition can be obtained.

Moreover, although it demonstrated using 1st Embodiment, it can be applied also to 2nd-4th embodiment similarly using a differential signal.
<< Seventh Embodiment >>
FIG. 9 is a block diagram showing a configuration of a semiconductor inspection system according to the seventh embodiment of the present invention. 9 and 5 are different in the configuration of the inspection apparatus 200. First, the differential signal superimposing circuit 406 described in the sixth embodiment outputs the power line 221 output from the power supply apparatus 201 and the power supply apparatus 202. The signal output from the signal generators 203 and 204 is superimposed as a differential signal on the GND line 222 to be generated, and a differential power supply signal 232 and a differential GND signal 233 are generated instead of the signal extraction circuit 207. The signal extraction circuit 407 is arranged.

  The system LSI 100 includes the differential signal extraction circuit 302 that extracts signals from the differential power supply signal 232 and the differential GND signal 233 described in the sixth embodiment, and performs signal extraction, and the inspection control circuit 104 Make a transmission. In addition, since the differential signal is superimposed on the power supply and GND, the differential signal superposition is performed in place of the signal superimposition circuit 151, and the point that the noise removal circuit 103 is configured to remove each superimposed signal. The circuit 351 is arranged.

  Further, the differential signal extraction circuit 407 is composed of the same elements as the differential signal extraction circuit 302, thereby extracting the data of the encoded signal 146, generating the FLAG signal 225, and transmitting it to the determination device 205, The determination unit 205 determines the FLAG signal 225.

  Further, the differential signal superimposing circuit 351 is composed of the same elements as the differential signal superimposing circuit 406 and superimposes signals on the differential power supply signal 232 and the differential GND signal 233 in accordance with the encoded signal 146.

  The semiconductor inspection system according to the seventh embodiment of the present invention can perform the semiconductor inspection similarly to the fifth embodiment by combining the inspection apparatus 200 and the system LSI 100.

Also, by using differential signals, the signal amplitude level to be superimposed can be lowered by improving the signal reliability as in the sixth embodiment and improving the signal reliability. An effect of reducing power supply noise caused by superimposing signals can be obtained.

<< Eighth Embodiment >>
FIG. 10 is a block diagram showing a configuration of a semiconductor inspection system according to the eighth embodiment of the present invention. The difference between FIG. 10 and FIG. 9 is that the configuration of the inspection apparatus 200 is different, and the power line 221 output from the power supply apparatus 201 and the GND line 222 output from the power supply apparatus 202 described in the sixth embodiment are differentiated. A probe P5 for outputting the power supply line 221 to the outside and a probe P6 for outputting the GND line 222 to the outside are provided in addition to being input to the signal superimposing circuit 406.

  In the system LSI 100, the power supply and GND are provided with a bypass circuit, and the power supply line 221 which is a power supply on which no signal is superimposed is connected to the power supply 131 after noise removal through the probe P5 and the terminal 116, and after noise removal. A GND line 222, which is a GND on which no signal is superimposed, is connected to the GND 131 through a probe P6 and a terminal 117.

  It goes without saying that the power supply and GND can be strengthened by configuring a bypass circuit for the power supply and GND. In particular, in a test using a probe, there is a limit on an allowable current amount that can flow per pin. For example, when the allowable current amount per pin is 100 mA, the consumption current of the LSI that can be inspected in the seventh embodiment is limited to 100 mA or less. By adopting the configuration shown in FIG. 10, a bypass circuit for two pins is inserted, so that an LSI with a current consumption of up to 300 mA can be inspected. Further, the bypass circuit can also be used as a power supply and GND during normal use other than inspection. In other words, the terminals for inputting / outputting the differential power supply signal 232 and the differential GND signal 233 of the system LSI 100 can be used as test-dedicated terminals. In addition, by providing a malfunction prevention circuit (for example, a Schmitt inverter as a noise removal circuit) for the test dedicated terminal, it is possible to prevent malfunction during normal use other than inspection and not affect the operation of the system LSI 100. It is.

  The present invention can be applied to general inspection of semiconductor integrated circuits, but in particular, since it is possible to reduce the number of probes in inspection using probes, probe inspection for simultaneously inspecting a plurality of wafers or a batch of wafers. Wafer level burn-in, etc., in which inspection is performed in particular, is particularly effective.

1 is a block diagram showing a configuration of a semiconductor inspection system according to a first embodiment. It is a block diagram which shows the structure of the semiconductor inspection system by 2nd Embodiment. It is a block diagram which shows the structure of the semiconductor inspection system by 3rd Embodiment. It is a block diagram which shows the structure of the semiconductor inspection system by 4th Embodiment. It is a block diagram which shows the structure of the semiconductor inspection system by 5th Embodiment. It is a figure which shows an example of a signal format. It is a block diagram which shows an example which used the chip ID circuit when test | inspecting several system LSIs collectively. It is a block diagram which shows the structure of the semiconductor inspection system by 6th Embodiment. It is a block diagram which shows the structure of the semiconductor inspection system by 7th Embodiment. It is a block diagram which shows the structure of the semiconductor inspection system by 8th Embodiment.

Explanation of symbols

100 system LSI
101 circuit under test 102 signal extraction circuit 103 noise removal circuit 104 inspection control circuit 108 clock generation circuit 110 decoding circuit 111 VDD terminal 112 GND terminal 113 clock terminal 114 FLAG terminal 115 control terminal 150 encoding circuit 151 signal superposition circuit 160 OR circuit 200 Inspection device 201 Power supply device (VDD output)
202 Power supply (GND output)
203 Signal generator (clock signal)
204 Signal generator (control signal)
205 Determination Device 206 Signal Superimposing Circuit 207 Signal Extracting Circuit 210 Delay Circuit 302 Differential Signal Extracting Circuit 351 Differential Signal Superimposing Circuit 406 Differential Signal Superimposing Circuit 407 Differential Signal Extracting Circuits P1 to P6 Probe

Claims (27)

A system for inspecting a semiconductor integrated circuit using an inspection apparatus,
The inspection device includes:
A power supply device for generating power to be supplied to the semiconductor integrated circuit;
A first probe for supplying power generated by the power supply device to the semiconductor integrated circuit;
A first signal generator for generating a signal for inspecting the semiconductor integrated circuit;
A first signal superimposing circuit that superimposes the signal generated by the first signal generator on the power source generated by the power supply device and supplies the signal to the first probe;
The semiconductor integrated circuit is:
A first power supply terminal receiving power supply from the first probe;
A first signal extraction circuit for extracting a signal superimposed on a power source supplied to the first power source terminal;
An inspection control circuit that inspects the circuit under measurement based on the signal extracted by the first signal extraction circuit;
A semiconductor inspection system characterized by that. In claim 1,
The power supply device
Generate power supply voltage and ground voltage,
The first probe includes:
A second probe for supplying a power supply voltage generated by the power supply device to the semiconductor integrated circuit;
A third probe for supplying a ground voltage generated by the power supply device to the semiconductor integrated circuit,
The first power supply terminal is
A second power supply terminal that receives supply of power supply voltage from the second probe;
A third power supply terminal that receives a ground voltage from the third probe,
A semiconductor inspection system characterized by that. In claim 2,
The first signal superimposing circuit includes:
Supplying the second probe with the signal generated by the first signal generator superimposed on the power supply voltage generated by the power supply device;
The first signal extraction circuit includes:
Extracting a signal superimposed on a power supply voltage supplied to the second power supply terminal;
A semiconductor inspection system characterized by that. In claim 2,
The first signal superimposing circuit includes:
A signal generated by the first signal generator is superimposed on a ground voltage generated by the power supply device and supplied to the third probe;
The first signal extraction circuit includes:
Extracting a signal superimposed on a ground voltage supplied to the third power supply terminal;
A semiconductor inspection system characterized by that. In claim 2,
The first signal superimposing circuit includes:
A signal generated by the first signal generator is differentially superimposed on a power supply voltage and a ground voltage generated by the power supply device and supplied to the second and third probes;
The first signal extraction circuit includes:
Extracting a differentially superimposed signal between a power supply voltage supplied to the second power supply terminal and a ground voltage supplied to the third power supply terminal;
A semiconductor inspection system characterized by that. In claim 1,
The semiconductor integrated circuit is:
A noise removing circuit that removes a noise component superimposed on a power source supplied to the first power source terminal and supplies the noise component to an internal circuit;
A semiconductor inspection system characterized by that. In claim 1,
The inspection control circuit includes a plurality of BIST circuits,
Each of the plurality of BIST circuits includes:
Inspecting the corresponding part of the circuit under test,
The inspection control circuit includes:
Activating / deactivating each of the plurality of BIST circuits according to a control signal;
A semiconductor inspection system characterized by that. In claim 1,
The frequency of the signal transmitted from the control inspection circuit to the circuit under test is different from the frequency of the signal extracted by the first signal extraction circuit.
A semiconductor inspection system characterized by that. In claim 1,
The first signal generator is
A plurality of signal generating units each generating a signal of a different frequency;
The first signal extraction circuit includes:
A plurality of signal extraction units for extracting signals having different frequencies from among signals superimposed on a power source supplied to the first power source terminal;
A semiconductor inspection system characterized by that. In claim 9,
The inspection control circuit includes:
It has a function of detecting a plurality of arbitrary frequency signals, generates a control signal according to a plurality of arbitrary frequency signal states, and controls the circuit under test.
A semiconductor inspection system characterized by that. In claim 1,
The signal generated by the first signal generator includes a synchronization signal having an arbitrary fixed period,
The semiconductor integrated circuit is:
A clock generation circuit for generating a clock signal based on the synchronization signal extracted by the first signal extraction circuit;
The inspection control circuit includes:
Inspecting the circuit under test using a clock signal generated by the clock generation circuit;
A semiconductor inspection system characterized by that. In claim 11,
The signal generated by the first signal generator further includes an arbitrary data signal following the synchronization signal,
A semiconductor inspection system characterized by that. In claim 11,
The signal generated by the first signal generator further includes a control signal following the synchronization signal,
A semiconductor inspection system characterized by that. In claim 1,
The signal generated by the first signal generator includes a chip ID code of the inspection target chip,
The semiconductor integrated circuit is:
A chip ID circuit for transmitting a chip ID code of the semiconductor integrated circuit to the inspection control circuit;
The inspection control circuit includes:
The chip ID code extracted by the first signal extraction circuit is compared with the chip ID code from the chip ID circuit, and the circuit under test is inspected based on the comparison result.
A semiconductor inspection system characterized by that. In claim 1,
The signal generated by the first signal generator includes a redundant code for increasing the reliability of the signal,
The semiconductor integrated circuit is:
A decoding circuit for decoding the extracted signal based on a redundant code included in the signal extracted by the first signal extracting circuit;
The inspection control circuit includes:
Inspecting the circuit under measurement based on the signal decoded by the decoding circuit,
A semiconductor inspection system characterized by that. In claim 1,
The semiconductor integrated circuit is:
A second signal superimposing circuit that superimposes a signal indicating a test result obtained by the test control circuit on a power source supplied to the first power source terminal;
The inspection device includes:
A second signal extraction circuit for extracting the signal superimposed by the second signal superposition circuit;
A determination device for determining the content of the signal extracted by the second signal extraction circuit;
A semiconductor inspection system characterized by that. In claim 16,
The determination device includes:
Using the difference between the signal generated by the first signal generator and the signal extracted by the second signal extraction circuit to determine the content of the signal extracted by the second signal extraction circuit;
A semiconductor inspection system characterized by that. In claim 16,
The frequency band of the signal superimposed by the second signal superposition circuit is different from the frequency band of the signal generated by the first signal generator.
A semiconductor inspection system characterized by that. In claim 16,
The second superposition circuit includes:
Superimposing a signal interpolating the chip ID code of the semiconductor integrated circuit;
A semiconductor inspection system characterized by that. In claim 16,
The second superposition circuit includes:
Superimpose a signal interpolated with a redundant code,
A semiconductor inspection system characterized by that. In claim 6,
The inspection device includes:
A fourth probe for supplying power generated by the power supply device to the semiconductor integrated circuit;
The semiconductor integrated circuit is:
A fourth power supply terminal that receives power from the fourth probe;
The fourth power terminal is
Connected to the output of the noise removal circuit;
A semiconductor inspection system characterized by that. In claim 21,
The first power supply terminal is a terminal dedicated for inspection.
A semiconductor inspection system characterized by that. In claim 22,
The semiconductor integrated circuit is:
A malfunction prevention circuit is further provided at a stage subsequent to the first power supply terminal.
A semiconductor inspection system characterized by that. An apparatus for inspecting a semiconductor integrated circuit,
A power supply device for generating power to be supplied to the semiconductor integrated circuit;
A probe for supplying power generated by the power supply device to a power supply terminal of the semiconductor integrated circuit;
A signal generator for generating a signal for inspecting the semiconductor integrated circuit;
A signal superimposing circuit that superimposes the signal generated by the signal generator on the power source generated by the power supply device and supplies the signal to the probe.
Inspection apparatus characterized by that. In claim 24,
The semiconductor integrated circuit is:
A signal extraction circuit for extracting a signal superimposed on a power supply supplied to the power supply terminal;
An inspection control circuit for inspecting a circuit under measurement based on the signal extracted by the signal extraction circuit;
Inspection apparatus characterized by that. A power supply terminal that receives power from the probe of the inspection device;
A signal extraction circuit for extracting a signal superimposed on a power supply supplied to the power supply terminal;
An inspection control circuit for inspecting a circuit under measurement based on the signal extracted by the signal extraction circuit;
A semiconductor integrated circuit. In claim 26,
The inspection device includes:
A power supply device for generating power to be supplied to the semiconductor integrated circuit;
A probe for supplying power generated by the power supply device to the power supply terminal;
A signal generator for generating a signal for inspecting the semiconductor integrated circuit;
A signal superimposing circuit that superimposes the signal generated by the signal generator on the power source generated by the power supply device and supplies the signal to the probe.
A semiconductor integrated circuit.

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