200936006 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種交錯-重疊式多差分對佈局走線結構設計，特別是指 一種可實際運用於PCB和IC佈局中，並可大量節省材料成本且使走線訊號 更為穩定之走線結構設計者。 【先前技術】 請參閱圖1，為習用PCB單層佈局走線示意圖，由圖中可知，在習用 的PCB佈局走線大多為一單層佈線方式，假設定走線寬度(w)為2〇mii ;走 線的間距〇)為20mil。由上述設定的條件可知一對差分訊號對所佔的寬度&) 包括2w加上Ly為60mil。唯上述方式在使用時，其具有訊號完整度不佳及 佔用較大佈局空間的缺點。 由於上述佈局走線方式具有使用上的限制，故在2〇〇4年由韓國人D〇ng200936006 IX. Description of the Invention: [Technical Field] The present invention relates to an interleaved-overlapping multi-difference pair layout trace structure design, in particular to a practical application in PCB and IC layout, and can save a lot of material The cost and structure of the trace structure that makes the trace signal more stable. [Prior Art] Please refer to Figure 1, which is a schematic diagram of the single-layer layout of the conventional PCB. As can be seen from the figure, most of the conventional PCB layout traces are a single-layer wiring, and the default trace width (w) is 2〇. Mii; the spacing of the traces 〇) is 20mil. It can be seen from the above-mentioned conditions that the width of the pair of differential signal pairs &) includes 2w plus Ly is 60 mils. Only when the above method is used, it has the disadvantages of poor signal integrity and occupying a large layout space. Due to the restrictions on the use of the above layout, the Korean D〇ng was in 2〇〇4 years.
Gun Kam、Heeseok Lee 及 Joungho Kim 於 IEEE TRANSACTIONS ON ADVANCED PACKAGING提出一種交錯式多差分對（TwistedGun Kam, Heeseok Lee and Joungho Kim proposed an interleaved multi-differential pair (Twisted) in IEEE TRANSACTIONS ON ADVANCED PACKAGING
DifferentiaW^TDP)佈局法；駐錯式η分對佈局走線方式如圖2所 不’由圖中可知’該父錯式多差分對所使用的面積寬度和上述習用單層走 線的面積寬度相同，但由於交錯式多差分對為二層板佈局走線，所以在訊 號的完整性上較方式為佳；傾_較大佈局朗的缺點，仍無法有 效克服。 由此可見’上述習用技術仍有諸多缺失及不足，實非一良善之設計者， 而亟待加以改良。 5 200936006 本案發明人鑑於上述㈣技術驗生的各項缺點及不足，乃亟思加以 改良創新，趣料苦心孤記細研雜，餅成功研發細柄J種交 錯-重疊式多差分對佈局走線結構設計。 【發明内容】 本發明之目的在於提供—種交錯_重疊心差分對佈騎線結構設 ef ’係可實際於PCB和IC佈局中，除了可使走線訊號更為穩定外，更 可有效節省佈局空間，大量節省材料成本。 本發明之次-目的係在於提供—種交錯_錢式多差料佈局走線結 構設計’係具有設單、可有效提高佈局品f、結構簡單、翻範圍廣 及使用壽命長等優點。 可達成上述發明目的之—種交錯·重疊式多差分_局走線結構設 。十係改良1用多差分對佈局法，本發明與習用多差分對佈局法比較時， 本發月將可有效知省佈局空間和降低雜訊，其空間節省比率為 ❹（2«_2)/(4«·1) ’此處的„為差分對的數量；且當本發明關走線在雙層板佈 局中其佈局工間乃為最佳化。綱話說，在單位面積的巾，本發明 將可提t、最夕數量的多差分對佈局走線；由於在本發明設計方法中，其走 線重叠面積加大，將導致電容輕合量加大，導致共模雜鱗低，又因為交 錯佈局的走線因素’使得電流迴路面積可以減少，因為線性正比於電 /;〇電机迴路面積’因此當電流迴路面積減少時就能降低電磁干擾。 【實施方式】 *月參閱圖3A、圖3B及圖4B，為本發明-種交錯_重疊式多差分對佈 200936006 局走線結構設計之走雜視圖、立體視圖及電路板剖關，由圖中可知， 本發明-種父錯-重叠式多差分對佈局走線結構設計，乃應用於四層板-二層 佈線之印刷電路板上，其巾在於第—佈線層1設置有第-走線u及第二走 線U ’而在第二佈線層2則設置有第三走線U及第四走線22，且該第二 走線12與第三走線21處於不同佈線層之相對位置上（重叠），並可藉由通 道（Vm) 3使走線交錯於第—佈線層丨及帛二佈線層2間，如此的交錯-重 叠方式，將可有效達雜走線訊號穩定及㈣、佈局空間之目的。 請參關4A關4B，為習用使歧錯式多差分對佈局方式之電路板 』面圖及個本發败錯·重疊式多差分對佈局方式之電路板剖面圖，由圖 中可知， 為了比較父錯式多差分對和交錯·重疊式多差分對佈線所制的面積 寬度’設定參數條件如下：假設在佈局走線寬度⑽為_ ;走線的間距⑷ 為2〇mil的情況下’先計算交錯式多差分對的佈局面積寬度，在圖从的架 ❹ 構下，其佈局交錯式多差分對計算差分線的佈局面積宽度公式如下，豆中„ 為差錄陳量和大於等於2的正整數丨_對的佈局走線的寬度: 1« -M\ =np+(n-l)s 以T以實例购’丨·對差分·交錯式差分雌構佈線寬度為： |1-對1=1糾1奸1…60(mil).........................⑴ 田P為1_對的佈局走線的寬度是60 (mil) 2對差刀對的交錯式多差分對架構佈線寬度為： 12-f=i-i =lp+\s+\p 200936006 =2p+\s=\4Q (mil)........... 3對差分對的交錯式多差分難構伟線寬度為....(2) 13-^f| =\p+\s+\p+\s+\p =3/?+2s=220(mil)…. 由上述(1)(2)(3)即可推導出交錯式多差............. ................... 》對的饰局面積寬度公式為： ....................... Φ 树算交錯·重疊式多差分對柄_寬户，h 見度在圖4B的架構下，1佑 局交錯·重叠式多差分對計算差分線的佈局面積寬度公式為：-I n -f^l =np~(n-l)s 以下以實舰明，1職讀的聽_重紅多差分雌_線寬度為： 11 -M\ =1vv+15+1w=60 (mil)....... ⑺ 2對差分對的交錯重疊式多差分對架構佈線寬度為： 12-對I =lp七+ip =2p-li=l〇〇 (mil)........................ ⑹ 3對差分對的交錯-重疊式多差分對架構佈線寬度為： 13 ·對丨〜Ip+le+lj^+ls+lp ~ 3/>-25=14〇 (mil)..............................⑺ 由上述(5)(6)(7)可推導出交錯_重疊式多差分對的佈局面積寬度公式 I n -M\ =np+(n^s........................................⑻ 當一對差分對的佈局寬度是三倍於線寬和此線寬是等於二條走線間之 8 200936006 空間距離，公式(4)和⑻計算TDL較TODL減少面積寬度比率為： ;此處的 l_p=3s 1001^=/7/7-(/7-1)5^/^35^75+5=2/75+5=(2/7+1)5 ;此處的 1/T=3s (TDL - TODL) — (4/1 -1+2w -1 )5 _ (4w -1 + 2w -1)5 (2w - 2) TDL (4n-l)s (4n-l)xS ^4ηΛ) 故由交錯式多差分對和交錯-重疊式多差分對的佈局走線面積寬度的 關係，即可推導出交錯•重疊式多差分對較交錯式多差分對減少面積寬度比 率為： (2n-2)/(4n-l).............................................(9) 由推導出公式計算的結果，比較同樣在多層板堆疊架構下二層板佈局 走線條件下交錯式衫分對和交錯·重疊絲差分對方式岐線面積寬度。DifferentiaW^TDP) layout method; the error-preserving η-segment layout routing method is as shown in Figure 2, which is known from the figure. The area width used by the parent-missing multi-differential pair and the area width of the conventional single-layer trace. The same, but because the interleaved multi-difference pair is the layout of the two-layer board layout, the signal integrity is better than the mode; the disadvantage of the tilt_large layout is still not effectively overcome. It can be seen that there are still many shortcomings and deficiencies in the above-mentioned conventional technologies. It is not a good designer and needs to be improved. 5 200936006 In view of the shortcomings and shortcomings of the above (4) technical hygiene test, the inventor of this case is thinking and improving and innovating, and the fun is painstakingly meticulously researched, and the cake successfully developed the fine-handle J-staggered-overlapping multi-differential pair layout. Line structure design. SUMMARY OF THE INVENTION The object of the present invention is to provide an interlaced-overlapped differential differential pairing line structure ef' system which can be practically used in PCB and IC layouts, in addition to making the routing signal more stable, and saving more effectively. Layout space, a lot of material cost savings. The second objective of the present invention is to provide an interlaced-money multi-differential layout layout structure design which has the advantages of providing a single sheet, effectively improving the layout product f, simple structure, wide range of rotation and long service life. An interleaved/overlapping multi-differential_local routing structure can be achieved for the above object. The ten-system improvement 1 uses the multi-difference pair layout method. When the present invention is compared with the conventional multi-difference pair layout method, the present month can effectively save the layout space and reduce the noise, and the space saving ratio is ❹(2«_2)/ (4«·1) 'The number here is the number of differential pairs; and when the line of the invention is in the layout of the two-layer board, its layout is optimized. In the words, the unit area of the towel, this The invention will be able to provide a multi-difference pair layout trace of t, the number of eves; because in the design method of the invention, the overlap area of the trace is increased, which will lead to an increase in the light weight of the capacitor, resulting in a low common mode scale, and Because the routing factor of the staggered layout 'so that the current loop area can be reduced, because the linearity is proportional to the electric /; 〇 motor loop area', therefore, when the current loop area is reduced, the electromagnetic interference can be reduced. [Embodiment] * month see Figure 3A FIG. 3B and FIG. 4B are schematic views, a perspective view, and a circuit board section of the interleaved-overlapped multi-difference pair fabric 200936006, and the circuit board is cut off. - Overlapping multiple differential pair layout routing design The method is applied to a printed circuit board of a four-layer board-two-layer wiring, wherein the first wiring layer 1 is provided with a first-line u and a second line U', and the second wiring layer 2 is provided with a first Three traces U and a fourth trace 22, and the second trace 12 and the third trace 21 are at opposite positions (overlap) of different wiring layers, and the traces can be interleaved by the channel (Vm) 3 Between the first wiring layer and the second wiring layer 2, such an interleaving-overlapping method can effectively achieve the purpose of stabilizing the wiring signal and (4) and layout space. Please refer to 4A off 4B for misuse. The board diagram of the multi-difference pair layout mode and the cross-section of the board of the multi-differential pair layout method, as shown in the figure, in order to compare the father-missing multi-difference pair and the interleaving/overlap type The area width of the differential pair wiring is set as follows: Assume that the layout trace width (10) is _; when the trace spacing (4) is 2 〇 mil, the layout area width of the interleaved multi-difference pair is calculated first. Under the framework of the figure, the layout of the interleaved multi-difference pair calculates the difference line The area width formula is as follows, in the bean „ is the width of the difference and the width of the layout of the positive integer 丨_ pair of 2 or more: 1« -M\ =np+(nl)s The width of the differential and interleaved differential female wiring is: |1-to 1=1correction 1...60(mil)...................... ...(1) Field P is a 1_pair layout. The width of the trace is 60 (mil). The width of the interleaved multi-differential pair of 2 pairs of differential pairs is: 12-f=ii =lp+\s+\p 200936006 = 2p+\s=\4Q (mil)........... 3 pairs of differential pairs of interleaved multi-differential hard-destructed line widths are...(2) 13-^f| =\p+ \s+\p+\s+\p =3/?+2s=220(mil).... From the above (1)(2)(3), we can derive the interlaced multi-difference.......... ... ................... The formula for the area width of the decoration is: .................. ..... Φ Tree interleaving and overlapping multi-difference handles _ wide household, h visibility Under the structure of Figure 4B, the layout area width formula of the difference line is calculated as: -I n -f^l =np~(nl)s The following is the real ship Ming, the listening _ red multi-differential female _ line width of 1 job reading is: 11 -M\ =1vv+15+1w=60 (mil )....... (7) 2 pairs of differential pairs The width of the mis-overlapping multi-differential pair architecture is: 12-pair I = lp seven + ip = 2p-li = l 〇〇 (mil)................... ..... (6) 3 pairs of differential pairs of interleaved-overlapping multi-differential pair architecture wiring width: 13 · 丨 ~ Ip + le + lj ^ + ls + lp ~ 3 /> 25 = 14 〇 (mil )..............................(7) Interlace_overlapping can be derived from (5)(6)(7) above The layout area width formula of multiple differential pairs I n -M\ =np+(n^s............................... ....(8) When the layout width of a pair of differential pairs is three times the line width and this line width is equal to the distance between the two lines of the 200936006 space, the formulas (4) and (8) calculate the TDL compared to the TODL. Reduce the area width ratio as: ; l_p=3s 1001^=/7/7-(/7-1)5^/^35^75+5=2/75+5=(2/7+1) 5; here 1/T=3s (TDL - TODL) — (4/1 -1+2w -1 )5 _ (4w -1 + 2w -1)5 (2w - 2) TDL (4n-l) s (4n-l)xS ^4ηΛ) Therefore, the relationship between the layout area width of the interleaved multi-difference pair and the interleaved-overlapped multi-difference pair can be derived, and the interleaved/overlapping multi-difference pair can be derived. The ratio of the reduced area width is: (2n-2)/(4n-l)................. ............................(9) The results calculated by deriving the formula, comparing the same two layers in the multi-layer stacking architecture Interlaced shirt pairing and interlaced/overlapping silk differential pairing method 岐 line area width under layout routing conditions.
表1 TDP和T〇DP面積寬度的結果 —_Table 1 Results of TDP and T〇DP area width —_
O 由表1可知在交錯式多差分對和交錯_重#式多差分對在佈局走線面積 ^少的比率和差分對的數量成正比，也就是說當使駐分走線的數量 多時’制雜·重疊衫齡_方式佈局在面肢絲式多差分 9 200936006 對的方式減少的愈多。 以下利用關針«用差分對走線方式、交錯式多差分對走線方式和 交錯-重叠式多差分對走線方式進行比較說明。在軟體模擬時的走線設定·· 總長度都是lOOOmil、標準高電位/低電位為+25〇mv/_25〇mv。 圖5為軟體模擬㈣差分對走線方式^圖，其模擬絲如下：O It can be seen from Table 1 that the ratio of the interleaved multi-difference pair and the interleaved _heavy-type multi-difference pair in the layout trace area is proportional to the number of differential pairs, that is, when the number of the standing traces is large 'Mixed and overlapped shirt age _ way layout in the face of the limb type multi-differential 9 200936006 The more ways to reduce the number. The following is a comparison of the use of the differential needle routing method, the interleaved multi-differential pair routing method, and the interleaved-overlapping multi-differential pair routing method. The trace setting during software simulation·· The total length is lOOOmil, and the standard high/low potential is +25〇mv/_25〇mv. Figure 5 is a software simulation (four) differential pair routing mode ^ map, the analog wire is as follows:
ΟΟ
Q 眼圖分析是利用把一串位元序列資料中各個位元相互重疊在同一張圖 上’所以可在單張圖上檢視所有的訊號的狀況，判定訊號失真的情況。當 張眼圖的眼睛越大時，表示失真的狀況越少，相反而言張眼圖的眼睛越小 時，就表示訊號失真的狀況越多。眼圖除了開眼大小外還有振鈴現象、通 延遲時間大小和過衝/下衝（〇versh〇t/Undershoot)的影響都會有影響。振於 愈大表示訊號波形變形愈嚴重。通延遲時間愈大，也表示上升沿和下降沿 太緩、一致性太差、訊號波形的高電位也不夠，傳輸線訊號質量是會非常 差的。 200936006 態 •就是一個訊號在轉 夺相對其理想上時間的偏移量。抖動值愈大表示訊號的抖動愈嚴重、通 道（料卩精大。由表四_2可知交錯_重疊式多差分對的抖動量最小。 振鈴（Ringing )的產生是訊號在轉態時電壓過，下衝現象 (OvershGt/UndershGot)的f彡響，另外傳魏上傳送的城纽抗不連續點 會發生信號反射，進而產生振鈴現象，因此當振铃現象愈大表示訊號變形 φ愈嚴重。由圖6之類結果可知交錯·重疊式多差分對的振鈐現象最小。 眼高和眼寬的大何以知觀醜_大小；愈大，絲失真的狀況 越由® 6之模擬結果可知交錯·重疊式多差分對騎高，雖然小於傳統 方式i_疋傳統方式的電財過衝和下衝的現象。交錯重叠式多差分對的 眼寬是最大的。因此可知麵_大小比錢式多差分獻；也就是訊號 失真較少。 本發月所提供之種交錯_重疊式多差分對佈局走線結構設計，與其他 ©習職術相互比較時，更具有下列之優點： 本發月之種交錯.重登式多差分對佈局走線結翻:計，係可實際 運用於PCB和1C佈局中，可使走線訊號更為穩定。 本發月之種父錯-重疊式多差分對佈局走線結構設計，係可實際 運用於PCB和1C佈局中，可有效節省佈局空間，大量節省材料成 本。 3.本發明之—種交錯·耗式多差分對佈局走線結構設計，係具有設 。十簡單可有效提局佈局品質、結構簡單、適用範圍廣及使用壽命 11 200936006 長等優點。 上列詳細說明係針對本發明之一可行實施例之具體說明，惟該實施例 並非用以_本發明之專纖圍，絲雌本發職髓神縣之等效實 施或變更，均應包含於本案之專利範圍中^ 综上所述，本案不但在技術思想上確屬創新，並能較習用物品增進上 述多項功效’應以充分符合新穎性及進步性之法定發明專利要件，麦依法 〇提出申請，懇請貴局核准本件發明專利申請案，以勵發明，域德便。 【圖式簡單說明】 圖1為習用印刷電路板（PCB)單層佈局走、線示意圖； 圖2為習用交錯式多差分對佈局法之佈局示意圖； 圖3A為本發明-種交錯重疊式多差分對佈局走線結構設計之走線俯 視圖； 圖3B為該-種交錯-重疊式多差分對佈局走線結構設計之走線立趙捉 % 圖; 圖4A為習用使用交錯式多差分對佈局方式之電路板剖面圖； 圖犯為使用本發明交錯-重叠式多差分對佈局方式之電路板剖面圖； 圖5為軟體模擬習用差分對走線方式之眼圖； 圖6為軟體模擬交錯式多差分對走線方式之眼圖； 圖7為軟體模擬交錯-重疊式多差分對差分對走線方式之眼圖。 【主要元件符號說明】 1第一佈線層 12 200936006 11第·一走線 12第二走線 2第二佈線層 21第三走線 22第四走線 3通道The Q eye diagram analysis uses the fact that each bit in a series of bit sequence data is superimposed on the same picture. Therefore, it is possible to view all the signals on a single picture and determine the distortion of the signal. When the eye of the eye is larger, the less the distortion is indicated. On the contrary, the smaller the eye of the eye, the more the signal is distorted. In addition to the size of the eye, the eye diagram has the effects of ringing, delay time and overshoot/undershoot (〇versh〇t/Undershoot). The greater the vibration, the more severe the waveform distortion. The greater the delay time, the longer the rising edge and the falling edge are too slow, the consistency is too poor, the high potential of the signal waveform is not enough, and the signal quality of the transmission line is very poor. 200936006 State • It is the offset of a signal in relation to its ideal time. The larger the jitter value, the more severe the jitter of the signal and the larger the channel. The jitter of the interleaved _ overlapped multi-differential pair is the smallest. The ringing (Ringing) is generated when the signal is in the transition state. The undershoot phenomenon (OvershGt/UndershGot) f 彡 , 另外 Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over Over It can be seen from the results of Fig. 6 that the vibrating phenomenon of the interleaved/overlapping multi-difference pair is the smallest. The height of the eye and the width of the eye are so large that the size of the eye is _ _ size; the larger the wire distortion is, the more the simulation results of the -6 are interleaved. · Overlapped multi-difference pair ride height, although smaller than the traditional way of i_疋 traditional mode of power overshoot and undershoot. The interleaved overlap type multi-difference pair has the largest eye width. Therefore, it is known that the size is larger than the money type. Multi-differential contribution; that is, less signal distortion. The interleaved-overlapping multi-difference pair layout routing structure provided by this month has the following advantages when compared with other ©-apprentices: Kind of The re-entry multi-differential pair layout traces: the meter can be practically used in the PCB and 1C layout to make the trace signal more stable. This month's parent-fault-overlap multiple differential pair layout The line structure design can be practically used in PCB and 1C layout, which can effectively save layout space and save a lot of material cost. 3. The invention has a staggered and consumable multi-difference pair layout routing structure design. Ten simple can effectively improve the layout quality, simple structure, wide application range and longevity 11 200936006. The above detailed description is specific to one of the possible embodiments of the present invention, but the embodiment is not used for The invention shall be included in the patent scope of this case. In summary, the case is not only innovative in terms of technical thinking, but also more customary. Articles to enhance the above-mentioned multiple functions 'should be in accordance with the statutory invention patents that fully meet the novelty and progressiveness. Mai applied for an application for the invention, and urged you to approve the application for the invention patent to encourage invention and domain. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a single-layer layout of a conventional printed circuit board (PCB); FIG. 2 is a schematic diagram of a layout of a conventional interleaved multiple differential pair layout method; FIG. 3A is a cross-over overlap type of the present invention. Figure 3B shows the trace of the cross-over-overlap multi-difference pair layout structure design. Figure 4A shows the layout of the interleaved multi-differential pair. The circuit board sectional view of the mode; the figure is a circuit board sectional view using the staggered-overlapped multiple differential pair layout mode of the present invention; FIG. 5 is an eye diagram of the software simulation conventional differential pair routing mode; Eye diagram of multi-differential pair routing mode; Figure 7 is an eye diagram of software analog interleaving-overlap multiple differential pair differential pair routing mode. [Main component symbol description] 1 first wiring layer 12 200936006 11 first one 12 second trace 2 second wiring layer 21 third trace 22 fourth trace 3 channel