TWI898767B - Design method for the layout of output capacitors in a switch-mode power supply with constant current output - Google Patents

Abstract

This invention relates to a design method for the layout of output capacitors in a switch-mode power supply with constant current output. The primary approach involves arranging the capacitors in the circuit loop with a spacing of 5mm on the traces. This arrangement enhances the charge transfer rate within the circuit loop, ensuring that the rate is not affected by frequency variations and reducing noise during constant current output. This design increases the practical efficiency and effectiveness of the overall implementation.

Description

Output Capacitor Layout Design Method for Constant Current Output in Switching Power Supplies

This invention relates to a design method for output capacitor layouts used in switching power supplies with constant current output. Specifically, the design improves the charge transfer rate within the circuit loop, making it independent of frequency variations and reducing noise during constant current output, thereby enhancing overall practicality and performance.

Traditional switching power supplies typically utilize coupled capacitors for output filtering. Common practice involves arranging capacitors based on their value, from largest to smallest, according to the direction of input and output current. This approach typically employs a dense arrangement of capacitors. While this approach achieves filtering effects, it cannot effectively filter out resonant frequencies generated along the path. Currently, most applications that require constant current output are related to LED or motor driving. Both applications require stable voltage and current. Therefore, noise suppression must be within the specified range of the application to ensure stable operation of the LED or motor. In a switching power supply architecture with constant current output, the coupling capacitor at the output end will be affected by the current brought by the output path. The essence of current is the movement of charge, and The magnitude of the current is related to the amount and rate of charge movement. According to the equation I = Q/t [Q = charge, t = time], frequency fluctuations in the output path [t = 1/f] affect the rate of charge movement. Frequency instability in the output loop causes the output coupling capacitor to become instantaneously saturated. This frequency fluctuation also causes the coupling capacitor's capacitance to vary, causing noise in the output current signal.

Frequency instability in the output loop causes changes in charge flow rate, which is closely related to the width and length of the layout traces. This parasitic inductance generated by the PCB traces can affect noise, preventing it from being completely suppressed by capacitors. Longer traces tend to generate higher frequencies, necessitating the placement of a larger number of coupling capacitors for filtering. However, placing too many coupling capacitors increases the frequency and noise in the loop. When the loop frequency (loop frequency is related to the power switching frequency) increases, the output capacitor size will be reduced. When the output current increases, the trace width will also increase, and the parasitic parameters will also change accordingly, making the output filtering design more difficult.

Please refer to the schematic diagram of the parasitic inductance generated by the existing circuit board in Figure 24. Generally, the power conversion circuit on the overall circuit system (2) is called VRM [Voltage Regulator Module, voltage regulation module] (21). The output voltage from the VRM (21) is supplied to the load (22) [such as LED or motor] through the trace [trace] (231) on the circuit board (23) as a conductive path. The trace (231) is usually made of a thin copper wire, copper foil or other conductive materials. The trace (231) has impedance and frequency, thereby generating parasitic inductance (2 32), so that the capacitor (24) is added to perform filtering; generally, the parameters and selection of the capacitor (24) used in the loop filtering can effectively suppress the noise generated by other passive components in the circuit system (2), but different noises will be generated in the loop due to the frequency variation of the trace (231) of the circuit board (23), and high-frequency noise will be generated in the loop, which cannot be effectively suppressed even if the capacitor (24) is added.

When the line (231) between the VRM (21) and the load (22) of the circuit system (2) is longer, the parasitic inductance (232) and impedance will be relatively large. On the contrary, when the line (231) is shorter, the parasitic inductance (232) will be relatively small. Regardless of whether the line (231) is long or short, it will produce resonance. To reduce the resonance phenomenon in the loop, the target is first set. The target impedance in the loop is mainly related to the characteristics of the capacitor selected in the loop. The capacitor parameters selected according to the target impedance are introduced into the trace (231) between the VRM (21) and the load (22). Basically, most of the noise generated by the passive components can be filtered out. The remaining noise is caused by the noise (resonance) generated by the capacitor (24) filtering and the plane of the circuit board (23).

With this in mind, the inventors, drawing on years of extensive design, development, and manufacturing experience in the relevant industry, have further researched and improved existing structures and shortcomings, providing a method for designing output capacitor layouts for constant-current output switching power supplies, aiming to achieve greater practical value.

The primary objective of this invention is to provide a method for designing an output capacitor layout for a constant-current switching power supply. This method improves the charge transfer rate within the circuit loop, making it independent of frequency variations and reducing noise during constant-current output. Overall, this method enhances practical performance.

The primary purpose and effectiveness of the present invention's output capacitor layout design method for a switching power supply with a constant current output are achieved through the following specific technical means:

This is mainly done by arranging capacitors on the traces in the circuit loop with a spacing of 5mm.

The present invention is applied to a preferred embodiment of a method for designing an output capacitor layout for a switching power supply with a constant current output, wherein the output current in the circuit loop is 1A and the trace width is 1mm.

The present invention is applied to a preferred embodiment of a method for designing an output capacitor layout for a switching power supply with a constant current output, wherein the output current in the circuit loop is 5A and the trace width is 5mm.

The present invention is applied to a preferred embodiment of a method for designing an output capacitor layout for a switching power supply with a constant current output, wherein the trace in the circuit loop is arranged between a voltage regulator module (VRM) and a load.

The present invention is applied to a preferred embodiment of a method for designing an output capacitor layout for a switching power supply with a constant current output, wherein the load is either an LED or a motor.

To provide a more complete and clear disclosure of the technical content, purpose of the invention, and the effects achieved by the present invention, the following is a detailed description thereof, and please refer to the accompanying drawings and figure numbers:

First, please refer to the first figure of the invention, which shows the state of the transverse electromagnetic wave generated in the trace, and the second figure, which shows the state of the equivalent circuit RL impedance characteristic of the invention, as shown in FIG. Since there is a certain voltage in the circuit loop (1), an electric field (12) is generated on the trace (11), and the energy transfer direction in the circuit loop (1) is the same as the magnetic field (13) and is perpendicular to the electric field (12). When the The greater the energy of the electric field (12) in the trace (11), the more resonances of varying magnitudes will be generated in the loop. The more resonances occur, the more noise or signal instability will be generated in the output signal. When the resonance frequency is higher, the trace may generate impedance and a voltage drop may be generated at the output. This resonance phenomenon can be calculated using Maxwell's equations. The transverse electric wave (14) [Transverse Electric, TE Mode] generated in the trace (11) can be written as TE _mn according to the amplitude change of the electromagnetic field in the cross section in the waveguide, where m and n represent the number of fluctuations in the field strength along a certain coordinate dimension.

In the simulation experiment, 1mm and 5mm capacitor spacing arrangements were used for resonance simulation. The resonance state of each spacing arrangement when applied to the traces flowing through 1A and 5A copper foils with widths of 1mm and 5mm was analyzed one by one:

When the capacitor spacing is 1mm, 5mm, and the trace current and width is 1A@1mm, please also refer to the third figure, which is the waveform diagram of the resonance mode test at a current of 1A and a capacitor spacing of 1mm [584KHz], the fourth figure, which is the waveform diagram of the resonance mode test at a current of 1A and a capacitor spacing of 1mm [731KHz], the fifth figure, which is the waveform diagram of the resonance mode test at a current of 1A and a capacitor spacing of 1mm [1.16MHz], and the sixth figure, which is the waveform diagram of the resonance mode test at a current of 1A and a capacitor spacing of As shown in the waveform diagram of the resonance mode test at 1mm [2.74MHz], and the waveform diagram of the resonance mode test at 1A current and 1mm capacitor spacing [3.84GHz] of the present invention in the seventh figure, in the resonance simulation test results, the simulation software extracted five resonance frequencies and displayed the resonance positions respectively. The resonance frequencies occurred at 584KHz, 731KHz, 1.16MHz, 2.74MHz, and 3.84GHz respectively. Generally speaking, the resonance in the loop is recommended to fall on TE The results show that TE ₀₁ or _{TE 10 are} 584 _kHz , 731 kHz, 1.16 MHz, and 2.74 MHz, respectively. At 3.84 GHz, two resonance positions (TE ₂₀ ) are simultaneously generated. Because these two resonance points occur at high frequencies, they are not very effective in filtering high-frequency noise.

Please also refer to Figure 8, which is a waveform diagram of the resonance mode test at a current of 1A and a capacitor spacing of 5mm [440KHz], Figure 9, which is a waveform diagram of the resonance mode test at a current of 1A and a capacitor spacing of 5mm [558KHz], Figure 10, which is a waveform diagram of the resonance mode test at a current of 1A and a capacitor spacing of 5mm [866KHz], Figure 11, which is a waveform diagram of the resonance mode test at a current of 1A, As shown in the waveform diagram [2.03MHz] of the resonant mode test with a capacitor spacing of 5mm, and the waveform diagram [3.67GHz] of the resonant mode test with a current of 1A and a capacitor spacing of 5mm in Figure 12, when the capacitor spacing is changed to 5mm, the resonant frequency is significantly reduced. The high-frequency resonant frequency is reduced from the original 3.84GHz to 3.67GHz, and the resonance point is reduced from the original TE ₂₀ to TE ₁₀ , which is a clear improvement.

When the capacitor spacing is 1mm or 5mm, and the trace current and width are 5A@5mm, please also refer to Figure 13, which shows the waveform of the resonance mode test at 5A and 1mm capacitor spacing [661KHz], Figure 14, which shows the waveform of the resonance mode test at 5A and 1mm capacitor spacing [784KHz], Figure 15, which shows the waveform of the resonance mode test at 5A and 1mm capacitor spacing [1.2MHz], and Figure 16, which shows the waveform of the resonance mode test at 5A and 1mm capacitor spacing [1.2MHz]. The test waveform [2.98MHz] and Figure 17 show the waveform [2.96GHz] of the present invention tested in resonant mode with a current of 5A and a capacitor spacing of 1mm. Because the loop needs to withstand a current of 5A, the trace width is changed to 5mm, and the capacitor spacing is initially set at 1mm for resonance simulation. The simulation results generate five resonant frequencies: 661kHz, 784kHz, 1.2MHz, 2.98MHz, and 2.96GHz. At 2.96GHz, two resonance points (TE ₂₀ ) are simultaneously generated. Because these two resonance points occur at high frequencies, they are not very effective in filtering high-frequency noise.

Please also refer to Figure 18, which shows the waveform of the present invention under the resonant mode test with a current of 5A and a capacitor spacing of 5mm [628KHz], Figure 19, which shows the waveform of the present invention under the resonant mode test with a current of 5A and a capacitor spacing of 5mm [970KHz], Figure 20, which shows the waveform of the present invention under the resonant mode test with a current of 5A and a capacitor spacing of 5mm [2.4MHz], and Figure 21. As shown in the waveform diagram [1.93GHz] of the resonance mode test conducted with a current of 5A and a capacitor spacing of 5mm, the present invention adopts a 5mm arrangement for the resonance simulation. The simulation shows a significant frequency reduction, with only four large resonant frequencies generated. The high-frequency resonant frequency decreases from 2.96GHz to 1.93GHz, and the TE is also reduced from ₂₀ to _10. This also indicates that this spacing arrangement is also suitable for filtering traces with larger areas.

Therefore, according to the above simulation results, it can be known that, please refer to the output capacitor layout design structure schematic diagram of the present invention in Figure 22 [output current 1A, trace width 1mm] and the output capacitor layout design structure schematic diagram of the present invention in Figure 23 [output current 5A, trace width 5mm]. As shown in the circuit loop (1), when the trace (11) is set between the voltage regulator module [Voltage Regulator Module, VRM] and the load [such as: LED or motor], the capacitor (15) is arranged on the trace (11) with an arrangement spacing of 5mm. The filtering effect is better and the generation of high-frequency oscillation can also be effectively reduced.

From the above description of the use and implementation of the present invention, it can be seen that compared with the existing technical means, the present invention mainly has the following advantages:

1. The present invention can improve the rate of charge transfer in a circuit loop, making the charge transfer rate unaffected by frequency variations, and further enhances the practical performance characteristics of its overall implementation.

2. Currently, most applications requiring constant current output are related to LED or motor driving. Both applications require stable voltage and current. Therefore, noise suppression must comply with the application's specified range to ensure stable operation of the LED or motor. This invention can also reduce noise during constant current output, allowing the LED or motor to operate stably.

However, the aforementioned embodiments or drawings do not limit the product structure or usage of the present invention. Any appropriate changes or modifications by those skilled in the art should be considered as falling within the patent scope of the present invention.

In summary, the embodiments of this invention can indeed achieve the intended effects. Moreover, the specific structure disclosed therein is not only unprecedented in similar products, but has also not been disclosed prior to the filing of this application. Therefore, this invention fully complies with the provisions and requirements of the Patent Law. Therefore, we hereby file an application for an invention patent in accordance with the law and earnestly request your review and the granting of the patent. We would be grateful for your kindness.

1: Circuit loop 11: Trace 12: Electric field 13: Magnetic field 14: Transverse electromagnetic wave 15: Capacitor 2: Circuit system 21: VRM 22: Load 23: Circuit board 231: Trace 232: Parasitic inductance 24: Capacitor

Figure 1: Schematic diagram of the present invention generating transverse electromagnetic waves in traces Figure 2: Schematic diagram of the equivalent circuit RL impedance characteristics of the present invention generating transverse electromagnetic waves in traces Figure 3: Waveform diagram of the present invention tested in resonant mode with a current of 1A and a capacitor spacing of 1mm [584kHz] Figure 4: Waveform diagram of the present invention tested in resonant mode with a current of 1A and a capacitor spacing of 1mm [731kHz] Figure 5: Waveform diagram of the present invention tested in resonant mode with a current of 1A and a capacitor spacing of 1mm [1.16MHz] Figure 6: Waveform diagram of the present invention tested in resonant mode with a current of 1A and a capacitor spacing of 1mm [2.74MHz] Figure 7: Waveform diagram of the present invention tested in resonant mode with a current of 1A and a capacitor spacing of 1mm [3.84GHz] Figure 8: Waveform diagram of the present invention under resonant mode testing at a current of 1A and a capacitor spacing of 5mm [440KHz] Figure 9: Waveform diagram of the present invention under resonant mode testing at a current of 1A and a capacitor spacing of 5mm [558KHz] Figure 10: Waveform diagram of the present invention under resonant mode testing at a current of 1A and a capacitor spacing of 5mm [866KHz] Figure 11: Waveform diagram of the present invention under resonant mode testing at a current of 1A and a capacitor spacing of 5mm [2.03MHz] Figure 12: Waveform diagram of the present invention under resonant mode testing at a current of 1A and a capacitor spacing of 5mm [3.67GHz] Figure 13: Waveform diagram of the present invention under resonant mode testing at a current of 5A and a capacitor spacing of 1mm [661KHz] Figure 14: Waveform diagram of the present invention under resonant mode testing at a current of 5A and a capacitor spacing of 1mm [784KHz] Figure 15: Waveform diagram of the present invention under resonant mode testing at a current of 5A and a capacitor spacing of 1mm [1.2MHz] Figure 16: Waveform diagram of the present invention under resonant mode testing at a current of 5A and a capacitor spacing of 1mm [2.98MHz] Figure 17: Waveform diagram of the present invention under resonant mode testing at a current of 5A and a capacitor spacing of 1mm [2.96GHz] Figure 18: Waveform diagram of the present invention under resonant mode testing at a current of 5A and a capacitor spacing of 5mm [628KHz] Figure 19: Waveform diagram of the present invention under resonant mode testing at a current of 5A and a capacitor spacing of 5mm [970KHz] Figure 20: Waveform diagram of the present invention tested in resonant mode at 5A current and 5mm capacitor spacing [2.4MHz] Figure 21: Waveform diagram of the present invention tested in resonant mode at 5A current and 5mm capacitor spacing [1.93GHz] Figure 22: Schematic diagram of the output capacitor layout design structure of the present invention [output current 1A, trace width 1mm] Figure 23: Schematic diagram of the output capacitor layout design structure of the present invention [output current 5A, trace width 5mm] Figure 24: Schematic diagram of parasitic inductance generated in conventional circuit boards

1: Circuit loop

11: Routing

15: Capacitor

Claims (4)

A method for designing output capacitors for constant-current switching power supplies employs a circuit loop with a trace between the voltage regulator module (VRM) and the load, with capacitors arranged on this trace with a 5mm spacing. As described in claim 1, an output capacitor layout design method is applied to a switching power supply with a constant current output, wherein in the circuit loop, the output current is 1A and the trace width is 1mm. As described in claim 1, an output capacitor layout design method is applied to a switching power supply with a constant current output, wherein in the circuit loop, the output current is 5A and the trace width is 5mm. The output capacitor layout design method for a switching power supply with a constant current output as described in claim 1, wherein the load is either an LED or a motor.