CN108962839A - Packaging structure - Google Patents
Packaging structure Download PDFInfo
- Publication number
- CN108962839A CN108962839A CN201710384186.9A CN201710384186A CN108962839A CN 108962839 A CN108962839 A CN 108962839A CN 201710384186 A CN201710384186 A CN 201710384186A CN 108962839 A CN108962839 A CN 108962839A
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- Prior art keywords
- layer
- encapsulating structure
- patterned conductive
- structure according
- core structural
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention provides a packaging structure, which comprises a metal substrate, a core structure layer and a packaging element. The core structure layer is configured on the metal substrate and is provided with an opening and a patterned conductive layer. The packaging element is configured on the metal substrate and is positioned in the opening of the core structure layer. The packaging element comprises a plurality of outer pins, and the outer pins are electrically connected with the patterned conductive layer of the core structure layer. The outer surface of each outer pin is cut to be flush with the upper surface of the patterned conductive layer.
Description
Technical field
The present invention relates to a kind of encapsulating structures, more particularly to a kind of encapsulating structure that interior can bury potted element.
Background technique
When considering the integral thickness of electronic device or encapsulating structure, then need to inquire into the structure dress mode of embedded element.It is logical
Interior the burying for crossing element, can be such that encapsulation volume significantly reduces, more high functionality elements can be put into, to increase substrate surface
Layout area, to achieve the purpose that electronic product is thinned.In general, in the existing encapsulation technology using built-in type element
In, it needs first to form an accommodation groove on substrate, by element configuration in the accommodation groove of substrate.And then it is filled insulation
The step of colloid, so as to be embedded in substrate in element.However, embedded element often faces the problem of poor heat radiation, in turn
Influence the heat dissipation performance of electronic device or encapsulating structure entirety.
Summary of the invention
The present invention provides a kind of encapsulating structure, interior can bury potted element, has effects that reduce packaging height.
A kind of encapsulating structure of the invention, including metal substrate, core structural layer and potted element.Core structural layer configuration
In on metal substrate, and there is opening and patterned conductive layer, potted element to be configured on metal substrate, and is located at core knot
In the opening of structure layer.Wherein potted element includes multiple outer pins, and the patterned conductive layer of outer pin and core structural layer is electric
Property connection, and the outer surface of each outer pin is trimmed in the upper surface of patterned conductive layer.
In one embodiment of this invention, above-mentioned metal substrate has configuration surface and groove, core structural layer configuration
In on configuration surface, and potted element is configured in groove, and the bottom surface of configuration surface and groove has difference in height.
In one embodiment of this invention, the bottom surface of above-mentioned groove is rough surface.
In one embodiment of this invention, above-mentioned metal substrate has configuration surface, and core structural layer and encapsulation are first
Part is configured on configuration surface.
In one embodiment of this invention, above-mentioned core structural layer includes dielectric layer, and dielectric layer is located at pattern conductive
Between layer and metal substrate.
In one embodiment of this invention, above-mentioned potted element further includes chip, packing colloid.Chip has multiple connect
Pad.Packing colloid coating chip and the surface for exposing each connection pad, wherein outer pin is configured on packing colloid and distinguishes
It is connected to the surface of each connection pad.
In one embodiment of this invention, above-mentioned potted element further includes chip carrier, chip, packing colloid and a plurality of
Conducting wire.Chip is configured on chip carrier.Packing colloid coating chip and chip carrier, wherein outer pin is configured on packing colloid,
And conducting wire is electrically connected between chip and outer pin.
In one embodiment of this invention, the pattern conductive that above-mentioned outer pin passes through a plurality of conducting wire and core structural layer
Layer is electrically connected.
In one embodiment of this invention, above-mentioned external pin structure and it is electrically connected to the patterning of core structural layer
Conductive layer.
In one embodiment of this invention, above-mentioned encapsulating structure further includes insulating layer, is filled in potted element and core
Between the opening of structure sheaf.
In one embodiment of this invention, above-mentioned encapsulating structure further includes adhesion layer, is configured at core structural layer and gold
Belong between substrate.
In one embodiment of this invention, above-mentioned encapsulating structure further includes heat-conducting glue layer, is configured at potted element and gold
Belong between substrate.
In one embodiment of this invention, above-mentioned encapsulating structure further includes surface-treated layer, is configured at pattern conductive
On the upper surface of layer and on the outer surface of each outer pin.
In one embodiment of this invention, above-mentioned encapsulating structure further includes soldermask layer, is configured at core structural layer, and extremely
The outer pin of few overlay pattern conductive layer and potted element.
In one embodiment of this invention, above-mentioned encapsulating structure further includes electronic component and multiple conductive through holes.Electronics
Element configuration is on soldermask layer.Conductive through hole runs through soldermask layer and expose portion patterned conductive layer, and wherein electronic component passes through
Multiple conductive through holes and be electrically connected patterned conductive layer.
In one embodiment of this invention, above-mentioned encapsulating structure further includes soldermask layer and surface-treated layer.Soldermask layer
It is configured at core structural layer, and overlay pattern conductive layer, wherein soldermask layer exposes the portion of upper surface of patterned conductive layer.
Surface-treated layer is configured at the outer surface on the upper surface for the patterned conductive layer that soldermask layer is exposed with each outer pin
On.
Based on above-mentioned, in the configuration of encapsulating structure of the invention, potted element is disposed on metal substrate and is located at
In the opening of core structural layer.In this way, potted element is in interior embedment core structural layer, and the outer pin of potted element with
The patterned conductive layer of core structural layer can reduce the overall packaging height of encapsulating structure in coplanar whereby.In addition, encapsulation member
Part is arranged on metal substrate, and the radiating efficiency of potted element can be promoted by the thermal conductive property of metal substrate.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is shown as a kind of diagrammatic cross-section of encapsulating structure of one embodiment of the invention；
Fig. 2 is shown as a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention；
Fig. 3 is shown as a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention；
Fig. 4 is shown as a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention；
Fig. 5 is shown as a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention；
Fig. 6 is shown as a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention；
Fig. 7 is shown as a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention；
Fig. 8 is shown as a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention.
Description of symbols:
100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H: encapsulating structure
110,110c, 110d: metal substrate
112: configuration surface
114c, 114d: groove
115c, 115d: bottom surface
120: core structural layer
122: opening
124: patterned conductive layer
126: dielectric layer
130,230: potted element
231: chip carrier
132,232: outer pin
134,234: chip
1342: connection pad
136,236: packing colloid
238: conducting wire
140: insulating layer
150: adhesion layer
160: heat-conducting glue layer
170,170 ': surface-treated layer
180,180 ': soldermask layer
190: electronic component
190A: conductive through hole
W: conducting wire
H: difference in height
S1, S1 ': outer surface
S2: upper surface
S3: surface
G: the air gap
Specific embodiment
Fig. 1 is shown as a kind of diagrammatic cross-section of encapsulating structure of one embodiment of the invention.Referring to FIG. 1, this implementation
The encapsulating structure 100A of example comprising metal substrate 110, core structural layer 120 and potted element 130.Core structural layer 120 is matched
It is placed on metal substrate 110, and there is opening 122 and patterned conductive layer 124.Potted element 130 is configured at metal substrate
On 110 and it is located in the opening 122 of core structural layer 110.Potted element 130 includes multiple outer pins 132, and draws outside each
Foot 132 is electrically connected to the patterned conductive layer 124 of core structural layer 120.In particular, the outer surface of each outer pin 132
S1 trims the upper surface S2 in patterned conductive layer 124.
Specifically, the metal substrate 110 of the present embodiment has configuration surface 112, and core structural layer 120 and encapsulation member
Part 130 is respectively arranged on configuration surface 112.There is the air gap G between potted element 130 and core structural layer 120, imply that
Potted element 130 does not contact the inner wall of the opening 122 of core structural layer 120.Core structural layer 120 further includes dielectric layer 126,
Dielectric layer 126 is between patterned conductive layer 124 and metal substrate 110.Potted element 130 further includes chip 134, encapsulation
Colloid 136, wherein chip 134 has multiple connection pads 1342, and 136 coating chip 134 of packing colloid and exposes each and connect
The surface S3 of pad 1342.Each outer pin 132 is configured on packing colloid 136, and structural respectively and be electrically connected to every
The surface S3 of one connection pad 1342, so that chip 134 can be electrically connected to the figure of core structural layer 120 by outer pin 132
Case conductive layer 124.As shown in Figure 1, the potted element 130 of the present embodiment is embodied as the potted element of flip kenel, and seal
The outer pin 132 for filling element 130 is patterned conductive layer 124 that is structural and being electrically connected to core structural layer 120.
It refer again to Fig. 1, in order to further fix the position of potted element 130, the encapsulating structure 100A of the present embodiment can
Including insulating layer 140, wherein insulating layer 140 is filled in the sky between potted element 130 and the opening 122 of core structural layer 120
In gas clearance G, potted element 130 is positioned in opening 122.Furthermore the encapsulating structure 100A of the present embodiment can further include
Adhesion layer 150, wherein adhesion layer 150 is configured between core structural layer 120 and metal substrate 110, and core structural layer 120 is logical
It crosses adhesion layer 150 and sticks together and be fixed on metal substrate 110.In addition, in order to increase the heat dissipation effect of potted element 130, this
The encapsulating structure 100A of embodiment also further includes heat-conducting glue layer 160, and wherein heat-conducting glue layer 160 is configured at potted element 130 and gold
Belong between substrate 110, and potted element 130 can be sticked together by heat-conducting glue layer 160 and is fixed on metal substrate 110, and be sealed
Generated heat sequentially rapidly can be transferred to the external world by heat-conducting glue layer 160 and metal substrate 110 by dress element 130.
In short, potted element 130 is disposed on metal substrate 110 in the configuration of the present embodiment encapsulating structure 100A
In upper and opening 122 positioned at core structural layer 120.In this way, potted element 130 is in interior embedment core structural layer 120,
And the patterned conductive layer 124 of the outer pin 132 of potted element 130 and core structural layer 120 can reduce envelope in coplanar whereby
The overall packaging height of assembling structure 100A.In addition, potted element 130 is arranged on metal substrate 110, metal substrate can be passed through
110 thermal conductive property promotes the radiating efficiency of potted element 130.
It should be noted that, following embodiments continue to use the element numbers and partial content of previous embodiment, wherein adopting herein
Be denoted by the same reference numerals identical or approximate element, and the explanation of same technique content is omitted.About clipped
Explanation can refer to previous embodiment, following embodiment will not be repeated herein.
Fig. 2 is shown as a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention.Please also refer to Fig. 1 with
Fig. 2, the encapsulating structure 100A of encapsulating structure 100B and Fig. 1 of the present embodiment are similar, and the difference of the two is: the envelope of the present embodiment
Dress element 230 is embodied as the potted element of routing kenel.Specifically, the potted element 230 of the present embodiment includes chip carrier
231, outer pin 232, chip 234, packing colloid 236 and a plurality of conducting wire 238.Chip 234 is configured on chip carrier 231, and
Conducting wire 238 is electrically connected between chip 234 and outer pin 232, and 236 coating chip 234 of packing colloid, chip carrier 231 with
It conducting wire 238 and is filled between outer pin 232.Outer pin 232 is configured on packing colloid 236, and each outer pin 232
Outer surface S1 ' trims the upper surface S2 in patterned conductive layer 124.
Fig. 3 is shown as a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention.Please also refer to Fig. 1 with
Fig. 3, the encapsulating structure 100A of encapsulating structure 100C and Fig. 1 of the present embodiment are similar, and the difference of the two is: the gold of the present embodiment
Belonging to substrate 110c also has groove 114c, and wherein potted element 130 is configured in groove 114c, and configuration surface 112 and groove
The bottom surface 115c of 114c has height difference H.Specifically, the groove 114c of metal substrate 110c can be used for accommodating thickness biggish
Potted element 130 makes potted element 130 that can reach outer pin 132 by the interior opening 122 for being embedded in core structural layer 120
Outer surface S1 trims the upper surface S2 in patterned conductive layer 124, to reduce the purpose of overall packaging height.
Fig. 4 is shown as a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention.Please also refer to Fig. 3 with
Fig. 4, the encapsulating structure 100C of encapsulating structure 100D and Fig. 3 of the present embodiment are similar, and the difference of the two is: the gold of the present embodiment
The bottom surface 115d for belonging to the groove 114d of substrate 110d is embodied as rough surface, and wherein rough surface shape is, for example, rectangular saw-tooth shape
Structure, but the present invention is not limited according to this.The bottom surface 115d of the groove 114d of the metal substrate 110d of the present embodiment can increase absolutely
Contact area between edge layer 140 and heat-conducting glue layer 160 and metal substrate 110d, to increase the combination between metal substrate 110d
Power can promote the bond strength between insulating layer 140, heat-conducting glue layer 160 and metal substrate 110d whereby.
Fig. 5 is shown as a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention.Please also refer to Fig. 1 with
Fig. 5, the encapsulating structure 100A of encapsulating structure 100E and Fig. 1 of the present embodiment are similar, and the difference of the two is: the envelope of the present embodiment
Assembling structure 100E further includes surface-treated layer 170, is configured on the upper surface S2 of patterned conductive layer 124 and outer pin 132
On the S1 of outer surface, wherein surface-treated layer 170 is, for example, nickel layer, layer gold, silver layer, NiPdAu layer or other metals appropriate or conjunction
Gold generates the phenomenon that aoxidizing to prevent patterned conductive layer 124 and outer pin 132 from being invaded by water oxygen.
Fig. 6 is shown as a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention.Please also refer to Fig. 1 with
Fig. 6, the encapsulating structure 100A of encapsulating structure 100F and Fig. 1 of the present embodiment are similar, and the difference of the two is: the envelope of the present embodiment
Assembling structure 100F further includes soldermask layer 180, be configured in core structural layer 120 and at least overlay pattern conductive layer 124 and envelope
Fill the outer pin 132 of element 130.Specifically, in the present embodiment, 180 overlay pattern conductive layer 124 of soldermask layer, pattern
Change the outer pin 132 of dielectric layer 126 and potted element 130 that conductive layer 124 is exposed and between outer pin 132
Partial encapsulation colloid 136.Soldermask layer 180 can be used to that patterned conductive layer 124 or the abnormal of outer pin 132 is prevented to be electrically connected with
Touching, and generate the electrically situations such as interference or short circuit.
Fig. 7 is shown as a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention.Please also refer to Fig. 1 with
Fig. 7, the encapsulating structure 100A of encapsulating structure 100G and Fig. 1 of the present embodiment are similar, and the difference of the two is: the envelope of the present embodiment
Assembling structure 100G further includes surface-treated layer 170 ' and soldermask layer 180 '.Soldermask layer 180 ' be configured in core structural layer 120 and
Overlay pattern conductive layer 124, wherein soldermask layer 180 ' exposes the portion of upper surface S2 of patterned conductive layer 124.At surface
Reason layer 170 ' is configured on the upper surface S2 for the patterned conductive layer 124 that soldermask layer 180 ' is exposed and each outer pin
On 132 outer surface S1, with this prevents patterned conductive layer 124 and outer pin 132 from being invaded by water oxygen and generates oxidation.Encapsulation
Each outer pin 132 of element 130 is electrically connected by conducting wire W and the patterned conductive layer 124 of core structural layer 120.Into
For one step, the both ends of conducting wire W are the surface treatments that configuration is electrically connected on patterned conductive layer 124 and pin 132
Layer 170 '.In other words, the potted element 130 of the present embodiment is that the patterning by way of conducting wire W with core structural layer 120 is led
Electric layer 124 is electrically connected.
Fig. 8 is shown as a kind of diagrammatic cross-section of encapsulating structure of another embodiment of the present invention.Please also refer to Fig. 6 with
Fig. 8, the encapsulating structure 100F of encapsulating structure 100H and Fig. 6 of the present embodiment are similar, and the difference of the two is: the envelope of the present embodiment
Assembling structure 100H further includes electronic component 190 and multiple conductive through hole 190A.Electronic component 190 is configured on soldermask layer 180.It leads
Electric through-hole 190A runs through soldermask layer 180 and expose portion patterned conductive layer 124, and wherein electronic component 190 passes through conductive through hole
190A and be electrically connected patterned conductive layer 124.Herein, electronic component 190 be, for example, sensor, transmitter, receiver or its
His element appropriate, it is not limited herein.
In conclusion potted element is disposed on metal substrate and is located in the configuration of encapsulating structure of the invention
In the opening of core structural layer.In this way, potted element is in interior embedment core structural layer, and the outer pin of potted element with
The patterned conductive layer of core structural layer can reduce the overall packaging height of encapsulating structure in coplanar whereby.In addition, encapsulation member
Part is arranged on metal substrate, and the radiating efficiency of potted element can be promoted by the thermal conductive property of metal substrate.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field
Middle technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore protection of the invention
Subject to range ought be defined depending on appended claims.
Claims (16)
1. a kind of encapsulating structure characterized by comprising
Metal substrate；
Core structural layer is configured on the metal substrate, and has opening and patterned conductive layer；And
Potted element is configured on the metal substrate, and is located in the opening of the core structural layer, wherein the envelope
Filling element includes multiple outer pins, and the patterned conductive layer of the multiple outer pin and the core structural layer electrically connects
It connects, and the outer surface of each outer pin is trimmed in the upper surface of the patterned conductive layer.
2. encapsulating structure according to claim 1, which is characterized in that the metal substrate has configuration surface and groove,
The core structural layer is configured on the configuration surface, and the potted element is configured in the groove, and the configuration
Surface and the bottom surface of the groove have difference in height.
3. encapsulating structure according to claim 2, which is characterized in that the bottom surface of the groove is rough surface.
4. encapsulating structure according to claim 1, which is characterized in that the metal substrate has configuration surface, and described
Core structural layer and the potted element are configured on the configuration surface.
5. encapsulating structure according to claim 1, which is characterized in that the core structural layer includes dielectric layer, is given an account of
Electric layer is between the patterned conductive layer and the metal substrate.
6. encapsulating structure according to claim 1, which is characterized in that the potted element further include:
Chip has multiple connection pads；And
Packing colloid coats the chip and exposes the surface of each connection pad, wherein the multiple outer pin is configured at institute
State on packing colloid and be respectively connected to the surface of each connection pad.
7. encapsulating structure according to claim 1, which is characterized in that the potted element further include:
Chip carrier；
Chip is configured on the chip carrier；
Packing colloid coats the chip and the chip carrier, wherein the multiple outer pin is configured on the packing colloid；
And
A plurality of conducting wire is electrically connected between the chip and the multiple outer pin.
8. encapsulating structure according to claim 1, which is characterized in that the multiple outer pin of the potted element passes through
A plurality of conducting wire and the patterned conductive layer of the core structural layer are electrically connected.
9. encapsulating structure according to claim 1, which is characterized in that the multiple external pin structure of the potted element
Property and the patterned conductive layer for being electrically connected to the core structural layer.
10. encapsulating structure according to claim 1, which is characterized in that further include:
Insulating layer is filled between the potted element and the opening of the core structural layer.
11. encapsulating structure according to claim 1, which is characterized in that further include:
Adhesion layer is configured between the core structural layer and the metal substrate.
12. encapsulating structure according to claim 1, which is characterized in that further include:
Heat-conducting glue layer is configured between the potted element and the metal substrate.
13. encapsulating structure according to claim 1, which is characterized in that further include:
Surface-treated layer is configured at the outer surface on the upper surface of the patterned conductive layer with each outer pin
On.
14. encapsulating structure according to claim 1, which is characterized in that further include:
Soldermask layer is configured at the core structural layer, and at least covers the institute of the patterned conductive layer Yu the potted element
State multiple outer pins.
15. encapsulating structure according to claim 14, which is characterized in that further include:
Electronic component is configured on the soldermask layer；And
Multiple conductive through holes, through patterned conductive layer described in the soldermask layer and expose portion, the electronic component passes through institute
It states multiple conductive through holes and is electrically connected the patterned conductive layer.
16. encapsulating structure according to claim 1, which is characterized in that further include:
Soldermask layer is configured at the core structural layer, and covers the patterned conductive layer, wherein the soldermask layer exposes institute
State the part upper surface of patterned conductive layer；And
Surface-treated layer is configured on the upper surface for the patterned conductive layer that the soldermask layer is exposed and each institute
It states on the outer surface of outer pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710384186.9A CN108962839B (en) | 2017-05-26 | 2017-05-26 | Packaging structure |
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| CN201710384186.9A CN108962839B (en) | 2017-05-26 | 2017-05-26 | Packaging structure |
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| CN108962839A true CN108962839A (en) | 2018-12-07 |
| CN108962839B CN108962839B (en) | 2021-02-19 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111356280A (en) * | 2018-12-21 | 2020-06-30 | 深南电路股份有限公司 | Circuit board, circuit board assembly and electronic device |
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| CN102610583A (en) * | 2011-01-19 | 2012-07-25 | 旭德科技股份有限公司 | Packaging carrier board and manufacturing method thereof |
| US20130285254A1 (en) * | 2012-04-26 | 2013-10-31 | Shinko Electric Industries Co., Ltd. | Wiring substrate and method for manufacturing wiring subtrate |
| CN103000780A (en) * | 2012-12-14 | 2013-03-27 | 京东方科技集团股份有限公司 | LED (Light-Emitting Diode) chip packaging structure, manufacturing method thereof and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111356280A (en) * | 2018-12-21 | 2020-06-30 | 深南电路股份有限公司 | Circuit board, circuit board assembly and electronic device |
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