200906259 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種增層式印刷電路板（build-up PCB) 之製造方法，更明確的說，為一種增層式印刷電路板之製 5 造方法，其中增層式印刷電路板之核心電路層是經由一乾 式的金屬種子層形成製程而形成，其包括離子束表面處理 以及真空沈積，因此以一種對環境友善的方法，實現一高 可靠度之精細電路。 10 【先前技術】 目前，增層式印刷電路板使用減去法製程（subtractive process)、改良之半-加成製程（MSAP，modified semi-additive process)、以及半-加成製程（SAP， semi-additive process) ° 15 詳細來說，減去法製程是應用於高密度互相連接 (HDI，high density interconnection)產品，並且減去法製程 及MSAP應用於超薄晶片尺寸封裝（UT-CSP，ultra thin-chip scale .package)以及球型陣列（BGA，ball grid array)之產 品。再者，在覆晶球型陣列（FCBGA，flip chip BGA)的例子 20 中，核心層及建構的外部層（包括2F2B/3F3B)是分別以減去 法製程及SAP而形成，此外，一種子層經由無電電鍍而形 成，因此實現一精細電路。 關於上述，根據一第一習知技術，圖1A及1B分別顯示 形成一增層式印刷電路板之核心層及外部層的製程。 200906259 …參見圖1A及圖2八至扣’根據此第一習知技術’使用 減去法製程形成增層式印刷電路板之核心層的方法，詳述 於下文中。 首先，一樹脂基材11，其具有金屬層12層壓其兩表面， 5進行典型的银刻及鑽孔而形成—貫穿孔13 (圖2a及聊接 著具有貝f孔13之基材&表面進行去鑽污（desmearing) 後接著以無電電鑛而形成—無電電鑛金屬層“（圖2〇。經 由電鍍，形成一金屬電鍍層15(圓2D)。填充一導電膏 16(C〇miuctive paste)於貫穿孔13中（圖2E)，之後相對應於 10 一電路圖案之預定區域上形成乾膜17,並覆蓋貫穿孔13(圖 2F)。金屬層之不必要部分經由一典型之曝光/顯影及蝕刻 而移除，然後移除乾膜17，因此完成核心電路層（c〇re circuit layer)的程序（圖2G)。在進行外部層之形成製程之 刖，此基材進行典型的表面處理，例如習知技術之匚2處 15 理’然後在其上層壓一絕緣層（圖未示）。 此外’參見圖1B及圖3A至3F，根據第一習知技術所使 用之MSAP形成增層式印刷電路板外部層的製程，將詳述 如後。為方便起見，省略核心層之建構製程的敘述，只有 敘述外部層之形成製程。 20 首先，一具有金屬層22層壓於其兩表面之樹脂基材21 進行半-蝕刻（half-etched)，然後進行典型的蝕刻及鑽孔而 形成盲孔23(圖3A及3B)。之後，具有盲孔23之基材的表面 進行去鑽污及無電電鍍而形成無電電鍍金屬層24(圖3C)。 之後’在一相對應於電路圖案以外之預定區域（包括盲孔23) 200906259 形成乾膜26(圖3D)。使用乾膜為阻層，經由電鑛形成金屬 圖案電鑛層27(圖3E)。之後，移除乾膜26，㈣金屬層之 非必要部分藉由快速蝕刻而移除，因此完成圖案化之製程 (圖 3F)。 5 根據第二習知技術，形成增層式印刷電路板之核心層 及外部層的製程，分別顯示於圖4A及4B之流程圖中。 參見圖4A至圖5A至5G，使用根據第二習知技術之減 去法製程，而形成增層式印刷電路板之核心層的製程，詳 I 述於後。 1〇 首先，一包括具有厚度約12 μιη之金屬層32層壓於其 兩表面之樹脂基材31，進行典型的姓刻及錯孔，因此形成 一具有直徑約350 μπι之貫穿孔13(圖5人Α5Β)。接著，將 具有貫穿孔33之基材的表面進行去鑽污及無電電鍍，因此 形成厚度約為1〜3 μιη的無電電鍍金屬層34(圖5C)。經由電 15鍍，形成一厚度約為18 之金屬電鍍層35(圖5D)。填充 導電膏36於具有電鍍層35的貫穿孔33中（圖5E)，之後，在 ϋ 對應於一電路圖案之預定區域（包括貫穿孔33)上形成乾膜 37(圖5F)。金屬層之非必要部分經由典型之曝光/顯影和蝕 刻而移除，然後移除乾膜37,因此完成形成核心電路層的 2〇程序（圖5G)。在進行外部層之形成製程之前，此基材進行 典型的表面處理，例如如習知技術之cz處理，然後在其上 層壓一絕緣層（圖未示）。 、 此外，參見圖4B及圖6A至6F，根據第二習知技術所使 用之SAP形成增層式印刷電路板外部層的製程，將詳述如 200906259 後。為方便起見’省略核心層之建構製程的敘述，只有敘 述外部層之形成製程。 首先，一具有金屬層42層壓於其兩表面之樹脂基材 41，例如厚度約為 35 μιη之 ABF(Ajinomoto Build-Film)，進 5 行典型的触刻及錢孔而形成具有75μπι直徑之盲孔43(圖6A 及6Β)。之後，具有盲孔43之基材表面進行去鑽污及無電 電鑛，因此形成厚度約為1±〇·3 μιη之無電電鑛金屬層44(圖 6C)。之後，在一相對應於電路圖案以外之預定區域（包括 盲孔43)形成乾膜45(圖6D)。使用乾膜為阻層，經由電鍍形 1〇 成金屬圖案電鍍層46(圖6E)。之後，移除乾膜45，然後金 屬層之非必要部分藉由快速蝕刻而移除，因此完成圖案化 之製程（圖6F)。 據此，根據產品之種類，樹脂基材之材料例子包括環 氧樹脂，例如 FR-4、BT (Bismaleimide Triazine)、ABF.等。 15 舉例來說，經由減去法製程及MSAP而生產之BGA及 UT-CSP的例子中，其包括有一 BT絕緣材料，此材料之表 面輪廓（surface profile)至少1 μιη，且在減去法製程中，很 難實現具有間距不超過80 μιη(線寬/間距=40/40 μιη)的細 電路。在MSAP中，因為由於半-蝕刻所衍生之金屬層厚度 2〇 變化，可以得到具有間距約50 μιη(線寬/間距=25/25 μιη) 數量級之精細電路。 在FCBGA產品之群組中，核心層一般是使用FR-4樹脂 基材經由一減去法製程形成而實現一具有間距約為100 μιη(線寬/間距=50/50 μιη)之電路，並且所建構之外部層是 200906259 使用ABF樹脂基材經由SAP而得到一具有間距36 μηι〇線寬/ 間距=1 8/18 μιη)之精細電路。然而，據此，很難實現精細 電路之核心層，這可歸責於樹脂基材之表面粗糙度及減去 法製程本身的限制。 5 再者’在FCBGA產品之群組中，其中多層基材是使用 ABF絕緣材料經由SAP而製造，如圖7所示，減去法製程應 用於核心層（由第1〜第2層52a、52b所構成），以及應用SAP 於外部層（由第3〜第6層55a、55b、57a、57b所構成）。更明 確的說’為了形成電路，外部層之形成製程，係重複兩次 10 之包括無電電鍍形成厚度約1〜3 μιη之種子層、電鍍、去光 阻、以及快速蝕刻。因此’通孔53及電路圖案52a ' 52b、 55a、55b、57a' 57b是形成於樹脂基材 51、54a、54b、56a、 56b中。接著’形成一防焊層（s〇ider resist)並且形成防焊層 之開口部59a，59b。所以，完成一具有總共6層的FCBGA。 15 然而’使用昂貴之ABF材料造成製程成本增加及高的 產品價格。在應用SAP的例子中，ABF材料的表面輪廓 (surface profile)至少是丨μΓη，導致大的表面粗糙度及36μιη 之間距（線寬/間距=18/18 gm)。此外，經由濕式表面處理 及無電化學電鍍實現一精細電路是有其限制。 20 關於印刷電路板之輕薄短小的需求，很多製造商嘗試 開發絕緣材料以實現精細電路以及展示以增加電路之訊 號傳輸速率為目標之高功能性。根據上述之發展趨勢，將 增加輸入及輸出訊號的數目，因此，需要高可靠度的精細 電路。然而’習知的SAP遭受因為金屬種子層是經由包括 200906259 漁式表面處理及無電電鍍之濕式製程而形成，不合意地增 加了表面粗链度，而使得無法實現一精細電路。同時產生 大量的廢棄物，而衍生環境的問題。 5 【發明内容】 本發明是經由密集與大量之增層式印刷電路板製程研 究而得到，本案發明人致力於避免習知技術所面臨的問 題，而發現本發明，當形成增層式印刷電路板之核心層 時，一具金屬層層壓於其兩表面之樹脂基材，其金屬層被 1〇完全蝕刻，因此獲得一適合實現高剝離強度之表面粗糙 度，然後經由SAP形成電路層以取代一般的減去法製程， 藉由包括離子束表面處理及真空沈積之乾式製程形成金 屬種子層，並沒有使用包括濕式蝕刻及無電電鍍之一般的 濕式製程’因此以一對環境友善之方式製造一具有高可靠 15 度精細電路的增層式印刷電路板。 因此，本發明之一目的係提供一製造增層式印刷電路 板之方法’其中’包括有核心層及外部層之增層式印刷電 路板之所有電路層可經由SAP而製造，因此實現一精細電 路0 20 本發明之另一目的係提供一製造增層式印刷電路板之 方法，其中之金屬種子層係經由乾式製帛而形成，而不經 由濕式製程，因此以一對環境友善及經濟的方式實現一電 路層。 本發明之再一目的係提供一製造增層式印刷電路板之 200906259 方去’其中樹脂基材與金屬層之間的剝離強度可以增加， 因此實現一高可靠度之精細電路。 為達上述之目的’本發明提供一製造包括有一核心層 及外部層之增層式印刷電路板之方法，製造該核心層包 括以下步驟：（a)提供一第一樹脂基材，其具有金屬層層壓 於其兩表面’（b)由該第一樹脂基材之該兩表面移除該些金 屬層’（c)於不具金屬層之該第一樹脂基材中形成一作為層 間電II連接之貫穿孔；（d)使用離子束，將具有貫穿孔之該 第一樹脂基材進行表面處理；（e)使用真空沈積，形成一第 金屬種子層於已進行表面處理之該第一樹脂基材；（f)使 用電鍍，形成一第一金屬圖案電鍍層於具有該第一金屬種 子層之該基材上，（g)移除不具有第一金屬圖案電鐘層部分 之第一金屬種子層；以及（11)填充導電膏於該貫穿孔，因此 形成一核心電路層， 就本發明而論，該使甩離子束之表面處理較佳為於惰 性氣體存在下進行，該惰性氣體係選自下列群組，包括·· 氬、氧、氮、氙、四氟化碳、氫、氖、氪以及上述之混合 物。 "亥真空沈積可以使用濺錄（Sputtering)、熱蒸發（thermal evaporation)或電子束沈積（e_beam depositio)進行。 該第一金屬種子之厚度較佳為介於0.02〜4 μηι，更加為 介於0.02〜1 μιχι。 再者，該外部層係以下列步驟製造：⑴層壓一第二樹 脂基材於該核心電路層上；⑴於該第二樹脂基材中形成作 200906259 為層間電性連接之盲孔；⑻使用無電電鍍，形成第二金屬 種子層於具有該盲孔之該第二樹脂基材上；⑴使用電鍵， 形成第二金屬圖案電鍍層於具有該第二金屬種子層之該 基材上；以及（m)移除不具有該第二金屬圖案電鍍層部分之 該第二金屬種子層。 該第一樹脂基材以及該第二樹脂基材，其可為相互相 同或不同，其可包括環氧樹脂或氟樹脂。 同時’此金屬較佳為銅。 10 【實施方式】 以下’將配合附圖詳細救述本發明。 如上所述’傳統上製備增層式印刷電路板（build_up PCB)之核心層（core iayer),係利用一減去法製程 (subtractive process)，實現一電路在一樹脂基材上，其具 15有金屬層層壓於此基材之兩表面，應用乾膜、曝光、顯影 以及濕式蝕刻，然而，這樣很難得到一間距不大於8〇 μιη(線 /寬=40/40 μιη)之電路線寬。此外，為緩和這種係間距圖案 之問題，SAP被認為是有效的形成一電路之方法，其為將 基材進行通孔加工、去鑽污（desmearing) '以無電電鑛 20 (electroless plating)形成一金屬種子層、電鍍、然後快速蝕 刻。然而，如果應用SAP經由一包括無電電鍍及電鍍之典 型濕式製程而形成電路層，樹脂基材與金屬層之間充足的 剝離強度（peel strength)是不能確定的，並且它很難實現一 細間距電路。 12 200906259 5 10 15 20 在本發明中，為克服上述問題，當藉由SAp製備核心 層（core layer)時，層壓於核心層樹脂基材之兩表面的金屬 層被完全蝕刻，因此露出的表面粗糙度適合於實現高的剝 離強度，之後，以乾式製程形成一金屬種子層，包括離子 束表面處理以及真空沈積，以代替一般的濕式製程，包括 去鑽污（desmearing)以及無電電鍍。因此，經由對環境友善 的SAP，金屬上的剝離強度（> 〇·8 Kgf/cm)可以增加，最後 使實現具有高密度之細間距電路成為可能。更進一步，在 增層的外部層中（outer layer)，是使用一般濕式的去鑽污、 無電電鍍、及電鍍而形成電路層。以這種方法，因為SAp 可以應用於增層式印刷電路板的所有層別，所以可以得到 一具有高密度的細間距電路。 根據本發明，圖8入及88分別圖示形成增層式印刷電路 板之核心層及外部層之製程流程圖。 、、參閱圖8A及圖9A至9H，以下詳細說明根據本發明形 成增層式印刷電路板之核心層之製程。 首先’準備一作為PCB之樹脂基材61，其由環氧樹脂 (eP〇xy resin)或是氟樹脂（fiuorine resin)所形成，且具有金 屬層62層壓於此基材之兩表面。關於此金屬，任何導電金 屬均可使用，只要它是適合形成電路的。基於經濟利益之 考量’銅為特別有用處的。 然後’經由一全面蝕刻製程，金屬層62由樹脂基材61 之兩表面移除。因此，既使沒有額外的表面處理，此基材 露出適合實現高剝離強度之表面粗糙度（圖9B)。 13 200906259 接著，於樹脂基材61形成作為内層電性連接之内部通 孔（inner via holes)的一或多個貫穿孔63(圖9C)，並且具有 貫穿孔63之基材的表面以離子束處理。 較佳地，離子束表面處理程序可在離子劑量（i〇nd〇se) 5為1E15〜1E19(ions/cm2)及加速電壓為0,5〜20keV下進行， 其中提供惰性氣體係選自下列群組，包括Ar、〇2、、Xe、200906259 IX. Description of the Invention: [Technical Field] The present invention relates to a method for manufacturing a build-up PCB, and more specifically, to a build-up printed circuit board. The method, wherein the core circuit layer of the build-up printed circuit board is formed by a dry metal seed layer forming process, including ion beam surface treatment and vacuum deposition, thereby achieving a high reliability in an environmentally friendly manner Fine circuit of degree. 10 [Prior Art] At present, the layered printed circuit board uses a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP, semi). -additive process) ° 15 In detail, the subtractive process is applied to high-density interconnect (HDI) products, and the subtractive process and MSAP are applied to ultra-thin wafer size packages (UT-CSP, ultra Thin-chip scale .package) and ball grid array (BGA) products. Furthermore, in the example 20 of the flip chip BGA, the core layer and the constructed outer layer (including 2F2B/3F3B) are formed by subtracting the process and SAP, respectively. The layer is formed by electroless plating, thus realizing a fine circuit. Regarding the above, according to a first conventional technique, Figs. 1A and 1B respectively show a process of forming a core layer and an outer layer of a build-up printed circuit board. 200906259 ... see Fig. 1A and Fig. 2 VIII to buckle 'A method for forming a core layer of a build-up printed circuit board using the subtractive process according to this first conventional technique, as described in detail below. First, a resin substrate 11 having a metal layer 12 laminated on both surfaces thereof, 5 is formed by a typical silver engraving and drilling, and a through-hole 13 is formed (Fig. 2a and the substrate & The surface is desmearing and then formed as an electroless ore-free electroless ore metal layer (Fig. 2〇. A metal plating layer 15 (circle 2D) is formed by electroplating. Filling a conductive paste 16 (C〇 The miuctive paste is in the through hole 13 (FIG. 2E), and then a dry film 17 is formed on a predetermined region corresponding to the 10 circuit pattern, and covers the through hole 13 (FIG. 2F). The unnecessary portion of the metal layer is via a typical The exposure/development and etching are removed, and then the dry film 17 is removed, thus completing the procedure of the core circuit layer (Fig. 2G). After performing the formation process of the outer layer, the substrate is typically The surface treatment, such as the conventional technique, is followed by laminating an insulating layer (not shown). Further, referring to FIG. 1B and FIGS. 3A to 3F, the MSAP used according to the first conventional technique. The process of forming the outer layer of the build-up printed circuit board will be described in detail later. For the sake of convenience, the description of the construction process of the core layer is omitted, and only the formation process of the outer layer is described. 20 First, a resin substrate 21 having a metal layer 22 laminated on both surfaces thereof is half-etched. Then, a typical etching and drilling is performed to form a blind via 23 (Figs. 3A and 3B). Thereafter, the surface of the substrate having the blind via 23 is subjected to desmear and electroless plating to form an electroless plated metal layer 24 (Fig. 3C). Then, a dry film 26 (Fig. 3D) is formed in a predetermined region (including the blind hole 23) 200906259 corresponding to the circuit pattern. The dry film is used as a resist layer to form a metal pattern electric ore layer 27 via the electric ore (Fig. 3E) After that, the dry film 26 is removed, and the unnecessary portion of the (4) metal layer is removed by rapid etching, thereby completing the patterning process (Fig. 3F). 5 According to the second conventional technique, the layered printed circuit is formed. The processes of the core layer and the outer layer of the board are respectively shown in the flow charts of Figures 4A and 4B. Referring to Figures 4A to 5A to 5G, the layer-by-layer printing is formed using the subtractive process according to the second conventional technique. The process of the core layer of the board is described in detail later. First, a resin substrate 31 comprising a metal layer 32 having a thickness of about 12 μm laminated on both surfaces thereof is subjected to a typical surname and a wrong hole, thereby forming a through hole 13 having a diameter of about 350 μm ( 5, the surface of the substrate having the through holes 33 is subjected to desmear and electroless plating, thereby forming an electroless plated metal layer 34 having a thickness of about 1 to 3 μm (Fig. 5C). A metal plating layer 35 having a thickness of about 18 is formed (Fig. 5D). The conductive paste 36 is filled in the through hole 33 having the plating layer 35 (Fig. 5E), and thereafter, in a predetermined region corresponding to a circuit pattern (including A dry film 37 is formed on the through hole 33) (Fig. 5F). The unnecessary portion of the metal layer is removed by typical exposure/development and etching, and then the dry film 37 is removed, thus completing the 2〇 process of forming the core circuit layer (Fig. 5G). Prior to the formation of the outer layer, the substrate is subjected to a typical surface treatment such as cz treatment as in the prior art, and then an insulating layer (not shown) is laminated thereon. Further, referring to Fig. 4B and Figs. 6A to 6F, the process of forming the outer layer of the build-up printed circuit board by the SAP used in the second conventional technique will be described in detail as after 200906259. For the sake of convenience, the description of the construction process of the core layer is omitted, and only the formation process of the outer layer is described. First, a resin substrate 41 having a metal layer 42 laminated on both surfaces thereof, for example, ABF (Ajinomoto Build-Film) having a thickness of about 35 μm, is formed into 5 rows of typical contact and money holes to form a diameter of 75 μm. Blind hole 43 (Figs. 6A and 6B). Thereafter, the surface of the substrate having the blind holes 43 is subjected to desmear and electroless ore, thereby forming an electroless ore metal layer 44 having a thickness of about 1 ± 3 μm (Fig. 6C). Thereafter, a dry film 45 is formed at a predetermined region (including the blind via 43) corresponding to the circuit pattern (Fig. 6D). A dry film is used as a resist layer, and a metal pattern plating layer 46 is formed via plating (Fig. 6E). Thereafter, the dry film 45 is removed, and then unnecessary portions of the metal layer are removed by rapid etching, thus completing the patterning process (Fig. 6F). Accordingly, examples of the material of the resin substrate include epoxy resins such as FR-4, BT (Bismaleimide Triazine), ABF., etc., depending on the kind of the product. 15 For example, the BGA and UT-CSP examples produced by subtracting the process and MSAP include a BT insulating material having a surface profile of at least 1 μηη and subtracting the process. In the case, it is difficult to realize a fine circuit having a pitch of not more than 80 μm (line width/pitch=40/40 μm). In MSAP, a fine circuit having a pitch of about 50 μm (line width/pitch = 25/25 μm) can be obtained because the thickness of the metal layer derived from the half-etching varies by 2 。. In the group of FCBGA products, the core layer is generally realized by a subtractive process using an FR-4 resin substrate to form a circuit having a pitch of about 100 μm (line width/pitch=50/50 μm), and The outer layer constructed is 200906259. A fine circuit with a pitch of 36 μηι 〇 line width/pitch = 18/18 μηη is obtained via SAP using an ABF resin substrate. However, according to this, it is difficult to realize the core layer of the fine circuit, which can be attributed to the surface roughness of the resin substrate and the limitation of the process itself. 5 Further, in the group of FCBGA products, in which the multilayer substrate is manufactured by using SAP using ABF insulating material, as shown in FIG. 7, the subtractive process is applied to the core layer (from the first to the second layer 52a, The configuration of 52b) and the application of SAP to the external layer (consisting of the third to sixth layers 55a, 55b, 57a, and 57b). More specifically, in order to form a circuit, the formation process of the outer layer is repeated twice including electroless plating to form a seed layer having a thickness of about 1 to 3 μm, electroplating, photoresist removal, and rapid etching. Therefore, the through holes 53 and the circuit patterns 52a' 52b, 55a, 55b, 57a' 57b are formed in the resin substrates 51, 54a, 54b, 56a, 56b. Next, a solder resist is formed and the opening portions 59a, 59b of the solder resist layer are formed. Therefore, a FCBGA having a total of 6 layers is completed. 15 However, the use of expensive ABF materials has resulted in increased process costs and high product prices. In the example of applying SAP, the surface profile of the ABF material is at least 丨μΓη, resulting in a large surface roughness and a distance of 36 μm (line width/pitch = 18/18 gm). In addition, there is a limit to achieving a fine circuit through wet surface treatment and electroless plating. 20 With regard to the thinness and lightness of printed circuit boards, many manufacturers have attempted to develop insulating materials to implement fine circuits and exhibit high functionality aimed at increasing the signal transmission rate of the circuit. According to the above development trend, the number of input and output signals will be increased, and therefore, a high-reliability fine circuit is required. However, the conventional SAP suffers from the fact that the metal seed layer is formed by a wet process including 200906259 fish-type surface treatment and electroless plating, which undesirably increases the surface thick chain, making it impossible to realize a fine circuit. At the same time, a large amount of waste is generated, and the problem of the environment is derived. 5 SUMMARY OF THE INVENTION The present invention has been made through intensive and large-scale layered printed circuit board process research, and the inventors of the present invention have been working to avoid the problems faced by the prior art, and have found the present invention to form a build-up printed circuit. In the core layer of the board, a metal substrate is laminated on the resin substrate on both surfaces thereof, and the metal layer is completely etched by 1 ,, thereby obtaining a surface roughness suitable for achieving high peel strength, and then forming a circuit layer via SAP Instead of the general subtractive process, the metal seed layer is formed by a dry process including ion beam surface treatment and vacuum deposition, and the general wet process including wet etching and electroless plating is not used. Therefore, a pair of environmentally friendly A method of manufacturing a build-up printed circuit board with a highly reliable 15 degree fine circuit. Accordingly, it is an object of the present invention to provide a method of manufacturing a build-up printed circuit board in which all of the circuit layers of the build-up printed circuit board including the core layer and the outer layer can be fabricated via SAP, thereby achieving a fine Circuit 0 20 Another object of the present invention is to provide a method of manufacturing a build-up printed circuit board in which a metal seed layer is formed by dry squeezing without a wet process, thereby providing a friendly and economical environment. The way to implement a circuit layer. A further object of the present invention is to provide a layered printed circuit board in which the peel strength between the resin substrate and the metal layer can be increased, thereby realizing a high-reliability fine circuit. For the above purposes, the present invention provides a method of manufacturing a build-up printed circuit board comprising a core layer and an outer layer, the core layer comprising the steps of: (a) providing a first resin substrate having a metal Laminating a layer on both surfaces '(b) removing the metal layers from the two surfaces of the first resin substrate' (c) forming an interlayer dielectric in the first resin substrate having no metal layer a through hole connected; (d) surface treating the first resin substrate having the through hole using an ion beam; (e) forming a first metal seed layer on the surface treated first resin using vacuum deposition a substrate; (f) using a plating to form a first metal pattern plating layer on the substrate having the first metal seed layer, (g) removing the first metal without the first metal pattern clock layer portion a seed layer; and (11) filling a conductive paste in the through hole, thereby forming a core circuit layer. For the purposes of the present invention, the surface treatment of the erbium ion beam is preferably performed in the presence of an inert gas system. Selected from the following groups , ·· comprising argon, oxygen, nitrogen, xenon, carbon tetrafluoride, hydrogen, neon, krypton and mixtures thereof of the above. "Heil vacuum deposition can be performed using sputtering, thermal evaporation, or electron beam deposition (e_beam depositio). The thickness of the first metal seed is preferably from 0.02 to 4 μηι, more preferably from 0.02 to 1 μιη. Furthermore, the outer layer is manufactured by: (1) laminating a second resin substrate on the core circuit layer; (1) forming a blind hole in the second resin substrate as an electrical connection between layers; (8) Forming a second metal seed layer on the second resin substrate having the blind via using electroless plating; (1) forming a second metal pattern plating layer on the substrate having the second metal seed layer using an electrical bond; (m) removing the second metal seed layer that does not have the portion of the second metal pattern plating layer. The first resin substrate and the second resin substrate may be the same or different from each other, and may include an epoxy resin or a fluororesin. At the same time, the metal is preferably copper. [Embodiment] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. As described above, the core layer iayer of the build-up PCB is conventionally fabricated by using a subtractive process to realize a circuit on a resin substrate having 15 A metal layer is laminated on both surfaces of the substrate, and dry film, exposure, development, and wet etching are applied. However, it is difficult to obtain a circuit having a pitch of not more than 8 μm (line/width = 40/40 μm). Line width. In addition, in order to alleviate the problem of such a pitch pattern, SAP is considered to be an effective method of forming a circuit for through-hole processing and desmearing of a substrate to electroless plating 20 (electroless plating). A metal seed layer is formed, plated, and then quickly etched. However, if the application SAP forms a circuit layer via a typical wet process including electroless plating and electroplating, sufficient peel strength between the resin substrate and the metal layer is undeterminable, and it is difficult to achieve a fine Spacing circuit. 12 200906259 5 10 15 20 In the present invention, in order to overcome the above problem, when a core layer is prepared by SAp, the metal layer laminated on both surfaces of the core layer resin substrate is completely etched, thus being exposed The surface roughness is suitable for achieving high peel strength, after which a metal seed layer is formed in a dry process, including ion beam surface treatment and vacuum deposition, instead of the usual wet process, including desmearing and electroless plating. Therefore, the peel strength (> 8 Kgf/cm) on the metal can be increased via the environmentally friendly SAP, and finally it is possible to realize a fine pitch circuit having a high density. Further, in the outer layer of the build-up layer, the circuit layer is formed using general wet type de-soiling, electroless plating, and electroplating. In this way, since SAp can be applied to all layers of the build-up printed circuit board, a fine pitch circuit having a high density can be obtained. In accordance with the present invention, Figures 8 and 88 illustrate process flow diagrams for forming the core and outer layers of a build-up printed circuit board, respectively. Referring to Figures 8A and 9A through 9H, the process of forming the core layer of the build-up printed circuit board in accordance with the present invention will now be described in detail. First, a resin substrate 61 as a PCB, which is formed of an epoxy resin or a fluorinated resin, is formed, and has a metal layer 62 laminated on both surfaces of the substrate. Regarding this metal, any conductive metal can be used as long as it is suitable for circuit formation. Based on economic considerations, 'copper is particularly useful. The metal layer 62 is then removed from both surfaces of the resin substrate 61 via a full etching process. Therefore, even without additional surface treatment, the substrate exposes a surface roughness suitable for achieving high peel strength (Fig. 9B). 13 200906259 Next, one or more through holes 63 (FIG. 9C) which are inner via holes electrically connected to the inner layer are formed on the resin substrate 61, and the surface of the substrate having the through holes 63 is ion beam deal with. Preferably, the ion beam surface treatment procedure is performed at an ion dose of 1E15 to 1E19 (ions/cm2) and an acceleration voltage of 0,5 to 20 keV, wherein the inert gas system is selected from the following Groups, including Ar, 〇 2, Xe,
Cl?4、Η2、Ne、Kr以及上述之混合物，但是本發明並不侷 限於上述之條件。根據基材物質的種類，可以適當地設定 真實的製程條件，其對本技術領域之人而言是顯而易見 10 的。 經由這樣乾式離子束表面處理程序，樹脂基材對接續 要形成金屬種子層的剝離強度可以增加。亦即，如圖12所 示，樹脂基材之高分子材料之表面藉由具有可形成不穩定 連接之能量的惰性或反應性離子而被激發，其可以與反應 15 氣體（例如氧氣）進行化學反應，因此，基材之疏水性表面 轉變成親水性’因此增加材料的剝離強度。所以，實現細 間距電路是可能的。 在經過離子束表面處理之基材61上，以真空沈積 (vacuum deposition)形成一金屬離子層64至所要求的厚度 20 (圖 9D)。 真空沈積製程舉例可為錢鑛（sputtering)、熱蒸發 (thermal evaporation)、或電子束沈積（e_beam deposition)， 但並非受限於此，只要為該技術所習知的方法均可。 金屬種子層可形成0.02〜4 μιη之厚度，較佳為0.02〜1 200906259 μιη，更加為0.02〜0.5 μιη。特別是，由真空沈積所得之金 屬種子層，可以選擇性的形成比使用一般濕式無電電鍍所 形成之金屬種子層（2〜3 μιη)更薄的厚度，因此後續快速蝕 刻製程所需之工作時間可以減少、生產性得以提升，並且 5可以避免形成底切（undercutting)，因此得到具有高密度之 精細核心電路導線。再者，一乾式真空沈積製程，其可以 取代一般濕式無電電鍍製程，並可作為形成金屬種子層， 且因為不會產生廢液，所以被認為是對環境友善的。 接著，如習知技術，作為一電鍍阻層之乾膜65形成於 1〇預定區域，其為圖案電鍍區域以外（圖9E)，之後，電鍍一 電鍍金屬圖案以及移除乾膜65,因此，形成一金屬圖案電 鍍層66(圖9F)。 不具圖案電鍍層66之金屬種子層64藉由典型的快速蝕 刻而移除（圖9G)，並且具有圖案電鍍層66之貫穿孔⑺以習 15知的導電膏67填充其中，因此完成一核心電路層（圖9H)。 參見圖8B及圖10A至10F’根據本發明，於增層式印刷 電路板之核心層上建構外部層之製程將敘遞於下文。 圖9ΪΪ之核心電路層進行典型的表面處理，例如cZ處理 (CZ8100,可由MES得到），以增加電路層的表面粗糙度用 2〇以確保材料對樹脂基材之剝離強度，之後一由環氧樹脂或 氟樹月曰所形成之基材71 (可與核心層相同或不同）被層壓在 其上方（圖10A)。 接著，作為層間電性連接之盲孔72形成於樹脂基材71 中（圖10B)。經由進行去鑽污製程、無電電鍍之典型的表面 15 200906259 處理’因此得到厚度約2〜3 μιη之金屬種子層73(圖l〇C)。 接著’乾膜74形成於一預定區域’其為對應於包含盲 孔72之一電路圖案區域之外（圖1〇D)。使用乾膜為一阻層， 經由電鍍形成一金屬圖案電鍍層75(圖10E)。 5 接著，移除乾膜74，並且經由典型的快速蝕刻將不具 有金屬圖案電鑛層75之金屬種子層73的部分移除，因此完 成一外部電路層（圖10F)。 選擇性地，如圖10A至10F所示之SAP可以被重複兩次 以形成一第三層至第六層。此外，當FCBGA之最外層被應 10 用，一防焊阻層被形成，經由一典型的防焊阻層開口製程 而形成防焊阻層之開口部分，然後藉由鎳/金的無電電鍍形 成一凸塊’如典型的習知技術。 所製造之具有6層的FCBGA如圖11所示。 如圖11所示，提供了包括第一電路層82a、82b及通孔 15 83之第一樹脂基材81為核心層，並且提供了包括盲孔及第 二電路層85a、85b之第二樹脂基材84a、84b以及包括盲孔 及第三電路層87a、87b之第三樹脂基材86&、86b為外部層。 此外供了防知阻層88a、8 8b為最外層，並且經由一預 定的開口製程形成防焊阻層之開口部分89a、8处。 20 根據增層式印刷電路板之最後使用，外部層建構製程 可以重複數次，並且可以進一步進行一隨後之預設製程。 所製造之增層式印刷電路板可應用HDI、UT-CSP、 BGA、FCBG等等，且可以無限制的應用到實現細間距電 路之所有產品。 16 200906259 根據本發明之製造增層式印刷電路板的製程，因為具 有金屬層層壓於其兩表面之樹脂基材被使用成核心層的 基材之狀態是其中的金屬層被移除，此樹脂基材可以露出 適當之表面粗糙度（Ra<0.8 μιη)而實現高的剝離強度而不 5需另外的表面處理。再者，基材表面之粗链被使用離子束 處理，因此增加對金屬的剝離強度（>〇 8 Kgf/cm)，造成細 間距電路的實現。此外，利用乾式製程形成金屬種子層而 取代一般的濕式製程，所以細間距電路之核心層可以最小 的表面粗糙度（Ra < 0·8 μιη)而實現，經由一對環境友善的 10製程方式。再者，增層式印刷電路板的所有層，包括核心 層及外部層，可以進行SAP而形成電路。因此，實現一具 有高密度、高可靠度之細間距電路是可能的。 本發明之-較佳理解可由以下的實施例得到，其為說 明而敘述，而不是被解釋成限制本發明。 15 實施例1 _ A.具有銅薄膜層壓於其兩表面之FR-4 CCL(覆蓋 銅，copper dad laminate)，使用FeaA刻劑為將其完全鞋 刻’因此移除兩層鋼薄膜。不具有銅薄膜之fr_4基材使用 CNC (電腦數位控制）鑽頭進行機械鑽孔，以形成具有直徑 約議〜300哗的通孔’然後使錢氣在約i Μ的加速電 壓’以及1E15的離子劑量⑽dQse)下進行離子束表面處 理。之後，在經處縣材的表面上，制錢錢沈積厚 度約為0.3㈣的銅種子層。接著，在一預定空氣流動體積 17 200906259 (0,05~0,15 m3/min)，.溫度（20〜25°C) ’ 以及電流密度 (F/B1.5ASD)的條件下，藉由以H2SO4(120〜160 gm)、Cu (20〜40 g/1)、Cl_ (20〜50 ppm)、以及cupracid HL平坦劑 (5〜15 ml/1)的銅圖案電鍍形成厚度約為1〇〜20 μιη之銅圖案 5 電鍍層，之後藉由快速蝕刻（蝕刻速度2 m/min，使用 H2S04/H202蝕刻劑）移除銅種子層。最後’在黏度為3.0 pa.s，預熱處理為80oC/60 min以及固化為16〇°C/60min的條 件下，以銅膏填充於通孔中，因此完成一核心電路層。 Ο B.所得到的核心電路層進行CZ處理（CZ8100，可由 10 MEC得到）以增加銅的表面粗糙度而確保對基材材料的剝 離強度。使用主要的真空壓合設備’在條件為溫度100°c、 真空時間30秒、壓力7 kgf/cm2，以及按壓時間60秒’於核 心電路層上暫時性地熔接ABF，然後使用二級熱壓’在條 件為溫度100°C、壓力10kgf/cm2 ’以及按壓時間90秒下層 15 壓。接著使用二氧化碳雷射形成直徑約為7〇 μιη的盲孔， 以及在澎潤製程中使用高錳酸（permanganic acid) ’污斑於 〇 pHIO〜12因澎潤而被移除（(：114+12]^11〇4-+14011-->(：032- + 12Mn〇42- + 9H20 + 02)，因此形成預定的表面粗糙度。 隨後，經由中和（neutralization)而移除二氧化猛（manganese 20 dioxide)殘餘物（CH4 + 12Mn〇4- + 140H- ->· CO32- + 12Μη〇42·+9Η20 + 02)，進行去鑽污處理’以及在CuS04 + 2HCHO + 4NaOH Cu + 2HC02Na + H2 + 2H20 + Na2S04 的狀態下進行銅的無電電鍍（Atotech)，因此形成厚度約3 μηι的銅種子層。接著，藉由銅圖案電鍵（Evara)，以H2S04 18 200906259 (120〜160 gl/l)、Cu (20〜40 gA)、Cl· (20〜50 ppm)、及cupracid HL平坦劑（5〜15 ml/1)，在條件為預設空氣流量體積為 0.05〜0.15 m3/min、溫度20〜25°C及電流密度為 F/B1.5ASD、形成厚度約為15 μιη的銅圖案電鍍層，之後’ 5 使用H2S04/H2〇2為蝕刻劑，經由蝕刻速率為2 m/min之快速 姓刻移除銅種子層。 C.在B中所得到的基材進行兩次的建構製程（build-up process)，其與B的製程相同而形成包括第三層到第六層的 ( 外部層。在條件為滾輪高度（roll pitch) : 370 μιη、350 μιη 10 及 320 μιη，滾軸下壓（roll press)，到條下壓（doctor bar press)，滾軸速度：1.2〜1·6 m/min，以及乾燥溫度/時間： 78°C ± 2°C，形成防焊阻層，然後在第一停滯時間為30秒 及第二停滯時間為30秒下預烤，所以溶劑由油墨中移除， 並且所形成之油墨的表面是部分硬化（cured)及乾燥的，因 15 此適合於曝光製程。在曝光製程中，UV光以光強度為 700〜900 mJ/cm2照射於所形成之油墨的表面，並且經由一 C) 工作膜（working film)/玻璃光罩誘發油墨的光硬化反應 (photocuring)，使得油墨可以在顯影液中作為阻抗的功 能。在顯影製程中，油墨之光硬化部分於碳酸鈉（Na2C03 20 1%)中可作為阻抗，反之，沒有光硬化部分被溶解及移除。 所使用1%碳酸鈉水溶液（1 % sodium carbonate)之條件為： 碳酸鈉濃度 11 ± 1.0 g/l(SPEC: 10.5 ± 2.0 gA)，碳酸鈉pH 值10.0〜12.5，碳酸鈉溫度30 ± 3°C，顯影壓力，以及顯影 速度’並且進行紫外光硬化（UV curing)(被顯影之油墨的表 19 200906259 面是經過進一步的光硬化，所以不完全的光反應因紫外光 曝光而被另外誘發，以增加SR的性質）。為了改善後硬化 (post-cured)(完全乾燥）之油墨與銅之間的剝離強度，以及 增加油墨的硬度，油墨中硬化試劑（curing agent)之雙鍵被 5 活化，並且所有硬化試劑中的樹脂於後硬化製程 (post-curing process)中開始反應而產生完整的高分子。其 條件為溫度/時間：120°C/30 min及150°C/60 min，對應於凸 塊之電路圖案的部分，經由防焊層之開口而露出，隨後在 條件為硼酸：22~38 gn，pH : 3.5〜4.5，氨基磺酸鎳（nickel 10 sulfamate): 400〜500 g/1，氣化錄：8〜16 g/1，.Fe : 200ppm或 以下，Cu : 200 ppm或以下，以及溫度：45〜55°C，進行鎳 的無電電鍍，然後在條件為Au: 5.5〜7.5 gH，pH: 6.1〜6.4， 比重：1.09〜1.24，Fe: 50 ppm或以下，Cu: 18 ppm.或以下， Ni: 350 ppm或以下，Zn: 5 ppm或以下，T1:. 5〜15 ppm，以 15 及溫度：65〜75°C，進行金的無電電鍍，因此製造FCBGA。 增層式印刷電路板的剝離強度因此被製造出，並且量 測絕緣材料的表面粗糙度。其結果顯示於以下表1中。 實施例2Cl?4, Η2, Ne, Kr, and mixtures thereof, but the present invention is not limited to the above conditions. Depending on the kind of the substrate material, the actual process conditions can be appropriately set, which will be apparent to those skilled in the art. Through such a dry ion beam surface treatment procedure, the peel strength of the resin substrate to form a metal seed layer can be increased. That is, as shown in Fig. 12, the surface of the polymer material of the resin substrate is excited by inert or reactive ions having energy capable of forming an unstable connection, which can be chemically reacted with a reaction gas such as oxygen. The reaction, therefore, the hydrophobic surface of the substrate transforms into hydrophilicity' thus increasing the peel strength of the material. Therefore, it is possible to implement a fine pitch circuit. On the ion beam surface-treated substrate 61, a metal ion layer 64 is formed by vacuum deposition to a desired thickness 20 (Fig. 9D). The vacuum deposition process may be, for example, sputtering, thermal evaporation, or e_beam deposition, but is not limited thereto, as long as it is a method known in the art. The metal seed layer may have a thickness of 0.02 to 4 μm, preferably 0.02 to 1 2009 06259 μmη, more preferably 0.02 to 0.5 μm. In particular, the metal seed layer obtained by vacuum deposition can selectively form a thinner thickness than the metal seed layer (2 to 3 μm) formed by general wet electroless plating, so that the work required for the subsequent rapid etching process is required. Time can be reduced, productivity can be improved, and 5 can avoid undercutting, thus obtaining a fine core circuit wire with high density. Furthermore, a dry vacuum deposition process, which can replace the conventional wet electroless plating process, can be used as a metal seed layer and is considered environmentally friendly because it does not generate waste liquid. Next, as in the prior art, a dry film 65 as a plating resist layer is formed in a predetermined region which is outside the pattern plating region (FIG. 9E), after which a plating metal pattern is plated and the dry film 65 is removed, and thus, A metal pattern plating layer 66 is formed (Fig. 9F). The metal seed layer 64 without the pattern plating layer 66 is removed by a typical rapid etching (Fig. 9G), and the through hole (7) having the pattern plating layer 66 is filled therein with the conductive paste 67, thus completing a core circuit Layer (Figure 9H). Referring to Figure 8B and Figures 10A through 10F', a process for constructing an outer layer on the core layer of a build-up printed circuit board will be described below in accordance with the present invention. The core circuit layer of Figure 9 is subjected to a typical surface treatment, such as cZ processing (CZ8100, available from MES), to increase the surface roughness of the circuit layer by 2 〇 to ensure the peel strength of the material to the resin substrate, followed by epoxy A substrate 71 (which may be the same as or different from the core layer) formed of a resin or fluorophyllin is laminated thereon (Fig. 10A). Next, a blind hole 72 which is electrically connected between the layers is formed in the resin substrate 71 (Fig. 10B). The surface of the metal seed layer 73 (Fig. 10C) having a thickness of about 2 to 3 μm is obtained by performing a typical surface of the desmear process, electroless plating, 15 200906259. Next, the 'dry film 74 is formed in a predetermined area' which corresponds to a circuit pattern area including one of the blind holes 72 (Fig. 1A). Using a dry film as a resist layer, a metal pattern plating layer 75 is formed via electroplating (Fig. 10E). 5 Next, the dry film 74 is removed, and a portion of the metal seed layer 73 having no metal pattern electroderatic layer 75 is removed via typical rapid etching, thus completing an external circuit layer (Fig. 10F). Alternatively, the SAP as shown in Figs. 10A to 10F may be repeated twice to form a third layer to a sixth layer. In addition, when the outermost layer of the FCBGA is used, a solder resist layer is formed, and an opening portion of the solder resist layer is formed through a typical solder resist layer opening process, and then formed by electroless plating of nickel/gold. A bump 'is as a typical prior art. The manufactured FCBGA having 6 layers is shown in FIG. As shown in FIG. 11, a first resin substrate 81 including a first circuit layer 82a, 82b and a via hole 835 is provided as a core layer, and a second resin including a blind via and second circuit layers 85a, 85b is provided. The base materials 84a, 84b and the third resin substrate 86&, 86b including the blind holes and the third circuit layers 87a, 87b are outer layers. Further, the anti-knowledge layers 88a, 8 8b are provided as the outermost layer, and the opening portions 89a, 8 of the solder resist layer are formed via a predetermined opening process. 20 Depending on the final use of the layered printed circuit board, the external layer construction process can be repeated several times and a subsequent preset process can be further performed. The fabricated layered printed circuit boards can be applied to HDI, UT-CSP, BGA, FCBG, etc., and can be applied to all products that implement fine pitch circuits without limitation. 16 200906259 A process for manufacturing a build-up printed circuit board according to the present invention, in which a state in which a resin substrate having a metal layer laminated on both surfaces thereof is used as a core layer is a state in which a metal layer is removed, The resin substrate can expose a suitable surface roughness (Ra < 0.8 μηη) to achieve high peel strength without requiring additional surface treatment. Further, the thick chain on the surface of the substrate is treated with an ion beam, thereby increasing the peel strength to the metal (> K 8 Kgf/cm), resulting in the realization of a fine pitch circuit. In addition, the dry process is used to form the metal seed layer instead of the general wet process, so the core layer of the fine pitch circuit can be realized with a minimum surface roughness (Ra < 0·8 μιη), via a pair of environmentally friendly 10 processes. the way. Furthermore, all layers of the build-up printed circuit board, including the core layer and the outer layer, can be formed into a circuit by performing SAP. Therefore, it is possible to realize a fine pitch circuit with high density and high reliability. The invention is preferably understood by the following examples, which are set forth to illustrate and not to limit the invention. 15 Example 1 A. FR-4 CCL (copper dad laminate) having a copper film laminated on both surfaces thereof, using FeaA engraving to completely engrave it' thus removing two layers of steel film. The fr_4 substrate without a copper film is mechanically drilled using a CNC (Computer Digital Control) drill bit to form a through hole having a diameter of about ~300 ' and then making an acceleration voltage of about i Μ and 1E15 ions. The ion beam surface treatment was carried out at a dose of (10) dQse). Then, on the surface of the sap of the county, the money was deposited to deposit a copper seed layer having a thickness of about 0.3 (four). Then, under a predetermined air flow volume of 17 200906259 (0,05~0,15 m3/min), .temperature (20~25 °C)' and current density (F/B1.5ASD), The copper pattern of H2SO4 (120~160 gm), Cu (20~40 g/1), Cl_ (20~50 ppm), and cupracid HL flattening agent (5~15 ml/1) is plated to a thickness of about 1 〇~ A 20 μm copper pattern 5 was electroplated, after which the copper seed layer was removed by rapid etching (etching speed 2 m/min using H2S04/H202 etchant). Finally, at a viscosity of 3.0 pa.s, a preheat treatment of 80oC/60 min, and a curing of 16 〇 ° C / 60 min, a copper paste was filled in the via hole, thereby completing a core circuit layer. Ο B. The obtained core circuit layer is subjected to CZ treatment (CZ8100, available from 10 MEC) to increase the surface roughness of copper to ensure the peeling strength to the substrate material. Temporarily splicing ABF on the core circuit layer using a primary vacuum laminating device 'on a temperature of 100 ° C, a vacuum time of 30 seconds, a pressure of 7 kgf/cm 2 , and a press time of 60 seconds ', then using a secondary hot press The layer 15 was pressed under the conditions of a temperature of 100 ° C, a pressure of 10 kgf/cm 2 ', and a pressing time of 90 seconds. Then use a carbon dioxide laser to form a blind hole with a diameter of about 7 μm, and use permanganic acid in the moisturizing process. The stain is removed by the pHIO~12 due to sputum ((:114+ 12]^11〇4-+14011-->(:032- + 12Mn〇42- + 9H20 + 02), thus forming a predetermined surface roughness. Subsequently, the manganese dioxide is removed by neutralization. (manganese 20 dioxide) residue (CH4 + 12Mn〇4- + 140H-->·CO32- + 12Μη〇42·+9Η20 + 02), subjected to desmear treatment 'and in CuS04 + 2HCHO + 4NaOH Cu + 2HC02Na Electroless plating of copper (Atotech) was carried out in the state of +H2 + 2H20 + Na2S04, thereby forming a copper seed layer having a thickness of about 3 μm. Then, by a copper pattern key (Evara), H2S04 18 200906259 (120 to 160 gl/ l), Cu (20~40 gA), Cl· (20~50 ppm), and cupracid HL flattening agent (5~15 ml/1) under the condition that the preset air flow volume is 0.05~0.15 m3/min, The temperature is 20~25°C and the current density is F/B1.5ASD, forming a copper pattern plating layer with a thickness of about 15 μm, then '5 using H2S04/H2〇2 as the etch The copper seed layer is removed by a rapid surname of 2 m/min. C. The substrate obtained in B is subjected to two build-up processes, which are the same as the process of B. Forming the third layer to the sixth layer (the outer layer. Under the condition of roll pitch: 370 μηη, 350 μιη 10 and 320 μηη, roll press, to bar bar) Press), roller speed: 1.2~1·6 m/min, and drying temperature/time: 78 °C ± 2 °C, forming a solder resist layer, then the first dead time is 30 seconds and the second dead time Pre-baked for 30 seconds, so the solvent is removed from the ink, and the surface of the formed ink is partially cured and dried, as this is suitable for the exposure process. In the exposure process, UV light is used as the light intensity. Irradiating the surface of the formed ink for 700 to 900 mJ/cm 2 and inducing photocuring of the ink via a C) working film/glass reticle so that the ink can act as an impedance in the developer The function. In the developing process, the photohardening portion of the ink serves as an impedance in sodium carbonate (Na2C03 20 1%), whereas no photohardened portion is dissolved and removed. The conditions for using 1% sodium carbonate are: sodium carbonate concentration 11 ± 1.0 g / l (SPEC: 10.5 ± 2.0 gA), sodium carbonate pH 10.0 ~ 12.5, sodium carbonate temperature 30 ± 3 ° C, development pressure, and development speed' and UV curing (the surface of the developed ink is shown in Table 19 200906259 after further photohardening, so the incomplete photoreaction is additionally induced by ultraviolet light exposure, To increase the nature of SR). In order to improve the peel strength between the post-cured (completely dried) ink and copper, and to increase the hardness of the ink, the double bond of the curing agent in the ink is activated by 5, and in all the hardening agents The resin begins to react in a post-curing process to produce a complete polymer. The condition is temperature/time: 120 ° C / 30 min and 150 ° C / 60 min, corresponding to the portion of the circuit pattern of the bump, exposed through the opening of the solder resist layer, and then under the condition of boric acid: 22~38 gn , pH: 3.5~4.5, nickel 10 sulfamate: 400~500 g/1, gasification record: 8~16 g/1, .Fe: 200ppm or less, Cu: 200 ppm or less, and Temperature: 45 to 55 ° C, electroless plating of nickel, then in the conditions of Au: 5.5 ~ 7.5 gH, pH: 6.1 ~ 6.4, specific gravity: 1.09 ~ 1.24, Fe: 50 ppm or less, Cu: 18 ppm. or Hereinafter, Ni: 350 ppm or less, Zn: 5 ppm or less, T1: 5 to 15 ppm, and electroless plating of gold at 15 and temperature: 65 to 75 ° C, thereby producing FCBGA. The peel strength of the build-up printed circuit board is thus manufactured, and the surface roughness of the insulating material is measured. The results are shown in Table 1 below. Example 2
20 一 FCBGA以相同於實施例1的方法製造，除了在階段A 中以離子束濺鍍代替直流濺鍍。 增層式印刷電路板的剝離強度因此被製造出，並且量 測絕緣材料的表面粗糙度。其結果顯示於以下表1中。 25 比較例1 20 200906259 一FCBGA以相同於實施例1的方法製造，除了在階段A 中，略去離子束表面處理及直流濺鑛沈積，並且使用如下 所述之一般的濕式製程包括去鑽污及銅的無電電鍍而形 成銅種子層。 5 增層式印刷電路板的剝離強度因此被製造出，並且量 測絕緣材料的表面粗糙度。其結果顯示於以下表1中。 ※去錯污 澎潤（為軟化劑之功能，最佳餘刻於pH為1 〇〜12，亦 即，作為澎潤污斑）-> 三階段水洗4高錳酸處理（去除主要 1〇 污斑且將樹脂表面粗糙化）-> 一階段水洗-> 兩階段水洗— 中和（去除二氧化錳殘留）_>三階段水洗—乾燥 ※無電電鍍銅 清洗（是一鹼性化學清洗製程，其是為了高的剝離強度 以及為了鈀吸附之條件製程）—三階段水洗—蝕刻清洗（去 15 除鋼的氧化層以及為確保銅層間的剝離強度而粗糙化）— 二階段水洗->·預浸洗（去除過硫酸鹽（persulfate)殘留及作 為一預活化劑（pre-activator))—活化劑（鈀離子（非凝膠態） 吸附）-> 三階段水洗-> 還原（將鈀離子還原成鈀以作為觸媒） ->三階段水洗-> 化學銅（使用鈀觸媒將銅離子形成銅層）— 2〇 三階段水洗->乾燥 表一 實施例1 實施例2 比較例1 剝離強度 6.8 kgf/cm 1.0 kgf/cm 0.5 kgf/cm 21 20090625920 A FCBGA was fabricated in the same manner as in Example 1, except that ion beam sputtering was used instead of DC sputtering in Stage A. The peel strength of the build-up printed circuit board is thus manufactured, and the surface roughness of the insulating material is measured. The results are shown in Table 1 below. 25 Comparative Example 1 20 200906259 An FCBGA was produced in the same manner as in Example 1, except that in Stage A, ion beam surface treatment and DC splash deposition were omitted, and the general wet process as described below was used to include drilling. Electroless plating of dirt and copper forms a copper seed layer. 5 The peel strength of the build-up printed circuit board is thus manufactured, and the surface roughness of the insulating material is measured. The results are shown in Table 1 below. ※ Go to the wrong pollution (the function of softener, the best residue is at pH 1 〇~12, that is, as a smudge stain)-> Three-stage water washing 4 permanganic acid treatment (removal of main 〇 Staining and roughening the surface of the resin)-> One-stage water washing-> Two-stage water washing-Neutralization (removing manganese dioxide residue)_> Three-stage water washing-drying ※Electroless electroplating copper cleaning (is an alkaline chemical cleaning) Process, which is for high peel strength and conditions for palladium adsorption) - three-stage water wash - etching cleaning (to remove the oxide layer of steel and to roughen the peel strength between copper layers) - two-stage water washing -> ; pre-dip (removal of persulfate residue and as a pre-activator) - activator (palladium ion (non-gel state) adsorption) - > three-stage water wash - > reduction (Reducing palladium ions to palladium as a catalyst) -> Three-stage water washing-> Chemical copper (forming a copper layer with copper ions using a palladium catalyst) - 2〇 three-stage water washing -> Drying Table 1 Example 1 Example 2 Comparative Example 1 Peel strength 6.8 kgf/cm 1.0 kgf /cm 0.5 kgf/cm 21 200906259
如表一所示，在使用一般濕式製程所製造之積層基材 的例子中（比較例1)，剝離強度約為〇·5 kgf/cm及表面粗糙 度為1_0 (m，其能夠形成之間距為36 (m(線/間距=18/18 5 (m)。然而，在使用根據本發明之乾式製程所製造之積層基 材的例子中（實施例1和2)，剝離強度約為〇 9 kgf/cm且表面 粗縫度相對較小’在0.9 (m範圍。因此，可以實現具有間 距20 (m(線/間距=1〇/1〇 (m)的精細電路以及可得到較快的 sfl戒傳输速率。 10 雖然關於本發明之製造增層式印刷電路板的方法之較 佳實施例，以為了說明而揭露。本技術領域之人士可在不 背離本發明之技術精神下，是可能進行不同的修改、附加 及取代。 如前所述，本發明提供一種製造增層式印刷電路板之 15 方法。根據本發明，一具有金屬層層壓於兩表面之樹脂基 材’其被完全蝕刻而露出適合實現高剝離強度之表面粗糙 度，而不需另外的表面處理，之後，藉由SAP形成核心層 之金屬電路層，所提供之金屬種子層係經由一乾式製程而 形成，包括離子束表面處理及真空沈積，其代替了包括濕 20式蝕刻及無電電鍍之—般濕式製程，因此增加了材料的剝 離強度。 再者’在使用一般無電電鍍製程形成金屬種子層的製 程中’因所形成之層是相對厚的，大約在3 μιη的範圍，在 22 200906259 =後的金屬種子層的移除製程中，其快速蝕刻所需的時間 會增加，且可能發生底切（undercutting)的問題。然而，在 本發明中’、經由離子束表面處理及真空沈積，形成較薄的 金屬種子層’因此減少製程時間而有高生產性。同時，可 5以克服底切的問題。因此，實現具有高密度之精細電路是 可能的。 再者，以離子束表面處理及真空沈積取代一般濕式表 面處理及無電電鍍，並因此提升對金屬的剝離強度（> 〇.8 Kgf/cm) ’因此以一對環境友善的方法，使得實現具有間距 10 不大於40 (線/間距=20/20 μιη)的精細電路是可能的。 此外’因為為了基材與金屬電路層之間_的高剝離強 度’積層基材的核心層也是藉由SAP形成，積層基材中的 所有層別經由SAP製造，並因此可確保高可靠性之精細電 路。 15 在本發明範圍内之修改、附加及取代是落入如附揭露 之申請專利範圍中。 【圖式簡單說明】 圖1A及1B係根據第一習知技術，分別地顯示形成增 20 層式印刷電路板之核心層及外部層之製程流程圖。 圖2A至2G係根據第一習知技術，接續地顯示形成增 層式印刷電路板之核心層之製程剖面圊。 圖3A至3F係根據第一習知技術，接續地顯示形成增 層式印刷電路板之外部層之製程剖面圖。 23 200906259 圖4A及43係根據第二習知技術，分別地顯示形成增 層式印刷電路板之心層及外部層之製程流程圖。 圖5 A至5G係根據第二習知技術，接續地顯示形成增 層式印刷電路板之核心層之製程剖面圖。 .圖6A至6F係根據第二習知技術，接續地顯示形成增 層式印刷電路板之外部層之製程剖面圖。 圖7係顯示習知FCBGA印刷電路板結構之剖面示意 圖。 ( 圖8人及8B係根據本發明，分別地顯示形成增層式印 10刷電路板之核心層及外部層之製程流程圖。 圖9A至9H係根據本發明，接績地顯示形成增層式印 刷電路板之核心層之製程剖面圖。 圖10A至10F係.接續地顯示於圖9H之核心層上形成第 一外部層之製程剖面圖。 15 圖11係接續地顯示於圖10F之第一外部層上形成第二 外部層而製造之FCBGA印刷電路板之結構剖面圖。 G 圖12係根據本發明’顯示印刷電路板之離子束表面處 理之示意圖。 20 【主要元件符號說明】 11樹脂基材 12金屬層 13貫穿孔 Η無電電鍍金屬層 15金屬電鍍層 16導電膏 17乾膜 21樹脂基材 22金屬層 24 200906259 23盲孔 27金屬圖案電鍍層 33貫穿孔 36導電膏 42金屬層 45乾膜 52a,52b電路圖案 55a,55b電路圖案 59a, 59b 開口 63貫穿孔 66金屬圖案電鍍層 72盲孔 75乾膜 83通孔 86&,861)第三樹脂基材87&，871)第三電路層 89a，89b 開口 24無電電鍍金屬層 31樹脂基材 34無電電鍍金屬層 3 7乾膜 43盲孔 46金屬圖案電鍍層 53通孔 56a, 56b樹脂基材 61樹脂基材 64金屬離子層 67導電膏 73金屬種子層 81第一樹脂基材 84a,84b第二樹脂基材 26乾膜 32金屬層 35金屬電鍍層 41樹脂基材 44無電電鍍金屬層 5 1樹脂基材 54a，54b樹脂基材 57a，57b電路圖案 6_2金屬層 65乾膜 71樹脂基材 74乾膜 82a，82b第一電路層 85a，85b第二電路層 88a，88b防焊阻層As shown in Table 1, in the example of the laminated substrate produced by the general wet process (Comparative Example 1), the peel strength was about 〇·5 kgf/cm and the surface roughness was 1_0 (m, which was able to form The pitch is 36 (m/line = 18/18 5 (m). However, in the example of the laminated substrate manufactured by the dry process according to the present invention (Examples 1 and 2), the peel strength is about 〇. 9 kgf/cm and the surface roughness is relatively small 'in the range of 0.9 (m. Therefore, a fine circuit with a pitch of 20 (m/line = 1 〇 / 1 〇 (m) can be realized and can be obtained faster) Sfl ring transmission rate. 10 Although a preferred embodiment of the method for fabricating a build-up printed circuit board of the present invention is disclosed for the purpose of explanation, those skilled in the art can without departing from the technical spirit of the present invention. Different modifications, additions and substitutions are possible. As described above, the present invention provides a method of manufacturing a build-up printed circuit board. According to the present invention, a resin substrate having a metal layer laminated on both surfaces is Completely etched to expose surface roughness suitable for achieving high peel strength Without additional surface treatment, the metal circuit layer of the core layer is formed by SAP, and the metal seed layer is formed through a dry process, including ion beam surface treatment and vacuum deposition, which replaces the wet 20 Etching and electroless plating, the wet process, thus increasing the peel strength of the material. In addition, in the process of forming a metal seed layer using a general electroless plating process, the layer formed is relatively thick, about 3 In the range of μιη, in the removal process of the metal seed layer after 22 200906259 =, the time required for rapid etching may increase, and undercutting may occur. However, in the present invention, Beam surface treatment and vacuum deposition form a thin metal seed layer', thus reducing process time and high productivity. At the same time, it can overcome the problem of undercut. Therefore, it is possible to realize a fine circuit with high density. Replacing general wet surface treatment and electroless plating with ion beam surface treatment and vacuum deposition, and thus enhancing the peeling of the metal (> K.8 Kgf/cm) 'So it is possible to implement a fine circuit with a pitch of 10 not more than 40 (line/pitch = 20/20 μηη) in a pair of environmentally friendly methods. The high peel strength between the material and the metal circuit layer' is also formed by SAP, and all layers in the laminated substrate are manufactured via SAP, and thus a high-reliability fine circuit can be ensured. Modifications, additions and substitutions within the scope of the invention are within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B show the formation of a 20-layer printed circuit, respectively, according to a first prior art technique. Process flow chart of the core layer and the outer layer of the board. 2A to 2G are successively showing a process profile 形成 for forming a core layer of a build-up printed circuit board according to a first conventional technique. 3A through 3F are process cross-sectional views showing the formation of an outer layer of a build-up printed circuit board in accordance with a first conventional technique. 23 200906259 Figures 4A and 43 are flow diagrams showing the process of forming a core layer and an outer layer of a build-up printed circuit board, respectively, according to a second prior art technique. Figures 5A through 5G are cross-sectional views showing the process of forming a core layer of a build-up printed circuit board in accordance with a second conventional technique. Figures 6A through 6F are cross-sectional views showing the process of forming an outer layer of a build-up printed circuit board in accordance with a second conventional technique. Fig. 7 is a schematic cross-sectional view showing the structure of a conventional FCBGA printed circuit board. (Fig. 8 and 8B are respectively a flow chart showing the process of forming the core layer and the outer layer of the build-up printed circuit board according to the present invention. Figures 9A to 9H show the formation of the build-up layer according to the present invention. FIG. 10A to FIG. 10F are cross-sectional views showing the process of forming the first outer layer successively on the core layer of FIG. 9H. 15 FIG. 11 is successively shown in FIG. A cross-sectional view of a structure of an FCBGA printed circuit board fabricated by forming a second outer layer on an outer layer. Fig. 12 is a schematic view showing the surface treatment of an ion beam of a printed circuit board according to the present invention. 20 [Description of main components] 11 Resin Substrate 12 metal layer 13 through hole Η electroless plating metal layer 15 metal plating layer 16 conductive paste 17 dry film 21 resin substrate 22 metal layer 24 200906259 23 blind hole 27 metal pattern plating layer 33 through hole 36 conductive paste 42 metal layer 45 Dry film 52a, 52b circuit pattern 55a, 55b circuit pattern 59a, 59b opening 63 through hole 66 metal pattern plating layer 72 blind hole 75 dry film 83 through hole 86 & 861) third resin substrate 87 & 871) third Circuit layer 89a, 8 9b opening 24 electroless plating metal layer 31 resin substrate 34 electroless plating metal layer 3 7 dry film 43 blind hole 46 metal pattern plating layer 53 through hole 56a, 56b resin substrate 61 resin substrate 64 metal ion layer 67 conductive paste 73 metal Seed layer 81 first resin substrate 84a, 84b second resin substrate 26 dry film 32 metal layer 35 metal plating layer 41 resin substrate 44 electroless plating metal layer 5 1 resin substrate 54a, 54b resin substrate 57a, 57b circuit Pattern 6_2 metal layer 65 dry film 71 resin substrate 74 dry film 82a, 82b first circuit layer 85a, 85b second circuit layer 88a, 88b solder resist layer
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