九、發明說明： 【發明所屬之技術領域】 本發明係關於一種增層式印刷電路板（build-up PCB) 之製造方法，更明確的說，為一種增層式印刷電路板之製 5 造方法，其中增層式印刷電路板之核心電路層是經由一乾 式的金屬種子層形成製程而形成，其包括離子束表面處理 以及真空沈積，因此以一種對環境友善的方法，實現一高 可靠度之精細電路。 10 【先前技術】 目前，增廣式印刷電路板使用減去法製程（subtractive process)、改良之半-加成製程（MSAP，modified semi-additive process)、以及半-加成製程（SAP， semi-additive process) 0 15 詳細來說，減去法製程是應用於高密度互相連接 (HDI，high density interconnection)產品，並且減去法製程 及MSAP應用於超薄晶片尺寸封裝（UT-CSP，ultra thin-chip scale package)以及球型陣列（BGA，ball grid array)之產 品。再者，在覆晶球型陣列（FCBGA，flip chip BGA)的例子 20 中，核心層及建構的外部層（包括2F2B/3F3B)是分別以減去 法製程及SAP而形成，此外，一種子層經由無電電鍍而形 成，因此實現一精細電路。 關於上述，根據一第一習知技術，圖1A及1B分別顯示 形成一增層式印刷電路板之核心層及外部層的製程。 5 參見圖1A及圖2A至2G，根據此第一習知技術，使用 減去法製程形成增層式印刷電路板之核心層的方法，詳述 於下文中。 首先，一樹脂基材11，其具有金屬層12層壓其兩表面， 進行典型的蝕刻及鑽孔而形成一貫穿孔13(圖2Α及2Β)。接 著’具有貫穿孔13之基材的表面進行去鑽污（desmearing) 後接著以無電電鍍而形成一無電電鍍金屬層14(圖2C)。經 由電鍍，形成一金屬電鍍層15(圖2D)。填充一導電膏 16(〇〇11(111<^乂6?玨316)於貫穿孔13中（圖2£)，之後，相對應於 一電路圖案之預定區域上形成乾膜17,並覆蓋貫穿孔13(圖 2F)。金屬層之不必要部分經由一典型之曝光/顯影及蝕刻 而移除’然後移除乾膜17，因此完成核心電路層（core circuit layer)的程序（圖2G)。在進行外部層之形成製程之 前’此基材進行典型的表面處理，例如習知技術之CZ處 理’然後在其上層壓一絕緣層（圖未示 此外，參見圖1B及圖3A至3F，根據第一習知技術所使 用之MSAP形成增層式印刷電路板外部層的製程，將詳述 如後。為方便起見，省略核心層之建構製程的敘述，只有 敘述外部層之形成製程， 首先，一具有金屬層22層壓於其兩表面之樹脂基材21 進行半-蝕刻（half-etched)，然後進行典型的蝕刻及鑽孔而 形成盲孔23(圖3 A及3B)〇之後，具有盲孔23之基材的表面 進行去鑽污及無電電鍍而形成無電電鍍金屬層24(圖3C)。 之後’在一相對應於電路圖案以外之預定區域（包括盲孔23) 1342179 後β為方便起見，省略核心層之建構製程的敘述，只有敘 述外部層之形成製程。 首先’ 一具有金屬層42層壓於其兩表面之樹脂基材 41 ’ 例如厚度約為 35 μπι之 ABF(Ajinomoto Build-Film)，進 5 行典型的蝕刻及鑽孔而形成具有75μιη直徑之盲孔43(圖6A 及6Β)。之後，具有盲孔43之基材表面進行去鑽污及無電 電鍵’因此形成厚度約為1±〇· 3 μιη之無電電鑛金屬層44(圖 6C)。之後，在一相對應於電路圖案以外之預定區域（包括 盲孔43)形成乾骐45(圖6D)。使用乾膜為阻層，經由電鍍形 10 成金屬圖案電鍵層46(圖6E)。之後，移除乾膜45，然後金 屬層之非必要部分藉由快速餘刻而移除，因此完成圖案化 之製程（圖6F)。 據此，根據產品之種類，樹脂基材之材料例子包括環 氧樹脂’例如 FR-4、BT (Bismaleimide Triazine)、ABF等。 15 舉例來說’經由減去法製程及MSAP而生產之BGA及 UT-CSP的例子中，其包括有一 BT絕緣材料，此材料之表 面輪廓（surface profile)至少1 μπι，且在減去法製程令，很 難實現具有間距不超過80 μπι(線寬/間距=40/40 μπι)的細 電路。在MS ΑΡ中，因為由於半-蝕刻所衍生之金屬層厚度 20 變化，可以得到具有間距約50 μπι(線寬/間距=25/25 μιη) 數量級之精細電路》 在FCBGA產品之群組中，核心層一般是使用FR_4樹脂 基材經由一減去法製程形成而實現一具有間距約為1〇〇 ㈣(線寬/間距=50/50 μιη)之電路，並且所建構之外部層是 8 1342179 使用ABF樹脂基材經由SAP而得到一具有間距36 μιη(線寬/ 間距=1 8/18 μιη)之精細電路。然而，據此，很難實現精細 電路之核心層，這可歸責於樹脂基材之表面粗糙度及減去 法製程本身的限制。 5 再者，在FCBGA產品之群組中，其中多層基材是使用 ABF絕緣材料經由SAP而製造，如圖7所示，減去法製程應 用於核心層（由第1〜第2層52a、52b所構成），以及應用SAP 於外部層（由第3〜第6層55a、55b、57a、57b所構成）。更明 痛的說，為了形成電路，外部層之形成製程，係重複兩次 10 之包括無電電锻形成厚度約1〜3 μιη之種子層、電鐘、去光 阻、以及快速蝕刻。因此’通孔53及電路圖案52a、52b、 55a、55b、57a、57b是形成於樹脂基材51、54a、54b、56a、 56b中。接著，形成一防焊層（s〇]der resist)並且形成防焊層 之開口部59a，59b。所以，完成一具有總共6層的FCBGA。 15 然而’使用昂貴之ABF材料造成製程成本增加及高的 產品價格。在應用SAP的例子中，ABF材料的表面輪廓 (surface profile)至少是1 μιη，導致大的表面粗糙度及36μιη 之間距（線寬/間距= 18/18 μηι)。此外，經由濕式表面處理 及無電化學電鍍實現一精細電路是有其限制。 20 關於印刷電路板之輕薄短小的需求，很多製造商嘗試 開發絕緣材料以實現精細電路以及展示以增加電路之訊 號傳輸速率為目標之高功能性。根據上述之發展趨勢，將 增加輸入及輸出訊號的數目，因此，需要高可靠度的精細 電路。然而，習知的SAP遭受因為金屬種子層是經由包括 9 1342179 濕式表面處理及無電電鍍之濕式製程而形成，不合意地增 加了表面粗糙度，而使得無法實現一精細電路。同時產生 大量的廢棄物，而衍生環境的問題。 5 【發明内容】 本發明是經由密集與大量之增層式印刷電路板製程研 究而得到’本案發明人致力於避免習知技術所面臨的問 題，而發現本發明，當形成增層式印刷電路板之核心層 時’一具金屬層層壓於其兩表面之樹脂基材，其金屬層被 10 完全姓刻，因此獲得一適合實現高剝離強度之表面粗糙 度，然後經由SAP形成電路層以取代一般的減去法製程， 藉由包括離子束表面處理及真空沈積之乾式製程形成金 屬種子層’並沒有使用包括濕式蝕刻及無電電鍍之一般的 濕式製程，因此以一對環境友善之方式製造一具有高可靠 15 度精細電路的增層式印刷電路板。 因此，本發明之一目的係提供一製造增層式印刷電路 板之方法’其中’包括有核心層及外部層之增層式印刷電 路板之所有電路層可經由SAP而製造’因此實現一精細電 路〇 20 本發明之另一目的係提供一製造增層式印刷電路板之 方法’其中之金屬種子層係經由乾式製程而形成，而不經 由濕式製程，因此以一對環境友善及經濟的方式實現一電 路層。 本發明之再一目的係提供一製造增層式印刷電路板之 10 方法’其中樹脂基材與金屬層之間的剝離強度可以增加， 因此實現一高可靠度之精細電路。 為達上述之目的，本發明提供一製造包括有一核心層 及外部層之增層式印刷電路板之方法，製造該核心層包 括以下步驟：（a)提供―第—樹脂基材，其具有金屬層層壓 於其兩表面；（b)由該第-樹脂基材之該兩表面移除該些金 屬層’(c)於不具金屬層之該第—樹脂基材中形成一作為層 間電性連接之貫穿孔；⑷使用離子束，將具有貫穿孔之該 第樹月曰基材進行表面處理；⑷使用真空沈積，形成一第 金屬種子層於已進行表面處理之該第—樹脂基材；⑴使 用電鍍：形成一第一金屬圖案電鍍層於具有該第一金屬種 子層之該基材上；（g)移除不具有第一金屬圖案電鍍層部分 之第金屬種子層；以及⑻填充導電膏於該貫穿孔，因此 形成一核心電路層。 /尤本發明而論’該使甩離子束之表面處理較佳為於惰 ，氣體存在下進行’該惰性氣體係選自下列群組，包括: 氬氧、氮 '氣、四氟化碳、氫、氖、氣以及上述之混合 物。 該真空沈積可以使用濺鍍（sputtering)'熱蒸發（thermal evaporation)或電子束沈積（e beam ^ρ〇3^〇)進行。 該第一金屬種子之厚度較佳為介於〇 〇2〜4 μιη，更加為 介於0.02〜lpm。 t再者，該外部層係以下列步驟製造：⑴層壓一第二樹 月曰基材於該核心電路層上；⑴於該第二樹脂基材中形成作 1342179 為層間電性連接之盲孔；（k)使用無電電鍍，形成第二金屬 種子層於具有該盲孔之該第二樹脂基材上；⑴使用電鍍， 形成第二金屬圖案電鍍層於具有該第二金屬種子層之該 基材上；以及（m)移除不具有該第二金屬圖案電鍍層部分之 5 該第二金屬種子層。 該第一樹脂基材以及該第二樹脂基材，其可為相互相 同或不同，其可包括環氧樹脂或氟樹脂。 同時，此金屬較佳為銅。 【實施方式】 以下，將配合附圖詳細敘述本發明。 如上所述，傳統上製備增層式印刷電路板（build-up PCB)之核心層（core layer) ’係利用一減去法製程 (subtractive process) ’實現一電路在一樹脂基材上，其具 15 有金屬層層壓於此基材之兩表面，應用乾膜、曝光、顯影 以及濕式蝕刻，然而，這樣很難得到一間距不大於80 μιη(線 /寬=40/40 μιη)之電路線寬。此外，為緩和這種係間距圖案 之問題，SAP被認為是有效的形成一電路之方法，其為將 基材進行通孔加工、去鑽污（desmearing)、以無電電鍵 2〇 (electroless plating)形成一金屬種子層、電鍍、然後快速蝕 刻。然而’如果應用SAP經由一包括無電電錄及電鍍之典 型濕式製程而形成電路層，樹脂基材與金屬層之間充足的 剝離強度（peel strength)是不能確定的，並且它很難實現一 細間距電路。 12 1342179 在本發明中，為克服上述問題’當藉由SAP製備核心 層（core layer)時，層壓於核心層樹脂基材之兩表面的金屬 層被完全蝕刻，因此露出的表面粗糙度適合於實現高的剝 離強度，之後，以乾式製程形成一金屬種子層，包括離子 5 束表面處理以及真空沈積，以代替一般的濕式製程，包括 去錢污（desmearing)以及無電電鍵。因此’經由對環境友善 的SAP，金屬上的剝離強度（> 〇·8 Kgf/cm)可以增加，最後 使實現具有高密度之細間距電路成為可能。更進一步，在 增層的外部層中（outer layer)，是使用一般濕式的去鑽污、 10 無電電鍍、及電鍍而形成電路層。以這種方法，因為SAP 可以應用於增層式印刷電路板的所有層別，所以可以得到 一具有高密度的細間距電路。 根據本發明，圖8A及8B分別圖示形成增層式印刷電路 板之核心層及外部層之製程流程圖。 15 參閱圖8A及圖9A至9H，以下詳細說明根據本發明形 成增層式印刷電路板之核心層之製程。 首先’準備一作為PCB之樹脂基材61，其由環氧樹脂 (epoxy resin)或是氟樹脂（fluorine resin)所形成，且具有金 屬層62層壓於此基材之兩表面·»關於此金屬，任何導電金 20 屬均可使用，只要它是適合形成電路的。基於經濟利益之 考量’銅為特別有用處的》 然後’經由一全面姓刻製程，金屬層62由樹脂基材61 之兩表面移除。因此，既使沒有額外的表面處理，此基材 露出適合實現高剝離強度之表面粗糙度（圖9B)。 13 (S ) 1342179 接著’於樹脂基材61形成作為内層電性連接之内部通 孔（inner via holes)的一或多個貫穿孔63(圖9C)，並且具有 貫穿孔63之基材的表面以離子束處理。 較佳地，離子束表面處理程序可在離子劑量（i〇n dose) 5 為1E15〜lE19(ions/cm2)及加速電壓為0.5〜20keV下進行， 其中提供惰性氣體係選自下列群組，包括Ar、〇2、N2、Xe、 CF4、Η:、Ne、Kr以及上述之混合物，但是本發明並不侷 限於上述之條件。根據基材物質的種類，可以適當地設定 •真實的製程條件’其對本技術領域之人而言是顯而易見 10 的。 經由這樣乾式離子束表面處理程序，樹脂基材對接續 要形成金屬種子層的剝離強度可以增加。亦即，如圖丨2所 示，樹脂基材之高分子材料之表面藉由具有可形成不穩定 連接之能量的惰性或反應性離子而被激發，其可以與反應 15 氣體（例如氧氣）進行化學反應’因此’基材之疏水性表面 轉變成親水性，因此增加材料的剝離強度。所以，實現細 間距電路是可能的。 i 在經過離子束表面處理之基材61上，以真空沈積 (vacuum deposition)形成一金屬離子層64至所要求的厚度 .20 (圖 9D)。 - 真空沈積製程舉例可為減鍵（sputtering)、熱蒸發 (thermal evaporation)、或電子束沈積（e-beam deposition)， 但並非受限於此，只要為該技術所習知的方法均可。 金屬種子層可形成0.02〜4 μιη之厚度，較佳為〇.〇2〜1 14 1342179 μηι’更加為〇·()2〜〇 5特別是，由真空沈積所得之金 子層可以選擇性的形成比使用一般濕式無電電鑛所 形成之金屬種子層（2〜3㈣更薄的厚度，因此後續快速银 . _程所需之工作時間可以減少、生產性得以提升，並且 5可以避免形成底切（undercutting)，因此得到具有高密声之 #細核心電路導線，，一乾式真空沈積製程，其可以 取代-般濕式無電電鍵製程，並可作為形成金屬種子層， 且因為不會產生廢液，所以被認為是對環境友善的。 # #著，如習知技術，作為一電鑛阻層之乾膜65形成於 10預定區域’其為圖案電鑛區域以外（圖9E)，之後電鍵一 電鍵金屬圖案以及移除乾膜65，因此，形成一金屬圖^電 鍍層66(圖9F)。 不具圖案電鑛層66之金屬種子層64藉由典型的快速钱 刻而移除（圖9G) ’並且具有圖案電鑛層66之貫穿子㈤以習 15知的導電膏67填充其中，因此完成-核心電路層（圖9H)。 參見圖8B及圖l〇A至1〇F，根據本發明，於增層式印刷 • 電路板之核心層上建構外部層之製程將敘述於下文》 圖9H之核心電路層進行典型的表面處理，例如cz處理 (CZ81GG，可由鹏得到），以增加電路層的表面粗糙度用 20以確保材料對樹脂基材之剝離強度，之後一由環氧樹脂或 氟樹脂所形成之基材71(可與核心層相同或不同）被層壓在 其上方（圖10A)。 接著，作為層間電性連接之盲孔72形成於樹脂基材71 中（圖10B)〇經由進行去鑽污製程、無電電鍍之典型的表面 15 1342179 處理’因此得到厚度約2〜3 μιη之金屬種子層73(圖i〇c)。 接著，乾膜74形成於一預定區域’其為對應於包含盲 孔72之一電路圖案區域之外（圖1〇D)e使用乾膜為一阻層， 經由電鍵形成一金屬圖案電鑛層75(圖1〇E)。 5 接著，移除乾膜74，並且經由典型的快速蝕刻將不具 有金屬圖案電鍍層75之金屬種子層73的部分移除，因此完 成一外部電路層（圖10F)。 選擇性地，如圖10A至1 OF所示之SAP可以被重複兩次 以形成一第二層至第六層。此外，當FCBGA之最外層被應 10 用，一防焊阻層被形成，經由一典型的防焊阻層開口製程 而形成防焊阻層之開口部分，然後藉由鎳/金的無電電鍍形 成一凸塊，如典型的習知技術。 所製造之具有6層的FCBGA如圖11所示。 如圖11所示，提供了包括第一電路層82a、82b及通孔 15 83之第一樹脂基材81為核心層，並且提供了包括盲孔及第 二電路層85a、85b之第二樹脂基材84a、84b以及包括盲孔 及第二電路層87a、87b之第三樹脂基材86a、86b為外部層。 此外，提供了防焊阻層88a、88b為最外層，並且經由一預 定的開口製程形成防焊阻層之開口部分89a、89b。 20 根據增層式印刷電路板之最後使用，外部層建構製程 可以重複數次，並且可以進一步進行一隨後之預設製程。 所製造之增層式印刷電路板可應用HDI、UT-CSP、 BGA、FCBG等等’且可以無限制的應用到實現細間距電 路之所有產品。 1342179 根據本發明之製造增層式印刷電路板的製程，因為具 有金屬層層壓於其兩表面之樹脂基材被使用成核心層的 基材之狀態是其中的金屬層被移除，此樹脂基材可以露出 適當之表面粗糙度（Ra<0.8 μπι)而實現高的剝離強度而不 5 需另外的表面處理。再者，基材表面之粗糙被使用離子束 處理，因此增加對金屬的剝離強度（>〇.8 Kgf/cm)，造成細 間距電路的實現。此外’利用乾式製程形成金屬種子層而 取代一般的濕式製程，所以細間距電路之核心層可以最小 的表面粗糙度（Ra < 0.8 μηι)而實現，經由一對環境友善的 1〇 製程方式。再者，增層式印刷電路板的所有層，包括核心 層及外部層’可以進行SAP而形成電路。因此，實現—具 有高密度、高可靠度之細間距電路是可能的。 本發明之一較佳理解可由以下的實施例得到，其為說 明而敘述’而不是被解釋成限制本發明。 15 實施例1 A.—具有銅薄膜層壓於其兩表面之fr_4 CCL(覆蓋 銅，copper clad laminate)，使用FeCl2蝕刻劑為將其完全蝕 刻’因此移除兩層銅薄膜。不具有銅薄膜之FR-4基材使用 20 CNC (電腦數位控制）鑽頭進行機械鑽孔，以形成具有直徑 約100〜300 μηι的通孔，然後使用氮氣在約i KeV的加速電 壓’以及1E15的離子劑量（ion dose)下進行離子束表面處 理。之後，在經處理基材的表面上，使用直流濺鍍沈積厚 度約為0.3 μιη的鋼種子層，接著，在一預定空氣流動體積 17 1342179 (0.05〜0.15 m3/min)，溫度（20〜25°C)，以及電流密度 (F/B1.5ASD)的條件下，藉由以H2S04 (120〜160 gm)、Cu (20〜40 g/1)、Cl· (20〜50 ppm)、以及 cupracid HL平坦劑 (5〜15 ml/1)的銅圖案電鍍形成厚度約為l〇〜20 μιη之銅圖案 5 電鍍層，之後藉由快速蝕刻（蝕刻速度2 m/min，使用 H2S04/H202蝕刻劑）移除銅種子層《最後，在黏度為3.0 pa.s，預熱處理為80oC/60 min以及固化為160oC/60min的條 件下，以銅膏填充於通孔中，因此完成一核心電路層。 B.所得到的核心電路層進行CZ處理（CZ8100，可由 10 MEC得到）以增加銅的表面粗糙度而確保對基材材料的剝 離強度。使用主要的真空壓合設備，在條件為溫度100。(：、 真空時間30秒、壓力7 kgf/cm2，以及按壓時間60秒，於核 心電路層上暫時性地熔接ABF，然後使用二級熱壓，在條 件為溫度100°C、壓力10kgf/cm2，以及按壓時間90秒下層 15 壓。接著使用二氧化碳雷射形成直徑約為70 μιη的盲孔， 以及在彰淵製程中使用高猛酸（permanganic acid)，污斑於 pHIO 〜12因澎湖而被移除（〇114+12]^11〇4-+140丨4〇032-+ 12Μη042·+ 9H20 + 02)，因此形成預定的表面粗糙度。 隨後，經由中和（neutralization)而移除二氧化猛（manganese 20 dioxide)殘餘物（CH4 + 12Μη〇4· + 140H_ -> C032- + 12Μη042·+ 9H20 + 02)，進行去鑽污處理，以及在CuS04 + 2HCHO + 4NaOH Cu + 2HC〇2Na + H2 + 2H2O + Na2S〇4 的狀態下進行銅的無電電鍍（Atotech)，因此形成厚度約3 μπι的銅種子層。接著，藉由銅圖案電鍵（Evara)，以H2S04 18 1342179 • (120〜160 g1，1)、Cu (20〜40 g/l)、Cl- (20〜50 ppm)、及 cupracid HL平坦劑（5〜15 ml/1)，在條件為預設空氣流量體積為 0·05〜0.15 m3/min、溫度20〜25°C及電流密度為 • F/B1，5ASD、形成厚度約為15 μηι的銅圖案電鍵層，之後， 5使用H2S〇4/H2〇2為蝕刻劑，經由蝕刻速率為2 m/min之快速 蝕刻移除銅種子層。 C.在B中所得到的基材進行兩次的建構製程（build-up process) ’其與B的製程相同而形成包括第三層到第六層的 ® 外邻層。在條件為滾輪高度（roll pitch) : 370 μηι、350 μπι 10 及 32〇 ，滾軸下壓（roll press) ’ 刮條下壓（(1〇(^〇1· bar press) ’滾軸速度：丨2〜1,6 m/min，以及乾燥溫度/時間： 78 C ± 2°C，形成防焊阻層，然後在第一停滯時間為3〇秒 及第二停滞時間為3〇秒下預烤，所以溶劑由油墨中移除， 並且所形成之油墨的表面是部分硬化（cured)及乾燥的，因 15此適合於曝光製程。在曝光製程中，UV光以光強度為 700〜900 mJ/cm2照射於所形成之油墨的表面，並且經由一 • 工作膜（working film)/玻璃光罩誘發油墨的光硬化反應 (photocuring)，使得油墨可以在顯影液中作為阻抗的功 , 忐。在顯影製程中，油墨之光硬化部分於碳酸鈉（Na2C03 20 ι%)中可作為阻抗，反之，沒有光硬化部分被溶解及移除》 • 所使用1%碳酸鈉水溶液（1°/。sodium carbonate)之條件為： 碳酸納濃度 11 ± 1·〇 g/1(SPEC: 1〇 5 ± 2 〇 g/1)，碳酸鈉pH 值10.0〜12.5 ’碳酸納溫度3〇 ± 3〇c，顯影壓力，以及顯影 速度，並且進行紫外光硬化（UV curing)(被顯影之油墨的表 1342179 面是經過進一步的光硬化，所以不完全的光反應因紫外光 曝光而被另外誘發’以增加SR的性質）。為了改善後硬化 (post-cured)(完全乾燥）之油墨與銅之間的剝離強度，以及 增加油墨的硬度’油墨中硬化試劑（curing agent)之雙鍵被 5 活化’並且所有硬化試劑中的樹脂於後硬化製程 (post-cudng process)中開始反應而產生完整的高分子。其 條件為溫度/時間：120oC/30 min及150oC/60 min，對應於凸 塊之電路圖案的部分，經由防焊層之開口而露出，隨後在 條件為蝴酸：22〜38 g/1，pH : 3.5〜4.5 .，氣基項酸鎳（nickel 10 sulfamate): 400〜500 g/卜氣化鎳：8〜16 g/卜 Fe : 200ppm或 以下’ Cu : 200 ppm或以下，以及溫度：45~55。(：，進行鎳 的無電電鍍，然後在條件為Au: 5.5〜7.5 g/卜pH: 6.1〜6.4， 比重：1.09〜1.24，Fe: 50 ppm或以下，Cu: 18 ppm 或以下， Ni: 350 ppm或以下，Zn: 5 ppm或以下，T1:. 5〜15 ppm，以 15 及溫度：65〜75°C，進行金的無電電鍍，因此製造FCBGA。 增層式印刷電路板的剝離強度因此被製造出，並且量 測絕緣材料的表面粗糙度。其結果顯示於以下表1中。 實施例2IX. Description of the Invention: [Technical Field] The present invention relates to a method for manufacturing a build-up PCB, and more specifically to a build-up printed circuit board. The method wherein the core circuit layer of the build-up printed circuit board is formed by a dry metal seed layer forming process including ion beam surface treatment and vacuum deposition, thereby achieving a high reliability in an environmentally friendly manner Fine circuit. 10 [Prior Art] At present, augmented printed circuit boards use a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP, semi -additive process) 0 15 In detail, the subtraction process is applied to high-density interconnect (HDI) products, and the subtraction process and MSAP are applied to ultra-thin wafer size packages (UT-CSP, ultra Thin-chip scale package) and products of ball grid array (BGA). Furthermore, in the example 20 of the flip chip BGA, the core layer and the constructed outer layer (including 2F2B/3F3B) are formed by subtracting the process and SAP, respectively. The layer is formed by electroless plating, thus realizing a fine circuit. Regarding the above, according to a first conventional technique, Figs. 1A and 1B respectively show a process of forming a core layer and an outer layer of a build-up printed circuit board. 5 Referring to Fig. 1A and Figs. 2A to 2G, a method of forming a core layer of a build-up printed circuit board using a subtractive process according to this first conventional technique is described in detail below. First, a resin substrate 11 having a metal layer 12 laminated on both surfaces is subjected to typical etching and drilling to form a uniform perforation 13 (Figs. 2 and 2). Next, the surface of the substrate having the through holes 13 is subjected to desmearing, followed by electroless plating to form an electroless plated metal layer 14 (Fig. 2C). A metal plating layer 15 is formed by electroplating (Fig. 2D). Filling a conductive paste 16 (〇〇11 (111 < ^ 乂 6 玨 316) in the through hole 13 (Fig. 2), and then forming a dry film 17 corresponding to a predetermined area of a circuit pattern, and covering the through Hole 13 (Fig. 2F). Unnecessary portions of the metal layer are removed via a typical exposure/development and etching' and then the dry film 17 is removed, thus completing the core circuit layer procedure (Fig. 2G). The substrate is subjected to a typical surface treatment, such as the CZ treatment of the prior art, prior to the formation of the outer layer, and then an insulating layer is laminated thereon (not shown, see FIG. 1B and FIGS. 3A to 3F, The process of forming the outer layer of the build-up printed circuit board by the MSAP used in the first prior art will be described in detail later. For the sake of convenience, the description of the construction process of the core layer is omitted, and only the formation process of the outer layer is described. After a resin substrate 21 having a metal layer 22 laminated on both surfaces thereof is half-etched, and then subjected to typical etching and drilling to form blind vias 23 (Figs. 3A and 3B), Surface of the substrate with blind holes 23 for de-staining and without Electroplating forms an electroless plated metal layer 24 (Fig. 3C). After 'after a predetermined area (including the blind hole 23) 1342179 corresponding to the circuit pattern, β omits the description of the construction process of the core layer for convenience, only The formation process of the outer layer is described. First, a resin substrate 41 having a metal layer 42 laminated on both surfaces thereof, for example, ABF (Ajinomoto Build-Film) having a thickness of about 35 μm, is typically etched and drilled in 5 lines. A blind hole 43 having a diameter of 75 μm is formed (Figs. 6A and 6A). Thereafter, the surface of the substrate having the blind hole 43 is subjected to desmear and no electric contact, thereby forming an electroless ore having a thickness of about 1 ± 〇 · 3 μηη. Metal layer 44 (Fig. 6C). Thereafter, a dry layer 45 (Fig. 6D) is formed in a predetermined region (including the blind via 43) corresponding to the circuit pattern. The dry film is used as a resist layer, and a metal pattern is formed via plating. The key layer 46 (Fig. 6E). Thereafter, the dry film 45 is removed, and then the unnecessary portion of the metal layer is removed by the rapid residue, thereby completing the patterning process (Fig. 6F). Accordingly, depending on the type of the product Examples of materials for resin substrates include Epoxy resin' such as FR-4, BT (Bismaleimide Triazine), ABF, etc. 15 For example, 'examples of BGA and UT-CSP produced by subtractive process and MSAP include a BT insulating material, The surface profile of the material is at least 1 μπι, and it is difficult to achieve a fine circuit with a pitch of no more than 80 μm (line width/pitch = 40/40 μπι) after subtracting the process order. In the MS ,, since the thickness of the metal layer derived from the half-etching varies by 20, a fine circuit having a pitch of about 50 μm (line width/pitch=25/25 μm) can be obtained. In the group of FCBGA products, The core layer is generally formed by a subtractive process using an FR_4 resin substrate to realize a circuit having a pitch of about 1 〇〇 (four) (line width / pitch = 50 / 50 μηη), and the external layer constructed is 8 1342179 A fine circuit having a pitch of 36 μm (line width/pitch = 18/18 μm) was obtained via SAP using an ABF resin substrate. However, according to this, it is difficult to realize the core layer of the fine circuit, which can be attributed to the surface roughness of the resin substrate and the limitation of the process itself. 5 Further, in the group of FCBGA products, in which the multilayer substrate is manufactured by using SAP using ABF insulating material, as shown in FIG. 7, the subtractive process is applied to the core layer (from the first to the second layer 52a, The configuration of 52b) and the application of SAP to the external layer (consisting of the third to sixth layers 55a, 55b, 57a, and 57b). More specifically, in order to form a circuit, the formation process of the outer layer is repeated twice including electroless forging to form a seed layer having a thickness of about 1 to 3 μm, an electric clock, a photoresist, and a fast etching. Therefore, the through holes 53 and the circuit patterns 52a, 52b, 55a, 55b, 57a, 57b are formed in the resin substrates 51, 54a, 54b, 56a, 56b. Next, a solder resist layer is formed and the opening portions 59a, 59b of the solder resist layer are formed. Therefore, a FCBGA having a total of 6 layers is completed. 15 However, the use of expensive ABF materials has resulted in increased process costs and high product prices. In the case of SAP application, the surface profile of the ABF material is at least 1 μηη, resulting in a large surface roughness and a distance of 36 μm (line width/pitch = 18/18 μηι). In addition, there is a limit to achieving a fine circuit through wet surface treatment and electroless plating. 20 With regard to the thinness and lightness of printed circuit boards, many manufacturers have attempted to develop insulating materials to implement fine circuits and exhibit high functionality aimed at increasing the signal transmission rate of the circuit. According to the above development trend, the number of input and output signals will be increased, and therefore, a high-reliability fine circuit is required. However, the conventional SAP suffers from the fact that the metal seed layer is formed by a wet process including 9 1342179 wet surface treatment and electroless plating, which undesirably increases the surface roughness, making it impossible to realize a fine circuit. At the same time, a large amount of waste is generated, and the problem of the environment is derived. 5 SUMMARY OF THE INVENTION The present invention has been developed through intensive and extensive layer-up printed circuit board process research. The present inventors have made efforts to avoid the problems faced by the prior art, and have found the present invention to form a build-up printed circuit. When the core layer of the board is a resin substrate laminated with a metal layer on both surfaces thereof, the metal layer is completely engraved by 10, thereby obtaining a surface roughness suitable for achieving high peel strength, and then forming a circuit layer via SAP. Instead of the general subtractive process, the metal seed layer is formed by a dry process including ion beam surface treatment and vacuum deposition' without using a general wet process including wet etching and electroless plating, so that a pair of environmentally friendly A method of manufacturing a build-up printed circuit board with a highly reliable 15 degree fine circuit. Accordingly, it is an object of the present invention to provide a method of manufacturing a build-up printed circuit board in which all of the circuit layers of the build-up printed circuit board including the core layer and the outer layer can be fabricated via SAP' thus achieving a fine Circuit 〇 20 Another object of the present invention is to provide a method of manufacturing a build-up printed circuit board in which a metal seed layer is formed via a dry process without a wet process, thereby providing a pair of environmentally friendly and economical The way to implement a circuit layer. A further object of the present invention is to provide a method for manufacturing a build-up printed circuit board in which the peel strength between the resin substrate and the metal layer can be increased, thereby realizing a high-reliability fine circuit. To achieve the above object, the present invention provides a method of manufacturing a build-up printed circuit board comprising a core layer and an outer layer, the core layer comprising the steps of: (a) providing a "first" resin substrate having a metal Laminating the layers on both surfaces; (b) removing the metal layers from the two surfaces of the first resin substrate 'c) forming an interlayer electrical property in the first resin substrate having no metal layer Connecting the through hole; (4) using the ion beam to surface-treat the first tree substrate having the through hole; (4) forming a first metal seed layer on the surface-treated resin substrate by vacuum deposition; (1) using electroplating: forming a first metal pattern plating layer on the substrate having the first metal seed layer; (g) removing a metal seed layer having no plating portion of the first metal pattern; and (8) filling conductive Paste in the through hole, thus forming a core circuit layer. In particular, the surface treatment of the ion beam is preferably performed in the presence of a gas. The inert gas system is selected from the group consisting of: argon oxygen, nitrogen gas, carbon tetrafluoride, Hydrogen, helium, gas, and mixtures of the foregoing. This vacuum deposition can be performed using sputtering 'thermal evaporation or electron beam deposition (e beam). The thickness of the first metal seed is preferably between 〜2 and 4 μmη, more preferably between 0.02 and lpm. Further, the outer layer is manufactured by the following steps: (1) laminating a second tree raft substrate on the core circuit layer; (1) forming a blind layer in the second resin substrate as 1342179 for interlayer electrical connection (k) using electroless plating to form a second metal seed layer on the second resin substrate having the blind via; (1) using electroplating to form a second metal pattern plating layer having the second metal seed layer And (m) removing the second metal seed layer without the portion of the second metal pattern plating layer. The first resin substrate and the second resin substrate may be the same or different from each other, and may include an epoxy resin or a fluororesin. At the same time, the metal is preferably copper. [Embodiment] Hereinafter, the present invention will be described in detail with reference to the drawings. As described above, the core layer of the build-up PCB is conventionally prepared by using a subtractive process to implement a circuit on a resin substrate. With 15 metal layers laminated on both surfaces of the substrate, dry film, exposure, development, and wet etching are applied, however, it is difficult to obtain a pitch of not more than 80 μm (line/width = 40/40 μm). Circuit line width. In addition, in order to alleviate the problem of such a pitch pattern, SAP is considered to be an effective method of forming a circuit for through-hole processing, desmearing, and electroless plating. Forming a metal seed layer, plating, and then rapidly etching. However, if the application SAP forms a circuit layer via a typical wet process including electroless recording and electroplating, sufficient peel strength between the resin substrate and the metal layer is indeterminate, and it is difficult to achieve one. Fine pitch circuit. 12 1342179 In the present invention, in order to overcome the above problem, when a core layer is prepared by SAP, the metal layer laminated on both surfaces of the core layer resin substrate is completely etched, so that the exposed surface roughness is suitable. To achieve high peel strength, a metal seed layer is formed in a dry process, including ion 5 beam surface treatment and vacuum deposition, instead of the usual wet process, including desmearing and no electrical contacts. Therefore, the peel strength (> 8 Kgf/cm) on the metal can be increased by the environmentally friendly SAP, and finally, it is possible to realize a fine pitch circuit having a high density. Further, in the outer layer of the build-up layer, the circuit layer is formed by using general wet type desmear, 10 electroless plating, and electroplating. In this way, since SAP can be applied to all layers of the build-up printed circuit board, a fine pitch circuit with high density can be obtained. In accordance with the present invention, Figures 8A and 8B illustrate process flow diagrams for forming the core and outer layers of a build-up printed circuit board, respectively. Referring to Figures 8A and 9A through 9H, a process for forming a core layer of a build-up printed circuit board in accordance with the present invention will now be described in detail. First, 'prepare a resin substrate 61 as a PCB, which is formed of an epoxy resin or a fluorine resin, and has a metal layer 62 laminated on both surfaces of the substrate. Metal, any conductive gold 20 can be used as long as it is suitable for circuit formation. Based on economic considerations, 'copper is particularly useful' and then 'by a full-scale process, metal layer 62 is removed from both surfaces of resin substrate 61. Therefore, even without additional surface treatment, the substrate exposes a surface roughness suitable for achieving high peel strength (Fig. 9B). 13 (S ) 1342179 Next, one or a plurality of through holes 63 ( FIG. 9C ) are formed on the resin substrate 61 as inner via holes electrically connected to the inner layer, and the surface of the substrate having the through holes 63 is formed. Treated with an ion beam. Preferably, the ion beam surface treatment procedure is carried out at an ion dose of 5E1 to 1E19 (ions/cm2) and an acceleration voltage of 0.5 to 20 keV, wherein the inert gas system is selected from the group consisting of Including Ar, 〇2, N2, Xe, CF4, Η:, Ne, Kr, and mixtures thereof, but the present invention is not limited to the above conditions. Depending on the kind of the substrate material, the actual process conditions can be appropriately set, which is obvious to those skilled in the art. Through such a dry ion beam surface treatment procedure, the peel strength of the resin substrate to form a metal seed layer can be increased. That is, as shown in FIG. 2, the surface of the polymer material of the resin substrate is excited by inert or reactive ions having energy capable of forming an unstable connection, which can be carried out with a reaction gas of 15 (for example, oxygen). The chemical reaction 'so the 'hydrophobic surface of the substrate is converted to hydrophilicity, thus increasing the peel strength of the material. Therefore, it is possible to implement a fine pitch circuit. i On the ion beam surface-treated substrate 61, a metal ion layer 64 is formed by vacuum deposition to a desired thickness of .20 (Fig. 9D). - The vacuum deposition process may be, for example, sputtering, thermal evaporation, or e-beam deposition, but is not limited thereto, as long as it is a method known in the art. The metal seed layer may have a thickness of 0.02 to 4 μm, preferably 〇.〇2~1 14 1342179 μηι' is more 〇·()2~〇5, in particular, the gold layer obtained by vacuum deposition may be selectively formed. It is thinner than the metal seed layer (2~3 (4)) formed by the general wet type electroless ore, so the working time required for the subsequent fast silver. _ can be reduced, the productivity can be improved, and 5 can avoid the formation of undercuts. (undercutting), thus obtaining a #fine core circuit wire with high-density sound, a dry vacuum deposition process, which can replace the wet-type electroless keyless process, and can be used as a metal seed layer, and because no waste liquid is generated Therefore, it is considered to be environmentally friendly. # #着, as in the prior art, a dry film 65 as an electric barrier layer is formed in 10 predetermined areas 'which is outside the pattern electro-mineral area (Fig. 9E), after which the key one The metal pattern of the key is removed and the dry film 65 is removed, thereby forming a metal pattern 66 (Fig. 9F). The metal seed layer 64 without the patterned electrode layer 66 is removed by a typical quick credit (Fig. 9G). 'And with The through-hole (5) of the patterned electroderaline layer 66 is filled with the conductive paste 67 known from the prior art, thus completing the core circuit layer (Fig. 9H). Referring to Fig. 8B and Figs. A to 1F, according to the present invention, Layered printing • The process of constructing the outer layer on the core layer of the board will be described in the core circuit layer of Figure 9H below for typical surface treatment, such as cz processing (CZ81GG, available from Peng) to increase the surface roughness of the circuit layer. A degree of 20 is used to ensure the peel strength of the material to the resin substrate, and then a substrate 71 (which may be the same as or different from the core layer) formed of an epoxy resin or a fluororesin is laminated thereon (Fig. 10A). The blind hole 72, which is electrically connected between the layers, is formed in the resin substrate 71 (Fig. 10B) and is processed through a typical surface 15 1342179 which is subjected to a desmear process and electroless plating. Thus, a metal seed having a thickness of about 2 to 3 μm is obtained. Layer 73 (Fig. i〇c). Next, the dry film 74 is formed in a predetermined region 'which corresponds to a circuit pattern region including one of the blind holes 72 (Fig. 1A) e using a dry film as a resist layer, Forming a metal pattern electric ore layer 75 via a key (Fig. 1〇E). 5 Next, the dry film 74 is removed, and a portion of the metal seed layer 73 having no metal pattern plating layer 75 is removed via a typical rapid etching, thus completing an external circuit layer (Fig. 10F). Alternatively, the SAP as shown in FIGS. 10A to 1 OF may be repeated twice to form a second layer to a sixth layer. Further, when the outermost layer of the FCBGA is used, a solder resist layer is formed, via A typical solder resist layer opening process forms an opening portion of the solder resist layer, and then a bump is formed by electroless plating of nickel/gold, as is typical in the prior art. The fabricated FCBGA having 6 layers is shown in the figure. 11 is shown. As shown in FIG. 11, a first resin substrate 81 including a first circuit layer 82a, 82b and a via hole 835 is provided as a core layer, and a second resin including a blind via and second circuit layers 85a, 85b is provided. The base materials 84a, 84b and the third resin base materials 86a, 86b including the blind holes and the second circuit layers 87a, 87b are outer layers. Further, the solder resist layers 88a, 88b are provided as the outermost layer, and the opening portions 89a, 89b of the solder resist layer are formed via a predetermined opening process. 20 Depending on the final use of the layered printed circuit board, the external layer construction process can be repeated several times and a subsequent preset process can be further performed. The fabricated layered printed circuit boards can be applied to HDI, UT-CSP, BGA, FCBG, etc. and can be applied to all products that implement fine pitch circuits without limitation. 1342179 A process for producing a build-up printed circuit board according to the present invention, in which a resin substrate having a metal layer laminated on both surfaces thereof is used as a substrate of a core layer in which a metal layer is removed, the resin The substrate can be exposed to a suitable surface roughness (Ra < 0.8 μπι) to achieve high peel strength without requiring additional surface treatment. Further, the roughness of the surface of the substrate is treated by ion beam, thereby increasing the peel strength to the metal (> 8 Kgf/cm), resulting in the realization of a fine pitch circuit. In addition, the dry process is used to form the metal seed layer instead of the general wet process, so the core layer of the fine pitch circuit can be realized with a minimum surface roughness (Ra < 0.8 μηι), via a pair of environmentally friendly 1〇 process. . Furthermore, all layers of the build-up printed circuit board, including the core layer and the outer layer, can be formed into a circuit by performing SAP. Therefore, it is possible to realize a fine pitch circuit with high density and high reliability. A preferred embodiment of the present invention can be understood by the following examples, which are set forth to illustrate and not to limit the invention. 15 Example 1 A.—fr_4 CCL (copper clad laminate) having a copper film laminated on both surfaces thereof, which was completely etched using an FeCl2 etchant. Thus, the two copper films were removed. The FR-4 substrate without the copper film was mechanically drilled using a 20 CNC (computer digital control) drill to form a through hole having a diameter of about 100 to 300 μηι, and then using nitrogen at an acceleration voltage of about i KeV' and 1E15. The ion beam surface treatment was carried out under an ion dose. Thereafter, a steel seed layer having a thickness of about 0.3 μm is deposited on the surface of the treated substrate by DC sputtering, followed by a predetermined air flow volume of 17 1342179 (0.05 to 0.15 m3/min), and a temperature (20 to 25). °C), and current density (F/B1.5ASD) by H2S04 (120~160 gm), Cu (20~40 g/1), Cl· (20~50 ppm), and cupracid The copper pattern of the HL flattening agent (5 to 15 ml/1) is plated to form a copper pattern 5 plating layer having a thickness of about 10 Å to 20 μm, and then by rapid etching (etching speed 2 m/min, using H2S04/H202 etchant Remove the copper seed layer. Finally, under a condition of a viscosity of 3.0 pa.s, a preheat treatment of 80oC/60 min, and a curing of 160oC/60min, the copper paste is filled in the through hole, thus completing a core circuit layer. . B. The resulting core circuit layer was subjected to CZ treatment (CZ8100, available from 10 MEC) to increase the surface roughness of the copper to ensure the peel strength to the substrate material. Use the main vacuum press equipment at a temperature of 100. (:, vacuum time 30 seconds, pressure 7 kgf/cm2, and pressing time 60 seconds, temporarily splicing ABF on the core circuit layer, and then using secondary hot pressing under the conditions of temperature 100 ° C, pressure 10 kgf / cm 2 And pressing the lower layer 15 pressure for 90 seconds. Then use a carbon dioxide laser to form a blind hole with a diameter of about 70 μm, and use permanganic acid in the Changyuan process. The stain is at pHIO~12 because of the lagoon. Remove (〇114+12]^11〇4-+140丨4〇032-+12Μη042·+ 9H20 + 02), thus forming a predetermined surface roughness. Subsequently, the dioxide is removed by neutralization Manganese 20 dioxide residue (CH4 + 12Μη〇4· + 140H_ -> C032- + 12Μη042·+ 9H20 + 02), subjected to desmear treatment, and in CuS04 + 2HCHO + 4NaOH Cu + 2HC〇2Na + Electroless plating of copper (Atotech) was carried out in the state of H2 + 2H2O + Na2S〇4, thereby forming a copper seed layer having a thickness of about 3 μm. Then, by copper pattern key (Evara), H2S04 18 1342179 • (120-160) G1,1), Cu (20~40 g/l), Cl- (20~50 ppm), and cupracid H L flat agent (5~15 ml/1) under the condition that the preset air flow volume is 0.05~0.15 m3/min, the temperature is 20~25°C and the current density is • F/B1, 5ASD, forming thickness It is a copper pattern of 15 μηι, after which 5 is removed using H2S〇4/H2〇2 as an etchant, and the copper seed layer is removed by rapid etching at an etching rate of 2 m/min. The build-up process of the material is 'the same as the process of B to form the outer layer of the outer layer including the third to sixth layers. The condition is the roll pitch: 370 μηι, 350 Μπι 10 and 32〇, roll press 'Scratch strip down' ((1〇(^〇1· bar press) 'Roller speed: 丨2~1, 6 m/min, and drying temperature/ Time: 78 C ± 2 ° C, forming a solder resist layer, then pre-baked at a first stagnation time of 3 sec and a second stagnation time of 3 sec, so the solvent is removed from the ink and formed The surface of the ink is partially cured and dried, as this is suitable for the exposure process. In the exposure process, the UV light is irradiated with a light intensity of 700 to 900 mJ/cm2. The surface of the ink is formed, and the working diaphragm via a • (working film) / glass mask light-induced curing reaction of the ink (Photocuring), so that the ink can be used as the reactive impedance in the developer, nervous. In the development process, the photohardening portion of the ink can be used as an impedance in sodium carbonate (Na2C03 20%), whereas no photohardening portion is dissolved and removed. • 1% sodium carbonate solution (1°/.sodium) used. The conditions of carbonate are: sodium carbonate concentration 11 ± 1·〇g/1 (SPEC: 1〇5 ± 2 〇g/1), sodium carbonate pH value 10.0~12.5 'carbonate temperature 3〇± 3〇c, development Pressure, and development speed, and UV curing (the surface of the developed ink sheet 1342179 is further photohardened, so incomplete photoreaction is additionally induced by UV exposure) to increase SR nature). In order to improve the peel strength between the post-cured (completely dried) ink and copper, and to increase the hardness of the ink 'the double bond of the curing agent in the ink is activated by 5' and in all hardening agents The resin begins to react in a post-cudng process to produce a complete polymer. The condition is temperature/time: 120oC/30 min and 150oC/60 min, and the portion corresponding to the circuit pattern of the bump is exposed through the opening of the solder resist layer, and then the condition is: 52-38 g/1, pH: 3.5 to 4.5., nickel 10 sulfamate: 400 to 500 g/b vaporized nickel: 8 to 16 g/b Fe: 200 ppm or less 'Cu: 200 ppm or less, and temperature: 45~55. (:, electroless plating of nickel, then in the condition of Au: 5.5~7.5 g / Bu pH: 6.1 ~ 6.4, specific gravity: 1.09 ~ 1.24, Fe: 50 ppm or less, Cu: 18 ppm or less, Ni: 350 Ppm or less, Zn: 5 ppm or less, T1: 5 to 15 ppm, 15 and temperature: 65 to 75 ° C, electroless plating of gold, thus manufacturing FCBGA. The peel strength of the build-up printed circuit board is therefore The surface roughness of the insulating material was measured and measured. The results are shown in Table 1 below.
20 一FCBGA以相同於實施例1的方法製造，除了在階段A 中以離子束激链代替直流激鍵。 增層式印刷電路板的剝離強度因此被製造出，並且量 測絕緣材料的表面粗糙度。其結果顯示於以下表1中。 25 比較例1 20 1342179 一 FCBGA以相同於實施例1的方法製造，除了在階段a 中’略去離子束表面處理及直流濺鍍沈積，並且使用如下 所述之一般的濕式製程包括去鑽污及銅的無電電錢而形 成銅種子層。 5 增層式印刷電路板的剝離強度因此被製造出，並且量 測絕緣材料的表面粗糙度。其結果顯示於以下表1中。 ※去鑽污 澎潤（為軟化劑之功能，最佳蝕刻於PH為10〜12，亦 即’作為澎潤污斑►三階段水洗—高錳酸處理（去除主要 10 污斑且將樹脂表面粗糙化）—一階段水洗兩階段水洗— 中和（去除二氧化猛殘留）—三階段水洗_^乾燥 ※無電電鍍銅 清洗（是一鹼性化學清洗製程，其是為了高的剝離強度 以及為了鈀吸附之條件製程）—三階段水洗—蝕刻清洗（去 15 除銅的氧化層以及為確保銅層間的剝離強度而粗糙化）-> 二階段水洗-> 預浸洗（去除過硫酸鹽（persulfate)殘留及作 為一預活化劑（pre-activator))—活化劑（鈀離子（非凝膠態） 吸附）4三階段水洗—還原（將鈀離子還原成鈀以作為觸媒） —三階段水洗—化學銅（使用鈀觸媒將鋼離子形成銅層）— 2〇 三階段水洗—乾燥 表一 實施例1 實施例2 比較例1 剝離強度 0.8 kgf/cm 1.0 kgf/cm 0.5 kgf/cm 21 (5 ) 1342179 表面粗糙度 0.9 μιη 0.9 (m 1.0 (m 如表一所示’在使用一般濕式製程所製造之積層基材 的例子中（比較例1)，剝離強度約為0.5 kgf/cm及表面粗糙 度為1.0 (m，其能夠形成之間距為36 (m(線/間距=18/18 5 (m)。然而，在使用根據本發明之乾式製程所製造之積層基 材的例子中（實施例1和2)，剝離強度約為0.9 kgf/cm且表面 粗縫度相對較小’在0.9 (m範圍。因此，可以實現具有間 • 距20 (m(線/間距= 10/10 (m)的精細電路以及可得到較快的 訊號傳輸速率。 10 雖然關於本發明之製造增層式印刷電路板的方法之較 佳實施例，以為了說明而揭露。本技術領域之人士可在不 背離本發明之技術精神下’是可能進行不同的修改、附加 及取代。 如前所述’本發明提供一種製造增層式印刷電路板之 15 方法。根據本發明’一具有金屬層層壓於兩表面之樹脂基 材，其被完全蝕刻而露出適合實現高剝離強度之表面粗糙 度，而不需另外的表面處理，之後，藉由SAP形成核心層 之金屬電路層，所提供之金屬種子層係經由一乾式製程而 . 形成，包括離子束表面處理及真空沈積，其代替了包括濕 .2〇 式蝕刻及無電電鍍之一般濕式製程，因此增加了材料的剝 離強度。 再者’在使用一般無電電鍍製程形成金屬種子層的製 程中，因所形成之層是相對厚的，大約在3μιη的範圍，在 22 1342179 隨後的金屬種子層的移除製程中，其快速蝕刻所需的時間 會增加’且可能發生底切（undercutting)的問題。然而，在 本發明中’經由離子束表面處理及真空沈積，形成較薄的 金屬種子層，因此減少製程時間而有高生產性。同時，可 5 以克服底切的問題。因此，實現具有高密度之精細電路是 可能的。 再者，以離子束表面處理及真空沈積取代一般濕式表 面處理及無電電嫂，並因此提升對金屬的剝離強度（> 〇.8 φ Kgf/cm)’因此以一對環境友善的方法，使得實現具有間距 10 不大於40 μιη (線/間距=20/20 μιη)的精細電路是可能的。 此外，因為為了基材與金屬電路層之間的高剝離強 度’積層基材的核心層也是藉由SAP形成，積層基材中的 所有層別經由SAP製造，並因此可確保高可靠性之精細電 路0 15 在本發明範圍内之修改、附加及取代是落入如附揭露 之申請專利範圍中》 【圖式簡單說明】 . 圖1A及1B係根據第一習知技術，分別地顯示形成增 2〇 層式印刷電路板之核心層及外部層之製程流程圖。 圖2A至2G係根據第一習知技術，接續地顯示形成增 層式印刷電路板之核心層之製程剖面圖。 圖3 A至3F係根據第一習知技術’接續地顯示形成增 層式印刷電路板之外部層之製程剖面圖。 23 (S ) 1342179 圖4A及4B係根據第二習知技術，分別地顯示形成增 層式印刷電路板之核心層及外部層之製程流程圖。 圖5A至5G係根據第二習知技術，接續地顯示形成增 層式印刷電路板之核心層之製程剖面圖。 5 圖6A至6F係根據第二習知技術，接續地顯示形成增 層式印刷電路板之外部層之製程剖面圖。 圖7係顯示習知FCBGA印刷電路板結構之剖面示意 圖。 圖8 A及8B係根據本發明’分別地顯示形成增層式印 10 刷電路板之核心層及外部層之製程流程圖。 圖9A至9H係根據本發明，接續地顯示形成增層式印 刷電路板之核心層之製程剖面圖。 圖10A至10F係接續地顯示於圖9H之核心層上形成第 一外部層之製程剖面圖。 15 圖Η係接續地顯示於圖10F之第一外部層上形成第二 外部層而製造之FCBGA印刷電路板之結構剖面圖。 圖12係根據本發明，顯示印刷電路板之離子束表面處 理之示意圖。 20 【主要元件符號說明】 13貫穿孔 16導電膏 22金屬層 11樹脂基材 12金屬層 14無電電鍍金屬層 15金屬電鍍層 17乾膜 21樹脂基材 24 1342179 23盲孔 24無電電鍍金屬層 26乾膜 27金屬圖案電鍍層 31樹脂基材 32金屬層 33貫穿孔 34無電電鍍金屬層 35金屬電鍍層 36導電膏 37乾膜 41樹脂基材 42金屬層 43盲孔 44無電電鍍金屬層 45乾膜 46金屬圖案電鍍層 51樹脂基材 52a，52b電路圖案 53通孔 54a，54b樹脂基材 55a，55b電路圖案 56a, 56b樹脂基材 57a,57b電路圖案 59a，59b 開口 61樹脂基材 62金屬層 63貫穿孔 64金屬離子層 65乾膜 66金屬圖案電鍵層 67導電膏 71樹脂基材 72盲孔 73金屬種子層 74乾膜 75乾膜 81第一樹脂基材 82a，82b第一電路層 83通孔 84a，84b第二樹脂基材 85a，85b第二電路層 863,861»第三樹脂基材873,871)第三電路層 89 a,89b 開口 88a,88b防焊阻層20 An FCBGA was produced in the same manner as in Example 1, except that in the phase A, the ion beam was replaced by an ion beam. The peel strength of the build-up printed circuit board is thus manufactured, and the surface roughness of the insulating material is measured. The results are shown in Table 1 below. 25 Comparative Example 1 20 1342179 An FCBGA was produced in the same manner as in Example 1, except that in the stage a, the ion beam surface treatment and the DC sputtering deposition were omitted, and the general wet process as described below included drilling. Stain and copper have no electricity and electricity to form a copper seed layer. 5 The peel strength of the build-up printed circuit board is thus manufactured, and the surface roughness of the insulating material is measured. The results are shown in Table 1 below. ※Drilling and smudging (for the function of softener, the best etching is at pH 10~12, ie 'as 澎 污 ► ► three-stage water washing - permanganic treatment (removing the main 10 stains and the resin surface Roughening) - one-stage washing and two-stage washing - neutralization (removal of oxidizing slag) - three-stage washing _^ drying ※ electroless copper plating cleaning (an alkaline chemical cleaning process for high peel strength and for Palladium Adsorption Condition Process)—Three-stage water wash-etch cleaning (to remove the copper oxide layer and roughen to ensure the peel strength between the copper layers)-> Two-stage water wash-> Pre-dip wash (removal of persulfate (persulfate) residue and as a pre-activator) activator (palladium ion (non-gel state) adsorption) 4 three-stage water washing - reduction (reduction of palladium ions into palladium as a catalyst) - three Stage water washing - chemical copper (using a palladium catalyst to form a copper layer of steel ions) - 2 〇 three-stage water washing - drying Table 1 Example 1 Comparative Example 1 Peeling strength 0.8 kgf / cm 1.0 kgf / cm 0.5 kgf / cm 21 (5 ) 1342179 Roughness 0.9 μιη 0.9 (m 1.0 (m as shown in Table 1) In the example of a laminated substrate manufactured by a general wet process (Comparative Example 1), the peel strength was about 0.5 kgf/cm and the surface roughness was 1.0 (m, which can form a distance of 36 (m/line = 18/18 5 (m). However, in the example of using the laminated substrate manufactured by the dry process according to the present invention (Example 1 and 2), the peel strength is about 0.9 kgf/cm and the surface roughness is relatively small 'in the range of 0.9 (m. Therefore, it is possible to achieve a fineness with a distance of 20 (m/line/pitch = 10/10 (m)) The circuit and the faster signal transmission rate are available. 10 Although a preferred embodiment of the method of fabricating a build-up printed circuit board of the present invention is disclosed for purposes of illustration, those skilled in the art may leave without departing from the invention. Under the technical spirit, it is possible to make various modifications, additions and substitutions. As described above, the present invention provides a method for manufacturing a build-up printed circuit board. According to the present invention, a resin having a metal layer laminated on both surfaces Substrate, which is completely etched to expose suitable for implementation Peeling the surface roughness of the strength without additional surface treatment. Thereafter, the metal circuit layer of the core layer is formed by SAP, and the metal seed layer is formed through a dry process, including ion beam surface treatment and vacuum. Deposition, which replaces the general wet process including wet etching and electroless plating, thereby increasing the peel strength of the material. Furthermore, in the process of forming a metal seed layer using a general electroless plating process, The layer is relatively thick, in the range of about 3 μm, and in the subsequent removal process of the metal seed layer of 22 1342179, the time required for rapid etching increases, and undercutting problems may occur. However, in the present invention, a thin metal seed layer is formed by ion beam surface treatment and vacuum deposition, thereby reducing process time and high productivity. At the same time, you can overcome the problem of undercutting. Therefore, it is possible to realize a fine circuit with high density. Furthermore, ion beam surface treatment and vacuum deposition replace the general wet surface treatment and no electric enthalpy, and thus the peel strength of the metal (> φ Kgf/cm) is improved. Therefore, in a pair of environmentally friendly methods It is possible to realize a fine circuit having a pitch of 10 not more than 40 μm (line/pitch = 20/20 μm). In addition, since the core layer of the laminated substrate is also formed by SAP for high peel strength between the substrate and the metal circuit layer, all layers in the laminated substrate are manufactured via SAP, and thus high precision is ensured. Modifications, additions and substitutions of the circuit 0 15 within the scope of the invention are included in the scope of the appended claims. [FIG. 1A and 1B are respectively shown in the first prior art. Process flow chart for the core layer and the outer layer of the 2-layer printed circuit board. 2A to 2G are cross-sectional views showing processes of forming a core layer of a build-up printed circuit board in accordance with a first conventional technique. 3 to 3F are process sectional views showing the formation of the outer layer of the build-up printed circuit board in accordance with the first conventional technique. 23 (S) 1342179 Figures 4A and 4B are flow diagrams showing the process of forming the core layer and the outer layer of the build-up printed circuit board, respectively, according to a second prior art technique. Figures 5A through 5G are cross-sectional views showing the process of forming a core layer of a build-up printed circuit board in accordance with a second conventional technique. 5A to 6F are process cross-sectional views showing the formation of an outer layer of a build-up printed circuit board in accordance with a second conventional technique. Fig. 7 is a schematic cross-sectional view showing the structure of a conventional FCBGA printed circuit board. Figures 8A and 8B are process flow diagrams showing the formation of the core layer and the outer layer of the build-up printed circuit board, respectively, in accordance with the present invention. Figures 9A through 9H are cross-sectional views showing the process of forming a core layer of a build-up printed circuit board in accordance with the present invention. 10A through 10F are process cross-sectional views showing the first outer layer formed successively on the core layer of Fig. 9H. Figure 15 is a cross-sectional view showing the structure of an FCBGA printed circuit board manufactured by forming a second outer layer on the first outer layer of Figure 10F. Figure 12 is a schematic illustration of the surface treatment of an ion beam showing a printed circuit board in accordance with the present invention. 20 [Main component symbol description] 13 through hole 16 conductive paste 22 metal layer 11 resin substrate 12 metal layer 14 electroless plating metal layer 15 metal plating layer 17 dry film 21 resin substrate 24 1342179 23 blind hole 24 electroless plating metal layer 26 Dry film 27 metal pattern plating layer 31 resin substrate 32 metal layer 33 through hole 34 electroless plating metal layer 35 metal plating layer 36 conductive paste 37 dry film 41 resin substrate 42 metal layer 43 blind hole 44 electroless plating metal layer 45 dry film 46 metal pattern plating layer 51 resin substrate 52a, 52b circuit pattern 53 through hole 54a, 54b resin substrate 55a, 55b circuit pattern 56a, 56b resin substrate 57a, 57b circuit pattern 59a, 59b opening 61 resin substrate 62 metal layer 63 through hole 64 metal ion layer 65 dry film 66 metal pattern key layer 67 conductive paste 71 resin substrate 72 blind hole 73 metal seed layer 74 dry film 75 dry film 81 first resin substrate 82a, 82b first circuit layer 83 pass Holes 84a, 84b second resin substrate 85a, 85b second circuit layer 863, 861» third resin substrate 873, 871) third circuit layer 89 a, 89b opening 88a, 88b solder resist layer