JP2000294929A - Manufacture of multilayer printed wiring board and the multilayer printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a multilayer printed wiring board, in which connection reliability of a conductor circuit to a via hole formed on a roughened face can be ensured sufficiently, even when the roughened face is formed on the conductor circuit through etching operation. SOLUTION: In this manufacturing method of a multilayer printed wiring board, conductor circuits 4 which are composed of a plurality of layers by sandwiching interlayer resin-insulating layers are formed on an insulating board by repeating a process, wherein the conductor circuits 4 are formed, a roughening treatment is executed, the conductor circuits 4 to which the roughening treatment is executed are covered with an interlayer resin-insulating layers 2 and opening for via holes are formed. Than the manufacturing method for the multilayer printed wiring board includes after the formation of the openings for the via holes, an etching treatment executed to the roughened faces 4a on the conductor circuits 4, which are exposed from the openings for the via holes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Detailed description of the invention]

[0002]

2. Description of the Related Art In recent years, a so-called build-up multilayer wiring board has attracted attention due to a demand for higher density of the multilayer wiring board. This build-up multilayer wiring board, for example,
It is manufactured by a method as disclosed in Japanese Patent Publication No. 55555/1992. That is, an adhesive for electroless plating made of a photosensitive resin is applied to the core substrate on which the lower conductive circuit is formed, and then dried and exposed and developed to form an interlayer resin having an opening for a via hole. An insulating layer is formed. Next, after the surface of the interlayer resin insulating layer is roughened by a treatment with an oxidizing agent or the like, the photosensitive resin layer is exposed,
A plating resist is provided by performing a development process, and thereafter, a portion where the plating resist is not formed is subjected to electroless plating or the like to form a conductive circuit pattern including via holes. By repeating such a process a plurality of times, a multilayered build-up wiring board is manufactured.

In such a build-up multilayer wiring board, as described in JP-A-7-292483, a copper complex of an azole is used to improve the adhesion between the conductor circuit and the resin insulating layer. The surface of the conductor circuit is roughened with an etchant containing an organic acid to form a roughened surface.

[0004]

However, a roughened surface is formed on the surface of the conductor circuit by a roughening treatment using an etching solution containing a cupric complex of an azole and an organic acid. If a via hole is formed on the upper surface, a breakage may occur at the point of contact between the via hole and the underlying conductive circuit during heating or heat cycling, which may lower the connection reliability of the via hole. I found the facts.

An object of the present invention is to provide a multilayer printed wiring board capable of sufficiently securing the connection reliability with via holes formed thereon even when a roughened surface is formed in a conductive circuit by etching. And a multilayer printed wiring board manufactured by the manufacturing method.

[0006]

Means for Solving the Problems In view of the above problems, the present inventor has conducted intensive studies to achieve the above object. As a result, during heating or heat cycle, a breakage between the via hole and the roughened surface of the conductor circuit occurred. Is caused by the presence of the fragile layer in the portion where the roughened surface is formed. With a predetermined etching solution, only the fragile layer can be removed by etching, and as a result, The present inventors have found that the above problem can be solved, and have completed the present invention having the following configuration as a gist configuration.

That is, according to the method of manufacturing a multilayer printed wiring board of the present invention, a conductor circuit is formed, subjected to a roughening treatment, and then the conductor circuit subjected to the roughening treatment is covered with an interlayer resin insulating layer. In a method for manufacturing a multilayer printed wiring board in which a conductor circuit composed of a plurality of layers sandwiching an interlayer resin insulating layer is formed on an insulating substrate by repeating a step of forming a hole opening, a via hole opening is formed in the interlayer resin insulating layer. After the formation, the roughened surface of the conductor circuit exposed from the via hole opening is subjected to an etching process.

In the method for manufacturing a multilayer printed wiring board, it is desirable to perform the etching treatment using an aqueous solution of persulfate or a mixed aqueous solution of hydrogen peroxide and sulfuric acid. Further, it is desirable that the roughening treatment of the conductor circuit be performed by causing an etchant comprising a cupric complex and an organic acid to act in coexistence with oxygen.

In the multilayer printed wiring board according to the present invention, an interlayer resin insulating layer is formed on a substrate on which a conductor circuit having a roughened surface is formed, and a via hole opening is formed in the interlayer resin insulating layer. In a multilayer printed wiring board in which a conductor is formed in a hole opening and a via hole is formed, a roughened surface of the conductor circuit exposed from the via hole opening is subjected to an etching process for forming a roughened surface. After being applied, the roughened surface is further subjected to an etching process for removing a fragile layer. By performing such an etching treatment, the roughness of the roughened surface of the conductor circuit exposed from the via hole opening becomes smaller than that of the other portions. Since the roughened surface of the conductor circuit exposed from the via hole opening has such a form, without reducing the adhesion with the interlayer resin insulation layer, the throwing power of the plating is improved by improving the plating throwing power. Connection reliability can be ensured. It is desirable that the roughness of the roughened surface of the conductor circuit exposed from the via hole opening is smaller by 0.5 to 5 μm than the roughness of the roughened surface of the other portions. If the difference is too large, the peeling of the via tends to occur, and if the difference is too small, the fragile layer cannot be removed.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION In the method for manufacturing a multilayer printed wiring board according to the present invention, a conductor circuit is formed, roughened, and then the roughened conductor circuit is covered with an interlayer resin insulating layer. In a method of manufacturing a multilayer printed wiring board in which a conductor circuit composed of a plurality of layers sandwiching an interlayer resin insulating layer is formed on an insulating substrate by repeating a step of forming a via hole opening, a via hole is formed in the interlayer resin insulating layer. After forming the opening for etching, the roughened surface of the conductor circuit exposed from the opening for via hole is subjected to an etching treatment.

According to the method of manufacturing a multilayer printed wiring board of the present invention, a roughened surface of a conductor circuit exposed from a via hole opening formed in an interlayer resin insulating layer is subjected to an etching treatment for removing a fragile layer. Therefore, the fragile layer disappears at the portion where the roughened surface is formed, and the unevenness of the roughened surface is maintained. Therefore, a via hole having excellent adhesion to the conductor circuit can be formed on the conductor circuit, and a multilayer printed wiring board having sufficiently secured connection reliability between the via hole and the conductor circuit can be manufactured. it can.

An etching method for forming a roughened surface by subjecting a conductor circuit to a roughening process is not particularly limited. In the present invention, an etching solution containing a cupric complex and an organic acid is used. When the method of acting in the coexistence of oxygen is employed, the above-mentioned effects are sufficiently obtained. In this case, the etching proceeds by the chemical reaction of the following formulas (1) and (2).

[0013]

Embedded image

As the cupric complex, a cupric complex of an azole is desirable. This cupric complex of azoles is
It acts as an oxidizing agent that oxidizes metallic copper and the like. Examples of the azoles include diazole, triazole, and tetrazole. Among these, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-undecylimidazole and the like are desirable. The content of the cupric complex of azoles in the etching solution is desirably 1 to 15% by weight. This is because it is excellent in solubility and stability, and can also dissolve noble metals such as Pd constituting the catalyst core.

In order to dissolve copper oxide, an organic acid is added to a cupric complex of an azole. Specific examples of the organic acid include, for example, formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid, Glycolic acid, lactic acid, malic acid, sulfamic acid and the like can be mentioned. These may be used alone or in combination of two or more.

The content of the organic acid in the etching solution is 0.1%.
1 to 30% by weight is desirable. This is because the solubility of the oxidized copper can be maintained and the solubility stability can be ensured. As shown in the above formula (2), the generated cuprous complex dissolves under the action of an acid and combines with oxygen to form a cupric complex, which again contributes to oxidation of copper.

To aid in dissolving copper and oxidizing azoles, halogen ions, for example, fluorine ions, chlorine ions, bromine ions, etc., may be added to the etching solution. Also, halogen ions can be supplied by adding hydrochloric acid, sodium chloride, or the like. The content of halogen ions in the etching solution is 0.01 to 20.
% By weight is desirable. This is because adhesion between the formed roughened surface and the interlayer resin insulating layer is excellent.

In preparing the etching solution, a cupric complex of an azole and an organic acid (if necessary, having a halogen ion) are dissolved in water. As the etching solution, a commercially available etching solution, for example, “Mech Etch Bond” manufactured by Mec Co., Ltd. is used.
The etching amount (that is, roughness) when the above-mentioned etching solution is used is preferably 0.5 to 10 μm, and most preferably 1 to 5 μm. When the etching amount exceeds 10 μm, poor connection between the formed roughened surface and the via-hole conductor occurs. On the other hand, when the etching amount is less than 0.5 μm, the adhesion to the interlayer resin insulating layer formed thereon becomes poor. This is because it becomes insufficient.

The roughened surface formed by the above method may be covered with a layer of a metal or a noble metal having a higher ionization tendency than copper and not more than titanium (hereinafter, referred to as a metal layer). Such metals include, for example, titanium, aluminum, zinc, iron, indium, thallium, cobalt,
Examples include nickel, tin, lead, and bismuth. Examples of the noble metal include gold, silver, platinum, and palladium. These may be used alone,
A plurality of layers may be formed by using two or more kinds in combination.

These metal layers cover the roughened layer, and even if the interlayer resin insulating layer is roughened, the local electrode reaction is prevented and the conductor circuit is prevented from melting. The thickness of these metals is 0.1-
2 μm is desirable.

Of the metals constituting the metal layer, tin is desirable. This is because tin can form a thin layer by electroless displacement plating and can follow the roughened layer. When forming a metal layer made of tin, a solution containing tin borofluoride-thiourea, or tin chloride-
Displacement plating is performed using a solution containing thiourea. In this case, a Sn layer having a thickness of about 0.1 to 2 μm is formed by the substitution reaction of Cu—Sn. When a metal layer made of a noble metal is formed, a method such as sputtering or vapor deposition can be employed.

After an interlayer resin insulating layer is formed on a substrate surface including a conductor circuit having a roughened surface formed as described above by a method described later, a via hole opening is formed.
An etching process is performed to remove the fragile layer in the portion where the roughened surface is formed.

The etchant for removing the fragile layer is not particularly limited as long as it can remove the fragile layer. For example, an aqueous solution containing a persulfate may be used. The brittle layer can also be removed with an etchant made of sulfuric acid.

Examples of the above-mentioned persulfate include ammonium persulfate, sodium persulfate and potassium persulfate. These may be used alone or in combination of two or more. The concentration of the above persulfate in the aqueous solution is 2
0-100 g / l is desirable. Persulfate concentration 20g
/ L, it is difficult to completely remove the fragile layer. On the other hand, if the concentration of persulfate exceeds 100 g / l, the etching proceeds too much to etch other parts and the roughened surface The height of the unevenness is reduced.

The temperature of the etching solution at the time of etching is preferably 25 to 40 ° C., and the time of the etching treatment is preferably about 30 to 120 seconds.

In the multilayer printed wiring board according to the present invention, an interlayer resin insulating layer is formed on a substrate on which a conductor circuit having a roughened surface is formed, and a via hole opening is formed in the interlayer resin insulating layer. In a multilayer printed wiring board in which a conductor is formed in a hole opening and a via hole is formed, a roughened surface of the conductor circuit exposed from the via hole opening is subjected to an etching process for forming a roughened surface. After the application, the roughened surface is further subjected to an etching process.

According to the multilayer printed wiring board of the present invention, the roughened surface of the conductor circuit exposed from the via hole opening is subjected to the etching treatment to remove the fragile layer, so that the roughened surface is formed. There is no fragile layer at the portion where the connection is made, and a multilayer printed wiring board with sufficient connection reliability between the via hole and the conductor circuit is obtained. Further, by performing such an etching process, the roughness of the roughened surface of the conductor circuit exposed from the via hole opening becomes smaller than the roughness of the roughened surface of the other portions. Without reducing the adhesion to the layer, the throwing power of the plating can be improved and the connection reliability of the via hole can be ensured.

Next, a method of manufacturing a multilayer printed wiring board according to the present invention will be described by taking a semi-additive method as an example. (1) First, a substrate having an inner copper pattern (lower conductive circuit) formed on the surface of a core substrate is prepared. When forming a conductor circuit for this core substrate, a method of etching a copper-clad laminate into a specific pattern, a method of forming an adhesive layer for electroless plating on a substrate such as a glass epoxy substrate, a polyimide substrate, a ceramic substrate, and a metal substrate. Forming, after roughening the surface of the adhesive layer for electroless plating to a roughened surface, a method of performing electroless plating, or performing electroless plating on the entire roughened surface to form a plating resist, Using a method (semi-additive method) of forming a conductor circuit consisting of an electrolytic plating film and an electroless plating film by applying a plating resist after removing the plating resist after applying electrolytic plating to the portion where no plating resist is formed, and performing an etching process. Can be.

Normally, after a conductive circuit is formed on a substrate, a low-viscosity resin filler such as bisphenol F type epoxy resin is filled between the through hole and the conductive circuit of the core substrate, and then the resin layer and the conductive circuit are polished. By doing so, the smoothness between the resin layer and the conductor circuit is ensured, but a roughened surface or a roughened layer is formed on the surface of the conductor circuit before filling with the resin filler.

Note that a through hole may be formed in the core substrate, and the wiring layers on the front and back surfaces may be electrically connected via the through hole.

The roughened surface or the roughened layer is desirably formed by any one of a polishing treatment, an etching treatment, a blackening reduction treatment and a plating treatment. Of these processes, when performing the blackening reduction process, NaOH
(20 g / l), NaClO ₂ (50 g / l), Na ₃
A blackening bath (oxidizing bath) composed of an aqueous solution containing PO ₄ (15.0 g / l), NaOH (2.7 g / l), Na
A method of forming a roughened surface using a reducing bath composed of an aqueous solution containing BH ₄ (1.0 g / l) is desirable.

When a roughened layer is formed by plating, copper sulfate (1 to 40 g / l), nickel sulfate (0.1 to 6.0 g / l), and citric acid (10 to 20 g / l) are used.
l), sodium hypophosphite (10-100 g / l),
Boric acid (10 to 40 g / l), surfactant (Surfynol 465, manufactured by Nissin Chemical Industry Co., Ltd.) (0.01 to 10 g / l)
It is preferable to form a roughened layer made of a Cu-Ni-P alloy by performing electroless plating in an electroless plating bath having a pH of 9 and containing l). This is because the crystalline structure of the film deposited in this range has a needle-like structure, and thus has an excellent anchor effect. A complexing agent or an additive may be added to the electroless plating bath in addition to the above compounds.

As the above-mentioned etching treatment method, there is a method in which the above-mentioned etching solution containing a cupric complex and an organic acid is allowed to act in the coexistence of oxygen to roughen the surface of a conductor circuit. This method has been described in detail. Therefore, the description is omitted here.

The roughened surface or the roughened layer formed by the above method is usually polished while leaving the side surfaces, so that the smoothness between the resin layer and the conductor circuit is ensured.

Thereafter, the conductor circuit is again subjected to a roughening treatment. In this case, the above-mentioned method, that is, a method in which an etching solution containing a cupric complex and an organic acid is caused to act on the conductor circuit by coexistence of oxygen. Form a roughened surface. Note that, after a roughened surface is formed on a conductive circuit using an etching solution containing a cupric complex and an organic acid, the interlayer resin insulating layer may be formed without performing polishing treatment.

(2) Next, on the substrate prepared in (1) above, a resin composition for forming a roughened surface containing an organic solvent is applied and dried to form a layer of the resin composition for forming a roughened surface. Provide.

The above-mentioned resin composition for forming a roughened surface comprises an acid, an alkali and an acid in an uncured heat-resistant resin matrix which is hardly soluble in a roughening liquid comprising at least one selected from acids, alkalis and oxidizing agents. It is desirable that a substance that is soluble in a roughening liquid composed of at least one selected from an oxidizing agent and a oxidizing agent is dispersed. Note that the terms "poorly soluble" and "soluble" used in the present invention, when immersed in the same roughening solution for the same time, those having a relatively high dissolution rate are referred to as "soluble" for convenience, and Those with a slow dissolution rate are called "poorly soluble" for convenience.

As the heat-resistant resin matrix, for example, a thermosetting resin or a composite of a thermosetting resin (including one in which a part of the thermosetting group is sensitized) and a thermoplastic resin are used. Can be.

The thermosetting resin includes, for example, epoxy resin, phenol resin, polyimide resin, thermosetting polyolefin resin and the like. When the thermosetting resin is exposed to light, a methacrylic acid, acrylic acid, or the like is used to cause the thermosetting group to undergo a (meth) acrylation reaction. Particularly, epoxy resin (meth) acrylate is most suitable.

As the epoxy resin, for example, a novolak type epoxy resin, an alicyclic epoxy resin or the like can be used. As the thermoplastic resin, for example, polyether sulfone, polysulfone, polyphenylene sulfone, polyphenylene sulfide, polyphenyl ether, polyether imide, and the like can be used.

The substance soluble in the roughening liquid comprising at least one selected from the above-mentioned acids, alkalis and oxidizing agents is selected from inorganic particles, resin particles, metal particles, rubber particles, liquid resin and liquid rubber. It is desirable that it is at least one kind.

Examples of the inorganic particles include silica,
Examples include alumina, calcium carbonate, talc, and dolomite. These may be used alone or in combination of two or more. The alumina particles can be dissolved and removed with hydrofluoric acid, and the calcium carbonate can be dissolved and removed with hydrochloric acid. Further, sodium-containing silica and dolomite can be dissolved and removed with an alkaline aqueous solution.

Examples of the resin particles include amino resins (melamine resin, urea resin, guanamine resin, etc.),
Epoxy resins, bismaleimide-triazine resins and the like can be mentioned. These may be used alone or in combination of two or more. The epoxy resin can be arbitrarily manufactured by dissolving in an acid or an oxidizing agent or hardly dissolving in the acid or the oxidizing agent by selecting the type of the oligomer and the curing agent. For example, a resin obtained by curing a bisphenol A-type epoxy resin with an amine-based curing agent is very soluble in chromic acid, but a resin obtained by curing a cresol novolac-type epoxy resin with an imidazole curing agent is not easily dissolved in chromic acid. .

It is necessary that the resin particles have been previously cured. If not cured, the resin particles will dissolve in the solvent that dissolves the resin matrix, so they will be uniformly mixed, and it will not be possible to selectively dissolve and remove only the resin particles with an acid or oxidizing agent. is there.

The metal particles include, for example, gold, silver,
Examples include copper, tin, zinc, stainless steel, and aluminum. These may be used alone or in combination of two or more. Examples of the rubber particles include acrylonitrile-butadiene rubber, polychloroprene rubber,
Polyisoprene rubber, acrylic rubber, polysulfuric rigid rubber,
Fluorine rubber, urethane rubber, silicone rubber, ABS resin and the like can be mentioned. These may be used alone,
Two or more kinds may be used in combination.

As the liquid phase resin, an uncured solution of the thermosetting resin can be used. Specific examples of such a liquid phase resin include, for example, an uncured epoxy oligomer and an amine-based curing agent. And the like. As the liquid phase rubber, for example, an uncured solution of the rubber can be used.

When the photosensitive resin composition is prepared using the liquid resin or the liquid rubber, the heat-resistant resin matrix and the soluble substance are not homogeneously compatible (that is, separated into phases). First, it is necessary to select these substances. By mixing a heat-resistant resin matrix and a soluble substance selected according to the above criteria, a state in which "islands" of liquid-phase resin or liquid-phase rubber are dispersed in the "sea" of the heat-resistant resin matrix Alternatively, a photosensitive resin composition in which "islands" of a heat-resistant resin matrix are dispersed in a "sea" of a liquid phase resin or a liquid phase rubber can be prepared.

After the photosensitive resin composition in such a state is cured, the roughened surface can be formed by removing the "sea" or "island" liquid phase resin or liquid phase rubber. .

Examples of the acid used as the roughening liquid include phosphoric acid, hydrochloric acid, sulfuric acid, and organic acids such as formic acid and acetic acid. Among these, it is preferable to use an organic acid. This is because when the roughening treatment is performed, the metal conductor layer exposed from the via hole is hardly corroded. As the oxidizing agent, for example, an aqueous solution of chromic acid, an alkaline permanganate (such as potassium permanganate), or the like is desirably used. As the alkali, an aqueous solution of sodium hydroxide, potassium hydroxide or the like is desirable.

In the present invention, when the above-mentioned inorganic particles, the above-mentioned metal particles and the above-mentioned resin particles are used, the average particle size is desirably 10 μm or less. Further, in particular, by using a mixture of coarse particles having a relatively large average particle diameter and fine particles having a relatively small average particle diameter having an average particle diameter of less than 2 μm, the electroless plating film Dissolved residues can be eliminated, the amount of palladium catalyst under the plating resist can be reduced, and a shallow and complicated roughened surface can be formed. By forming such a complicated roughened surface, a practical peel strength can be maintained even on a shallow roughened surface.

By combining the above coarse particles and fine particles, a shallow and complicated roughened surface can be formed because the coarse particles used are coarse particles having an average particle size of less than 2 μm. The anchor formed even when dissolved is removed becomes shallow, and the particles to be removed are formed by the mixture of coarse particles having a relatively large particle diameter and fine particles having a relatively small particle diameter. The roughened surface becomes complicated. In this case, the particle diameter used is coarse and the average particle diameter is less than 2 μm, so that roughening does not proceed too much and no voids are generated, and the formed interlayer resin insulating layer has excellent interlayer insulating properties. ing.

The coarse particles have an average particle diameter of more than 0.8 μm and less than 2.0 μm, and the fine particles have an average particle diameter of 0.1 to 0.1 μm.
Preferably, it is 0.8 μm. In this range, the depth of the roughened surface is approximately Rmax = about 3 μm. In the semi-additive method, not only the electroless plating film is easily removed by etching, but also the Pd catalyst under the electroless plating film is easily removed. And a practical peel strength of 1.0 to 1.3 kg / cm can be maintained.

The content of the organic solvent in the resin composition for forming a roughened surface is desirably 10% by weight or less. When applying the resin composition for forming a roughened surface, a roll coater, a curtain coater, or the like can be used.

(3) After the resin composition layer for forming a roughened surface formed in the above (2) is dried to a semi-cured state, an opening for a via hole is provided. When the resin composition layer for forming a roughened surface is dried, the thickness of the resin composition layer on the conductor circuit pattern is small, and the thickness of the interlayer resin insulation layer on the plane layer having a large area is large. In addition, since irregularities are often generated in the interlayer resin insulating layer due to irregularities in the conductor circuit and the portion where the conductor circuit is not formed, the interlayer resin insulating layer is pressed with heating using a metal plate or a metal roll. It is desirable to planarize the surface of the insulating layer.

The opening for the via hole is formed by performing a developing process after exposing the resin composition layer for forming a roughened surface to ultraviolet rays or the like. In the case of performing the exposure and development processing, a portion corresponding to the opening for the via hole described above is provided.
A photomask (preferably a glass substrate) on which a black circle pattern is drawn is placed in a state where the side on which the black circle pattern is drawn is in close contact with the resin composition layer for forming a roughened surface.
Develop.

4) Next, the resin composition layer for forming a roughened surface is cured to form an interlayer resin insulating layer, and the interlayer resin insulating layer is roughened. In the roughening treatment, at least one soluble substance selected from inorganic particles, resin particles, metal particles, rubber particles, a liquid-phase resin, and a liquid-phase rubber, which is present on the surface of the interlayer resin insulating layer, is treated with the above-described acid. By using a roughening liquid such as an oxidizing agent or an alkali. The depth of the roughened surface is 1 to 5
About μm is desirable.

(5) Next, the roughened substrate is immersed in an aqueous solution of persulfate to perform an etching process, so that the roughened surface of the conductor circuit exposed in the via hole opening is fragile. Remove the layer. Thereafter, a catalyst nucleus is applied to the wiring substrate having the interlayer resin insulating layer roughened. It is desirable to use a noble metal ion or a noble metal colloid for providing the catalyst nucleus, and generally, palladium chloride or a palladium colloid is used. Note that it is desirable to perform a heat treatment to fix the catalyst core. Palladium is preferred as such a catalyst core.

(6) Next, an electroless plating film is formed on the entire roughened surface. As the electroless plating solution, the above-described electroless plating solution of the present invention is used. As the plating solution composition,
For example, EDTA (50 g / l), copper sulfate (10 g
/ L), HCHO (6 ml / l), NaOH (10
g / l). The thickness of the electroless plating film is preferably from 0.1 to 5 μm, more preferably from 0.5 to 3 μm.

(7) Then, a photosensitive resin film (dry film) is laminated on the electroless plating film, and a photomask (preferably a glass substrate) on which a plating resist pattern is drawn is brought into close contact with the photosensitive resin film. A plating resist pattern is formed by mounting, exposing, and developing. (8) Next, electrolytic plating is applied to the portion where the plating resist is not formed to form a conductor circuit and a via hole. here,
As the above-mentioned electrolytic plating, it is desirable to use copper plating, and its thickness is desirably 1 to 20 μm.

(9) Further, after the plating resist is removed, the electroless plating film is formed with a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate, ammonium persulfate, ferric chloride, and cupric chloride. Dissolve and remove to form an independent conductor circuit. Thereafter, the palladium catalyst core is dissolved and removed with chromic acid or the like. (10) Next, a roughened surface is formed on the surface of the conductor circuit. In this case, the etching solution containing the cupric complex and the organic acid described above is allowed to act in the coexistence of oxygen, and the surface of the conductor circuit is roughened. To form a surface.

(11) Next, an interlayer resin insulating layer is formed on the substrate by using the above-described resin composition for forming a roughened surface by the same method as described above.

(12) Next, the steps (3) to (9) are repeated to provide a further upper layer conductive circuit, on which a flat conductive pad or via hole functioning as a solder pad is formed. Finally, by forming a solder resist layer, a solder bump, and the like, the manufacture of the multilayer printed wiring board is completed. Although the following method is based on the semi-additive method, a full additive method may be adopted.

[0063]

The present invention will be described in more detail below. Example 1 A. Preparation of photosensitive resin composition Cresol novolak type epoxy resin (Nippon Kayaku Co., Ltd.
34 parts by weight of a resin solution prepared by dissolving 25% acrylate having a molecular weight of 2500) in diethylene glycol dimethyl ether (DMDG), 2 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), and caprolactone-modified Tris as a photosensitive monomer (Acroxyethyl) isocyanurate (Toagosei Co., Ltd., trade name: Aronix M)
325) 4 parts by weight, 2 parts by weight of benzophenone (manufactured by Kanto Kagaku) as a photopolymerization initiator, 0.2 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer, photosensitive monomer (Nippon Kayaku Co., Ltd.) KAYAMER PM-21) 10
Parts by weight, and after mixing 15 parts by weight of epoxy resin particles (Polymer Pole manufactured by Sanyo Chemical Co., Ltd.) having an average particle size of 1.0 μm and 10 parts by weight having an average particle size of 0.5 μm,
The mixture was mixed while adding 30.0 parts by weight of N-methylpyrrolidone (NMP), and the viscosity was 7 Pa · s with a homodisper stirrer.
And kneaded with three rolls to prepare a photosensitive resin composition (interlayer resin insulating material).

B. Manufacturing method of printed wiring board (1) 0.6 mm thick glass epoxy resin or BT
The starting material was a copper-clad laminate in which 18 μm copper foils 8 were laminated on both sides of a substrate 1 made of (bismaleimide triazine) resin (see FIG. 1A). First, the copper-clad laminate was drilled, subjected to electroless plating, and etched in a pattern to form a lower conductor circuit 4 and through holes 9 on both surfaces of the substrate 1.

(2) Through-hole 9 and lower conductor circuit 4
After the substrate on which was formed was washed with water and dried, NaOH (1
0 g / l), NaClO ₂ (40 g / l), Na ₃ PO
₄ A blackening treatment using an aqueous solution containing (16 g / l) as a blackening bath (oxidizing bath), NaOH (19 g / l), NaB
A reduction treatment was performed using an aqueous solution containing H ₄ (5 g / l) as a reduction bath, and roughened surfaces 4 a and 9 a were formed on the entire surface of the lower conductor circuit 4 including the through holes 9 (see FIG. 1 (b)). ).

(3) A resin filler 10 containing a bisphenol F type epoxy resin is applied to one surface of the substrate using a roll coater to fill the space between the lower conductor circuits 4 or the inside of the through holes 9 and heat and dry. After that, the other surface was similarly filled with the resin filler 10 between the conductor circuits 4 or in the through holes 9 and dried by heating (FIG. 1).
(C)).

(4) One surface of the substrate after the treatment of the above (3) is subjected to belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku) to form the surface of the inner layer copper pattern 4 and the through holes 9. Polishing was performed so that the resin filler 10 did not remain on the land surface, and then buffing was performed to remove scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate. Then, at 100 ° C for 1 hour, at 120 ° C for 3 hours, at 150 ° C
For 1 hour and a heat treatment at 180 ° C. for 7 hours to cure the resin filler 10.

In this way, the surface portion of the resin filler 10 formed in the through-hole 9 and the portion where the conductor circuit is not formed and the surface of the lower conductor circuit 4 are flattened, and the resin filler 10 and the side surfaces of the lower conductor circuit 4 are flattened. 4a is firmly adhered through the roughened surface, and the inner wall surface 9a of the through hole 9 and the resin filler 10
Was obtained, thereby obtaining an insulating substrate firmly adhered through the roughened surface (see FIG. 1D).

(5) The substrate is washed with water and acid-degreased, and then soft-etched. Then, an etching solution is sprayed on both surfaces of the substrate by spraying, so that the surface of the lower conductor circuit 4, the land surface of the through hole 9 and the inner wall are formed. Thus, roughened surfaces 4a and 9a having a roughness of 3 to 4 μm were formed on the entire surface of the lower conductor circuit 4 (see FIG. 2A). As an etching solution, 10 parts by weight of an imidazole copper (II) complex,
A mixture of 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride and 78 parts by weight of ion-exchanged water was used.

(6) The photosensitive resin composition prepared by the method described in A above is applied to both surfaces of the substrate after the treatment of the above (5) using a roll coater, and left in a horizontal state for 20 minutes. After drying at 60 ° C for 30 minutes,
A photosensitive resin composition layer (interlayer resin insulating layer) 2 having a thickness of μm was formed (see FIG. 2B). Further, a polyethylene terephthalate film was stuck on the photosensitive resin composition layer 2 via an adhesive.

(7) On both surfaces of the substrate 1 on which the photosensitive resin composition layer 2 was formed in (6), a 5 μm thick
A 5 mm thick soda lime glass substrate on which a black circle is drawn is brought into close contact with the photosensitive resin composition layer 2 on the side where the black circle is drawn, and is exposed at 3000 mJ / cm ² intensity using an ultra-high pressure mercury lamp, and then DMDG. Spray developed with solution, 100μ
A via hole opening 6 having a diameter of m was formed. After this,
Heat treatment was performed at 100 ° C. for 1 hour and at 150 ° C. for 5 hours to form a 50 μm-thick interlayer resin insulating layer 2 having a via hole opening 6 having excellent dimensional accuracy corresponding to a photomask film (FIG. 2). (C)). The roughened layer was partially exposed in the opening serving as the via hole.

(8) The substrate in which the via hole opening 6 was formed was placed in an aqueous solution of ammonium persulfate having a concentration of 70 g / l.
By immersing for a minute, the fragile layer existing in the portion of the conductor circuit where the roughened surface was formed was removed. The roughness of the roughened surface is 2-3 μm
This means that the fragile layer of about 1 μm has been removed. After washing with water, the surface of the interlayer resin insulation layer 2 is roughened (5 μm in depth) by further immersing in a chromic acid aqueous solution to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulation layer 2. It was immersed in a neutralizing solution (manufactured by Shipley) and then washed with water (see FIG. 2D). further,
By applying a palladium catalyst (manufactured by Atotech) to the surface of the roughened substrate, catalyst nuclei were attached to the surface of the interlayer resin insulating layer 2 and the inner wall surface of the via hole opening 6.

(9) Next, the substrate was immersed in an electroless copper plating aqueous solution having the following composition to form a 3 μm-thick electroless copper plating film 12 on the entire rough surface (see FIG. 3A). ). [Electroless plating aqueous solution] EDTA 50 g / l Copper sulfate 10 g / l HCHO 6 ml / l NaOH 10 g / l α, α'-bipyridyl 80 mg / l Polyethylene glycol (PEG) 0.1 g / l [None Electroplating conditions] 30 minutes at a liquid temperature of 70 ° C

(10) A commercially available photosensitive dry film is bonded to the electroless copper plating film 12 by thermocompression bonding, and a 5 mm-thick soda lime in which a plating resist non-formed portion is drawn as a mask pattern by a chromium layer. After exposing the glass substrate to 110 mJ / cm ² with the chromium layer formed side in close contact with the photosensitive dry film,
It was developed with 0.8% sodium carbonate to provide a plating resist 3 having a thickness of 20 μm (see FIG. 3B).

(11) Then, electrolytic copper plating was performed under the following conditions to form an electrolytic copper plating film 13 having a thickness of 15 μm (see FIG. 3C). [Electroplating aqueous solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive 1 ml / l (Capparaside GL, manufactured by Atotech Japan) [Electroplating conditions] Current density 1.2 A / dm ² hours 30 minutes Temperature Room temperature

(12) After the plating resist 3 is peeled and removed with 5% KOH, the electroless plating film 12 under the plating resist 3 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and the electroless plating is performed. Copper plating film 12 and electrolytic copper plating film 1
A conductor circuit (including the via hole 7) 5 made of 3 and having a thickness of 18 μm was formed. Further, the substrate was immersed in a solution containing 800 g / l chromic acid for 1 to 2 minutes to remove the palladium catalyst remaining on the surface of the interlayer resin insulating layer 2 (FIG. 3D).
reference).

(13) By repeating the above steps (5) to (12), an upper interlayer resin insulating layer and a conductive circuit were further formed, and a multilayer wiring board was obtained. (14) Next, diethylene glycol dimethyl ether (D
MDG) to a concentration of 60% by weight.
Cresol novolak epoxy resin (Nippon Kayaku)
46.67 parts by weight of a photosensitizing oligomer (molecular weight: 4000) in which 50% of epoxy groups are acrylated, and 80% by weight of a bisphenol A type epoxy resin dissolved in methyl ethyl ketone (trade name: Epicoat, manufactured by Yuka Shell Co., Ltd.) 1001) 6.67 parts by weight, also bisphenol A
6.67 parts by weight of a type epoxy resin (trade name: Epicoat E-1001-B80, manufactured by Yuka Shell Co., Ltd.), imidazole curing agent (trade name: 2E4MZ-CN, manufactured by Shikoku Chemicals Co., Ltd.)
1.6 parts by weight, a photosensitive monomer (KAY manufactured by Nippon Kayaku Co., Ltd.)
AMER PM-21) 6 parts by weight, a leveling agent composed of an acrylate polymer (manufactured by Kyoei Chemical Co., trade name:
Polyflow No. 75) Take 0.36 parts by weight in a container,
A mixed composition was prepared by stirring and mixing, and 2.0 parts by weight of Irgacure I-907 (manufactured by Ciba Geigy) as a photopolymerization initiator and DE as a photosensitizer were added to the mixed composition.
0.2 parts by weight of TX-S (manufactured by Nippon Kayaku Co., Ltd.), DMDG0.
By adding 6 parts by weight, the viscosity is 1.4 ± at 25 ° C.
A solder resist composition adjusted to 0.3 Pa · s was obtained. The viscosity was measured using a B-type viscometer (manufactured by Tokyo Keiki Co., Ltd., D
VL-B) and at 60 rpm, the rotor No. 4,
In the case of 6 rpm, the rotor No. According to 3.

(15) Next, the above-mentioned solder resist composition is applied to both sides of the multilayer wiring board in a thickness of 20 μm,
After performing a drying process at 20 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a 5 mm thick soda lime glass substrate on which the pattern of the solder resist opening is drawn by the chrome layer is placed on the side where the chrome layer is drawn. Is adhered to a solder resist layer and exposed to ultraviolet light of 1000 mJ / cm ² , and D
The film was developed with an MTG solution to form an opening having a diameter of 200 μm. Further, the solder resist layer is further cured by heating at 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours, and has an opening. A 20 μm solder resist layer 14 was formed.

(16) Next, the substrate on which the solder resist layer 14 was formed was replaced with nickel chloride (30 g / l), sodium hypophosphite (10 g / l), and sodium citrate (10 g / l).
g / l) in the electroless nickel plating solution with pH = 5.
This was immersed for 0 minutes to form a nickel plating layer 15 having a thickness of 5 μm in the opening. Further, the substrate was subjected to potassium gold cyanide (2 g / l), ammonium chloride (75 g / l),
It was immersed in an electroless plating solution containing sodium citrate (50 g / l) and sodium hypophosphite (10 g / l) at a temperature of 93 ° C. for 23 seconds to form a 0.03 μm thick nickel plating layer 15 on the nickel plating layer 15. A gold plating layer 16 was formed.

(17) Thereafter, a solder paste is printed in the openings of the solder resist layer 14 and reflowed at 200 ° C. to form solder bumps (solder bodies) 17.
A multilayer wiring printed board having the solder bumps 17 was manufactured (see FIG. 5C).

Comparative Example 1 A multilayer printed wiring board was manufactured in the same manner as in Example 1 except that in the step (8), the etching treatment was not performed using an aqueous solution of ammonium persulfate.

With respect to the printed wiring boards thus manufactured in Example 1 and Comparative Example 1, a heat cycle test in which the heat cycle of holding at −55 ° C. for 30 minutes and then holding at 125 ° C. for 30 minutes was repeated 1,000 times was performed. Then, the connection at the via hole portion was examined by cross-cutting and microscopic observation. As a result, in the multilayer printed wiring board according to Example 1, the via hole was firmly connected to the rough surface of the lower conductive circuit, and no destruction or the like was observed, but in the multilayer printed wiring board according to Comparative Example 1, In this case, destruction was observed at the connection between the via hole and the lower conductive circuit.

[0083]

As described above, according to the method for manufacturing a printed wiring board of the present invention, it is possible to manufacture a multilayer printed wiring board in which connection reliability of via holes is ensured even under severe conditions.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views showing a part of a manufacturing process of a multilayer printed wiring board according to the present invention.

FIGS. 2A to 2D are cross-sectional views showing a part of a manufacturing process of the multilayer printed wiring board of the present invention.

FIGS. 3A to 3D are cross-sectional views illustrating a part of the manufacturing process of the multilayer printed wiring board according to the present invention.

FIGS. 4A to 4C are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.

FIGS. 5A to 5C are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.

[Explanation of symbols]

 Reference Signs List 1 substrate 2 interlayer resin insulation layer (adhesive layer for electroless plating) 4 lower conductor circuit 4a roughened surface 5 upper conductor circuit 7 via hole 8 copper foil 9 through hole 9a roughened surface 10 resin filler 14 solder resist layer ( Organic resin insulation layer) 15 Nickel plating film 16 Gold plating film 17 Solder bump

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 5E343 AA02 AA17 BB24 BB71 CC22 CC46 CC50 DD33 DD43 EE52 EE58 GG04 5E346 AA06 AA12 AA15 AA43 BB01 CC09 CC31 CC58 DD03 DD22 EE31 EE35 EE38 FF02 FF15 GG02 GG15 GG15 GG15

Claims (6)

[Claims] After forming a conductor circuit and performing a roughening treatment, the conductor circuit subjected to the roughening treatment is covered with an interlayer resin insulating layer, and a process of forming a via hole opening is repeated to thereby perform insulation. In a method for manufacturing a multilayer printed wiring board in which a conductive circuit comprising a plurality of layers sandwiching an interlayer resin insulating layer is formed on a functional substrate, a via hole opening is formed in the interlayer resin insulating layer and then exposed from the via hole opening. A method of manufacturing a multilayer printed wiring board, characterized in that a roughened surface of a conductive circuit is etched. 2. The method for producing a multilayer printed wiring board according to claim 1, wherein said etching treatment is performed using an aqueous solution of persulfate or a mixed aqueous solution of hydrogen peroxide and sulfuric acid. 3. The method for producing a multilayer printed wiring board according to claim 1, wherein the roughening treatment of the conductor circuit is performed by causing an etchant comprising a cupric complex and an organic acid to act in the presence of oxygen. 4. An interlayer resin insulating layer is formed on a substrate on which a conductor circuit having a roughened surface is formed, a via hole opening is formed in the interlayer resin insulating layer, and a conductor is placed in the via hole opening. In the multilayer printed wiring board formed to constitute the via hole, the roughened surface of the conductor circuit exposed from the via hole opening is subjected to an etching process for forming the roughened surface, and then further roughened. A multilayer printed wiring board characterized in that an etched surface is subjected to an etching treatment. 5. An interlayer resin insulating layer is formed on a substrate on which a conductor circuit having a roughened surface is formed, a via hole opening is formed in the interlayer resin insulating layer, and a conductor is placed in the via hole opening. In the multilayer printed wiring board formed to form the via hole, the roughness of the roughened surface of the conductor circuit exposed from the via hole opening is smaller than the roughness of the roughened surface of the other portion. Characteristic multilayer printed wiring board. 6. The multilayer printed wiring according to claim 5, wherein the roughness of the roughened surface of the conductor circuit exposed from the via hole opening is smaller by 0.5 to 5 μm than the roughness of the roughened surface of the other portion. Board.