200834818 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種製作應變矽互補式金氧半導體電晶 體的方法。 【先前技術】 隨著半導體製造技術越來越精密，積體電路也發生重大 ⑩ 的交革，使仔電腦的運异性能和存儲容量突飛猛進，並帶 動周邊産業迅速發展。而半導體產業也如同摩爾定律所預 測的’以每18個月增加一倍電晶體數目在積體電路上的速 度發展著，同時半導體製程也已經從1999年的0·18微米、 2001年的0.13微米、2003年的90奈米（〇.〇9微米），進入 到2005年65奈米（〇·〇65微米製程）。 而隨著半導體製程進入深次微米時代，在半導體製，程中 ® 如何利用一高應力薄膜來提升金氧半導體(MOS)電晶體的 驅動電流(drive current)已逐漸成為一熱門課題。目前利用 高應力薄膜來提升金氧半導體電晶體的驅動電流可概分為 兩方面·其一係應用在鎳化砍專金屬梦化物形成前的多晶 矽應力層（poly stressor);另一方面則係應用在鎳化矽等金 屬石夕化物形成後之接觸洞蚀刻停止層（contact etch stop 、 layer，CESL) 〇 200834818 請參照第1圖至第6圖，第1圖至第6圖為習知製作雙 接觸洞I虫刻停止層於一應變石夕互補式金氧半導體電晶體之 示意圖。如第1圖所示，首先提供一個以淺溝隔離(shall〇w trench isolation，SU) 106 區隔出 NM〇S 電晶體區 1〇2 以及 PM0S電晶體區104的半導體基底100，且&NM〇s電晶 體區102及PM0S電晶體區1〇4上各具有一閘極結構。其 中，NMOS閘極結構包含一 NM〇s閘極1〇8以及一設於 NM0S閘極108與半導體基底· i⑽之間的閘極介電層114, PM0S閘極結構則包含一 PM〇s閘極11〇以及一設置於各 閘極與半導體基底1〇〇之間的閘極介電層114。接著於 NM0S閘極1〇8與PM0S閘極11〇的側壁表面各別形成一 由石夕乳層與氮化/5夕層所構成的襯墊層1 1 2。 然後進行一離子佈植製程，以於NMOS閘極108與 PM0S閘極11〇周圍的半導體基底1〇〇中各形成一源極/汲 極區域Π 6與117。緊接著進行一快速升溫退火製程，利用 900至1050 C的尚溫來活化源極/汲極區域116與117内的 摻雜質，並同時修補在各離子佈植製程中受損之半導體基 底1〇〇表面的晶格結構，以kNM0S電晶體區1〇2形成一 NM0S電晶體丨32以及於PM〇s電晶體區}〇4形成一 pM〇s 電晶體134。此外，亦可視產品需求及功能性考量，另於 源極//及極區域1 1 6、1 1 7與各閘極1⑽、1 1 〇之間分別形成 幸莖換雜汲極(LDD)118與119。 8 200834818 w 接著於半導體基底100表面濺鍍一金屬層（圖未示），例 如一鎳金屬層，然後進行一快速升溫退火(rapid thermal anneal，RTA)製程，使金屬層與NMOS閘極108、PMOS閘 極110以及源極/汲極區域116與117接觸的部分反應成矽 化金屬層115，完成自行對準金屬石夕化物製程(salicide)。200834818 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of fabricating a strained 矽 complementary MOS semiconductor crystal. [Prior Art] With the increasingly sophisticated semiconductor manufacturing technology, the integrated circuit has also undergone a major 10-transition, which has enabled the computer's transmission performance and storage capacity to advance rapidly, and has driven the rapid development of surrounding industries. The semiconductor industry, as predicted by Moore's Law, has grown at a rate that doubles the number of transistors per 18 months on integrated circuits, and the semiconductor process has also been 0.18 micron in 1999 and 0.13 in 2001. Micron, 90 nm in 2003 (〇.〇9 μm), entered the 65 nm in 2005 (〇·〇 65 micron process). As the semiconductor process enters the deep submicron era, how to use a high stress film to enhance the drive current of a metal oxide semiconductor (MOS) transistor has become a hot topic in semiconductor manufacturing. At present, the use of high-stress films to enhance the driving current of MOS transistors can be divided into two aspects. One is applied to poly-poly stressors before the formation of nickel metallurgical metal dreams; on the other hand, Contact etching stop layer (contact etch stop, layer, CESL) after formation of a metal ruthenium compound such as nickel ruthenium 〇 200834818 Please refer to Fig. 1 to Fig. 6, and Fig. 1 to Fig. 6 are conventionally produced. A schematic diagram of a double contact hole I insect stop layer in a strained stone complementary MOS transistor. As shown in Fig. 1, first, a semiconductor substrate 100 is provided which is separated by a shallow trench isolation (SU) 106 region from the NM〇S transistor region 1〇2 and the PMOS transistor region 104, and & Each of the NM〇s transistor region 102 and the PMOS transistor region 1〇4 has a gate structure. The NMOS gate structure includes a NM 〇s gate 1 〇 8 and a gate dielectric layer 114 disposed between the NMOS gate 108 and the semiconductor substrate · i (10), and the PM0S gate structure includes a PM 〇 s gate A gate 11 and a gate dielectric layer 114 disposed between each gate and the semiconductor substrate 1A. Next, a liner layer 11 2 composed of a glacial layer and a nitride layer is formed on the sidewall surfaces of the NM0S gate 1〇8 and the PMOS gate 11〇. An ion implantation process is then performed to form a source/drain region Π 6 and 117 in each of the semiconductor substrate 1 〇 around the NMOS gate 108 and the PMOS gate 11 。. A rapid thermal annealing process is then performed, using a temperature of 900 to 1050 C to activate the dopants in the source/drain regions 116 and 117, and simultaneously repairing the damaged semiconductor substrate 1 in each ion implantation process. The lattice structure of the surface of the crucible is formed by forming a NM0S transistor 丨32 in the kNM0S transistor region 1〇2 and a pM〇s transistor 134 in the PM〇s transistor region 〇4. In addition, depending on the product requirements and functional considerations, the source// and the pole regions 1 16 and 1 1 7 and the gates 1 (10) and 1 1 〇 respectively form a fortunate stem-to-drain (LDD) 118 With 119. 8 200834818 w Next, a metal layer (not shown), such as a nickel metal layer, is sputtered on the surface of the semiconductor substrate 100, and then a rapid thermal anneal (RTA) process is performed to make the metal layer and the NMOS gate 108, The portions of the PMOS gate 110 and the source/drain regions 116 and 117 are in contact with the deuterated metal layer 115 to complete the self-alignment of the metallization salicide.
在去除未反應之金屬層之後，接著進行一電漿增強化學 血 氣相沈積（PECVD)製程，以於NMOS電晶體區102與PMOS 電晶體區104的矽化金屬層115表面形成一高張應力薄膜 (high tensile stress film) 120。然後如第2圖所示，進行一光 阻塗佈、曝光以及顯影製程，以形成一圖案化光阻層122 並覆蓋整個NMOS電晶體區102。 如第3圖所示，接著進行一蝕刻製程，利用圖案化光阻 層122當作遮罩來去除pm〇S電晶體區104上的高張應力 鲁 薄膜丨2〇,以形成 < 高張應力薄膜120於NMOS電晶體132 表面。然後移除覆蓋於NMOS電晶體區102的圖案化光阻 層 122 〇 如第4圖所示，接著進行另一電漿增強化學氣相沈積製 程，以於NMOS電晶體區102與PMOS電晶體區1〇4上形 成一鬲壓應力薄膜(high compressive stress film)124。其 中’高壓應力薄膜124於NMOS電晶體區i〇2係覆蓋於高 200834818 ，應力；1膜12〇表面而在PM〇s電晶體區刚則係直接覆 蓋於PM〇S電晶體134上。 厂、後如第5圖所示，進行―光阻塗佈、曝光以及顯影製 ^以形成一圖案化光阻層126並覆蓋整個pM〇s電晶體 區104。接著進行一蝕刻製程，利用圖案化光阻層當 作遮罩來去除NM0S電晶體區1〇2的高壓應力薄膜。 Φ 隨後再去除覆蓋於PM〇K晶體區1〇4的圖案化光阻層 126’以形成-高壓應力薄膜124於pM〇s電晶體134表面 以及一尚張應力薄膜120於]sfMOS電晶體132表面。 如第6圖所示’接著覆蓋—層間介電層 dielectric，ILD) 128於高張應力薄膜12〇與高壓應力薄膜 124表面。然後利用-圖案化光阻層（圖未示）作為触刻遮 罩，將高張應力薄臈120與高壓應力薄膜124最為一接觸 ⑩酿刻停止層，並進行-非等向性_製程，以於層間介 電層128中形成複數個接觸洞13〇，作為與其他元件連接 的橋樑。 值得注意的是，習知在製作雙接觸洞蝕刻停止層時，通 常係先形成一圖案化光阻層於一主動區域上，然後進行一 , 侧製程’利用該圖案化光阻層當作遮罩來直接去除位於 另一主動區域的應力層，如第2圖至第3圖所示。此方式 200834818 •雖可快速去除覆蓋於電晶體上的應力層，但在大部分的情 況下容易過渡侵触位於應力層下的石夕化金屬層，進而影響 後續製作接觸洞時與其他元件連接的良率。 除此之外，習知在利用圖案化光阻層來餘刻覆蓋於 職OS電晶體表面的高張應力薄膜與覆蓋於pM〇s電晶體 表面的高壓應力薄膜時不容易精準定義兩個應力層之間的 • 區域，因此容易發生重疊的現象，如第5圖所示。以45奈 米製程為例，如果高張應力薄膜與高壓應力薄膜堆疊的寬 度小於30奈米，在後續剝除光阻(strip)或進行濕式清洗 ^ ’便會發生脫落(peeling)的問題。然而，如高張應力薄 犋與高壓應力薄膜堆疊的寬度大於3〇奈米，雖町避免脫落 7ξ|，但在進行後續製程，例如去除圖案化光降廣、形 成層間介電層或進行化學機械研磨時，則容易廣生斷裂的 % 現象並造成元件毀損（defect)。 【發明内容】 八因此本發明之主要目的係提供一種製作應變矽彡補式 无氧半導體電晶體的方法，來解決上述習知之問癍。 、、根據本發明之申請專利範圍，係揭露一種製作應變矽互 ‘ 補式金氧半導體電晶體的方法。首先，提供一半導髏基底， ‘ 挪導體基底具有H動區域用以製備_第〆電晶 200834818 鹘、至少-第二主動區域用以製備一第二電晶體、以及一 !形成至少-第一閘極結構於該第一主動區域上與至少一 第-閘極結構於該第二主動區域上以及形成該第_電晶體 ，源極與汲極區域與該第二電晶體之雜與汲極區域。接 著依序形成-第-_停止層、—第—應力層以及一第二 餘刻#止層於该第-電晶體、該第二電晶體及該絕緣結構 表面。然後形成—第—圖案化光阻層於該第-主動區域之 該第二餘刻停止層上，並進行U刻製程，去除該第 二主動區域之該第二蝕刻停止層與部分該第一應力層。隨 後移除该第一圖案化光阻層，並進行一第二韻刻製程，利 用該第一主動區域之該第二蝕刻停止層當作遮罩去除該第 二主動區域剩餘之該第一應力層及部分該第一蝕刻停止 層。進一步地，在第二主動區第一蝕刻停止層上形成一第 二應力層，其中第一應力層與第二應力層之間具有一間 隙，以完成該應變矽互補式金氧半導體電晶體。 本發明另揭露一種應變矽互補式金氧半導體電晶體，其 包含有一半導體基底，該半導體基底具有一第一主動區域 用以製備一第一電晶體、一第二主動區域用以製備一第二 電晶體、以及一絕緣結構設於該第一主動區域與該第二主 動區域之間；一第一電晶體，設於該第一主動區域上方； 一第二電晶體，設於該第二主動區域上方；―第一名虫刻停 12 200834818 止層，設於該第一電晶體與該第二電晶體上；一第一應力 層，設於該第一電晶體上；一第二蝕刻停止層，設於該第 一電晶體上並覆蓋該第一應力層；一第二應力層，設於該 第二電晶體上，以及一第三触刻停止層，設於該第二電晶 體上並覆蓋該第二應力層，其中第一應力層與第二應力層 之間具有一間隙（gap)。 φ 本發明係先依序形成一第一蝕刻停止層、一應力層以及 一第二蝕刻停止層於一第一電晶體與第二電晶體上，然後 覆蓋一圖案化光阻層於第一電晶體上，並利用該圖案化光 阻層來去除第二電晶體上方的第二飿刻停止層與部分應力 層。接著移除該圖案化光阻層，然後利用該第一電晶體上 的第二I虫刻停止層當作遮罩來去除第二電晶體上剩餘的應 力層。換句話說，相較於習知僅利用圖案化光阻層來一次 鲁去除另^電晶體上的應力層，本發明係揭露一種兩段式的 姓刻方法’並藉由此方法來控制餘刻製程的強度 (magnitude)，以改善f知採用單—钱刻步驟時因|法控制 :製程的力量而容易過渡侵钱基底表面之矽化金屬層的 _，本發明另於製作雙接觸顺刻停程 去除嘱力薄膜與高厂堅應力薄膜連接的部八，^r 張應力薄膜與高塵應力薄臈之間形成一距離:進而改^ 13 200834818 知覆蓋應力層時容易因應力層的堆疊而造成脫落與元件毀 損的問題。 【實施方式】 請參照第7圖至第13圖，第7圖至第13圖為本發明製 作雙接觸洞蝕刻停止層於一應變矽互補式金氧半導體電晶 體之示意圖。如第7圖所示，首先提供一個以淺溝隔離 (shallow trench isolation，STI)206 區隔出 NMOS 電晶體區 202以及PMOS電晶體區204的半導體基底200，且各 NMOS電晶體區202及PMOS電晶體區204上各具有一閘 極結構。其中，NMOS閘極結構包含一 NMOS閘極208以 及一設於NMOS閘極208與半導體基底200之間的閘極介 電層214，PMOS閘極結構則包含一 pM〇s閘極21〇以及 一 a又置於各閘極與半導體基底2〇〇之間的閘極介電層 214。接著於NMOS閘極208與PMOS閘極210的侧壁表 面各別形成-切氧層錢切騎構成的襯墊層212。 然後進行-離子佈植製程，以於nm〇s問極2〇8與 PMOS閘極2H)周圍的半導體基底細中各形成一源祕 極區域216與。217。緊接著進行一快速升溫退火製程，利 用900至1050 C的w溫來活化源極/汲極區域216幻口产 的摻雜質’並同時修補在各離子佈植製程中受損之半導體 基底表面的晶格結構，以於難〇s電晶體區202形成 200834818 • 一 NM〇S電晶體232以及於PMOS電晶體區204形成一 PM0S電晶體234。此外，亦可視產品需求及功能性考量， 另於源極/汲極區域216、217與各閘極208、210之間分別 形成一輕摻雜汲極(LDD)218與219。 接著於半導體基底200表面濺鍍一金屬層（圖未示），例 如一鎳金屬層，然後進行一快速升溫退火(RTA)製程，使金 ⑩ 屬層與NMOS閘極208、PMOS閘極210以及源極/汲極區 域216與217接觸的部分反應成矽化金屬層215，完成自 行對準金屬石夕化物製程(salicide)。After removing the unreacted metal layer, a plasma enhanced chemical vapor deposition (PECVD) process is then performed to form a high tensile stress film on the surface of the NMOS transistor region 102 and the PMOS region 104 of the PMOS transistor region 104. Tensile stress film) 120. Then, as shown in Fig. 2, a photoresist coating, exposure and development process is performed to form a patterned photoresist layer 122 and cover the entire NMOS transistor region 102. As shown in FIG. 3, an etching process is then performed to remove the high tensile stress film 丨2〇 on the pm〇S transistor region 104 by using the patterned photoresist layer 122 as a mask to form a <high tensile stress film. 120 is on the surface of the NMOS transistor 132. The patterned photoresist layer 122 overlying the NMOS transistor region 102 is then removed, as shown in FIG. 4, followed by another plasma enhanced chemical vapor deposition process for the NMOS transistor region 102 and the PMOS transistor region. A high compressive stress film 124 is formed on 1〇4. The 'high-voltage stress film 124 is covered in the NMOS transistor region i〇2 to the high 200834818, stress; 1 film 12〇 surface and directly over the PM〇S transistor 134 in the PM〇s transistor region. After the factory, as shown in Fig. 5, photoresist coating, exposure, and development are performed to form a patterned photoresist layer 126 and cover the entire pM〇s transistor region 104. Then, an etching process is performed to remove the high-pressure stress film of the NM0S transistor region 1〇2 by using the patterned photoresist layer as a mask. Φ subsequently removes the patterned photoresist layer 126' overlying the PM〇K crystal region 1〇4 to form a high-voltage stress film 124 on the surface of the pM〇s transistor 134 and a tensile stress film 120 on the sfMOS transistor 132. surface. As shown in Fig. 6, 'subsequent covering-interlayer dielectric layer, ILD 128' is applied to the surface of the high tensile stress film 12 and the high voltage stress film 124. Then, using a patterned photoresist layer (not shown) as a etch mask, the high tensile stress enthalpy 120 is in contact with the high pressure stress film 124, and the stop layer is formed, and an anisotropic process is performed to A plurality of contact holes 13A are formed in the interlayer dielectric layer 128 as a bridge connecting the other elements. It is worth noting that, in the fabrication of the double contact hole etch stop layer, a patterned photoresist layer is usually formed on an active region, and then a side process is performed, using the patterned photoresist layer as a mask. The cover directly removes the stress layer located in the other active area, as shown in Figures 2 through 3. This method 200834818 • Although the stress layer covering the transistor can be quickly removed, in most cases, it is easy to transition and invade the layer of the metal layer under the stress layer, thereby affecting the connection with other components when the contact hole is subsequently formed. Yield. In addition, it is not easy to accurately define two stress layers when using a patterned photoresist layer to cover the high tensile stress film covering the surface of the OS transistor and the high voltage stress film covering the surface of the pM〇s transistor. The area between the two is therefore prone to overlap, as shown in Figure 5. Taking the 45 nm process as an example, if the width of the high tensile stress film and the high pressure stress film stack is less than 30 nm, the problem of peeling occurs in the subsequent stripping of the strip or wet cleaning. However, if the width of the high tensile stress thin film and the high pressure stress film stack is greater than 3 nanometers, although the town avoids falling off 7ξ|, it is subjected to subsequent processes, such as removing patterned light, forming an interlayer dielectric layer or performing chemical mechanical processing. When grinding, it is easy to widen the phenomenon of cracking and cause component damage. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a method of fabricating a strain-compensated oxygen-free semiconductor transistor to solve the above-mentioned problems. According to the patent application scope of the present invention, a method of fabricating a strained ‘ complementary MOS transistor is disclosed. First, a semi-conducting substrate is provided, 'the Norconductor substrate has a H-moving region for preparing _ Dielectric crystal 200834818 鹘, at least - a second active region for preparing a second transistor, and a! forming at least - first a gate structure on the first active region and at least one first gate structure on the second active region and forming the first transistor, the source and drain regions and the second transistor region. Then, a -th stop layer, a first stress layer, and a second residual layer are sequentially formed on the first transistor, the second transistor, and the surface of the insulating structure. Forming a first-patterned photoresist layer on the second residual stop layer of the first active region, and performing a U-etch process to remove the second etch stop layer and the first portion of the second active region Stress layer. And then removing the first patterned photoresist layer and performing a second rhyme process, using the second etch stop layer of the first active region as a mask to remove the remaining first stress of the second active region a layer and a portion of the first etch stop layer. Further, a second stress layer is formed on the first etch stop layer of the second active region, wherein the first stress layer and the second stress layer have a gap to complete the strain 矽 complementary MOS transistor. The present invention further discloses a strain 矽 complementary MOS transistor comprising a semiconductor substrate having a first active region for preparing a first transistor and a second active region for preparing a second a first transistor and a second active region are disposed between the first active region and the second active region; a first transistor is disposed above the first active region; and a second transistor is disposed at the second active region Above the area; "first insect stop 12 200834818 stop layer, located on the first transistor and the second transistor; a first stress layer, disposed on the first transistor; a second etch stop a layer disposed on the first transistor and covering the first stress layer; a second stress layer disposed on the second transistor, and a third etch stop layer disposed on the second transistor And covering the second stress layer, wherein a gap is formed between the first stress layer and the second stress layer. The invention firstly forms a first etch stop layer, a stress layer and a second etch stop layer on a first transistor and a second transistor, and then covers a patterned photoresist layer on the first electrode. The patterned photoresist layer is used on the crystal to remove the second etch stop layer and the partial stress layer above the second transistor. The patterned photoresist layer is then removed and the remaining stressor layer on the second transistor is removed using the second I-insertion stop layer on the first transistor as a mask. In other words, the present invention discloses a two-stage method of surname etching by using only a patterned photoresist layer to remove the stress layer on the other transistor. Incremental process intensity (magnitude), in order to improve the use of the single-money engraving step, due to the control of the process: the power of the process is easy to transition into the surface of the deuterated metal layer of the substrate, the invention is also made in double contact The stoppage removes the joint between the force film and the high-strength stress film, and forms a distance between the ^r tensile stress film and the high dust stress thinness: further change 13 13348818 It is easy to cover the stress layer when covering the stress layer The problem of falling off and component damage. [Embodiment] Referring to Figs. 7 to 13, Fig. 7 through Fig. 13 are schematic views showing the fabrication of a double contact hole etch stop layer in a strain 矽 complementary MOS semiconductor crystal. As shown in FIG. 7, first, a semiconductor substrate 200 is provided with a shallow trench isolation (STI) 206 region separating the NMOS transistor region 202 and the PMOS transistor region 204, and each NMOS transistor region 202 and PMOS are provided. Each of the transistor regions 204 has a gate structure. The NMOS gate structure includes an NMOS gate 208 and a gate dielectric layer 214 disposed between the NMOS gate 208 and the semiconductor substrate 200. The PMOS gate structure includes a pM 〇s gate 21 and a A is again placed on the gate dielectric layer 214 between each gate and the semiconductor substrate 2A. Next, a pad layer 212 composed of a cut-off layer is formed on the sidewalls of the NMOS gate 208 and the PMOS gate 210. An ion implantation process is then performed to form a source secret region 216 between the semiconductor substrate surrounding the nm 〇s pole 2 〇 8 and the PMOS gate 2H). 217. A rapid thermal annealing process is then performed, using a w temperature of 900 to 1050 C to activate the doping of the source/drain region 216 and simultaneously repair the surface of the damaged semiconductor substrate in each ion implantation process. The lattice structure is such that the hard s transistor region 202 forms 200834818 • an NM 〇S transistor 232 and a PMOS transistor 234 is formed in the PMOS transistor region 204. In addition, depending on product requirements and functional considerations, a lightly doped drain (LDD) 218 and 219 are formed between the source/drain regions 216, 217 and the gates 208, 210, respectively. Then, a metal layer (not shown), such as a nickel metal layer, is sputtered on the surface of the semiconductor substrate 200, and then a rapid thermal annealing (RTA) process is performed to make the gold 10 layer and the NMOS gate 208, the PMOS gate 210, and The portions of the source/drain regions 216 and 217 are in contact with the deuterated metal layer 215 to complete the self-alignment of the metallization salicide.
在去除未反應之金屬層之後，接著覆蓋一第一餘刻停止 層224於NMOS電晶體232、PMOS電晶體234及淺溝p 離206表面，然後進行一電漿增強化學氣相沈積(pEcvi^ 製程，以於第一蝕刻停止層224表面形成—高張應力薄膜 (high tensile stress film)226。緊接著形成一第二餘刻 ^ 止 228於高張應力薄膜226上，以完成一個三層纟士構。其中 第一I虫刻停止層224與第二姓刻停止層228可為氧化石夕 構成，而高張應力薄膜226則係為氮化石夕所構成 然後如第8圖所示’進行一光阻塗佈、曝光以及顯影制 程’以形成一圖案化光阻層230並覆蓋整個NM〇s電:衣 區202。接著進行一触刻製程，利用圖案化光阻屛Μ ^ ^ 當 15 200834818 " 作遮罩來去除覆蓋於PMOS電晶體區204的第二蝕刻停止 層228與部分高張應力薄膜22έ。 如第9圖所示，隨後去除圖案化光阻層23〇，並利用 NMOS電晶體區202的第二蝕刻停止層228當作遮罩來去 除PMOS電晶體區204剩餘的高張應力薄膜226及部分第 一蝕刻停止層224。根據本發明之較佳實施例，本發明可 ⑩於進行餘刻製程時通入ι甲烧((：明作為一控制媒介 (control agent) ’使餘刻製程容易停止於第一餘刻停止層以 上0 ，如第10圖所不’接著進行另__電漿增強化學氣相沈積 乂私以於:NMOS電晶體區202與pmos電晶體區204上 形成μ壓應力薄膜(hlgh 〇〇卿^_咖⑽film)236。其 :,應力薄膜236於難〇s電晶體區2〇2係覆蓋於第 一敍刻停止層228表面，而在PMOS電晶體區204則係直 接覆蓋於第—㈣停止層224上。緊接著再形成一第三韻 刻停止層238於㈣應力薄膜236表面。 ,:然後如第11圖所示’進行一光阻塗佈、曝光以及顯影 衣矛王以形成圖棄化光阻層24〇並覆蓋整個電晶 體區2〇4。接著進行-蝕刻製程，利用圖案化光阻詹240 田作遮罩來去除覆蓋於Nm〇s電晶體區搬的第三敍刻停 16 200834818 止層238與部分高壓應力薄膜236。 如第12圖所示’隨後去除圖案化光阻層240，並進行一 蝕刻製程，利用PMOS電晶體區204的第三蝕刻停止層238 當作遮罩來去除NMOS電晶體區202剩餘的高壓應力薄膜 236及NMOS電晶體區202與？]\4〇8電晶體區204交界處 的高壓應力薄膜236，以於NMOS電晶體區202的高張應 力薄膜226與PMOS電晶體區204的高壓應力薄膜236之 間形成一開口 246。其中開口 246之兩侧邊會因為經過單 次或二次餘刻程序而有不同的傾斜度，在本實施例中特別 是緊鄰PMOS電晶體204之側邊會呈現一斜面（單次触 刻）。如同先前所述，本發明可於進行蝕刻製程時通入氣甲 烧(CH3F)當作一控制媒介(control agent)，使餘刻製程容易 停止於第一蝕刻停止層224上。舉例來說，本發明可於進 行蚀刻製程時通入氟甲烧，然後去除高張應力薄膜226與 南壓應力薄膜236之間部分的第一餘刻停止層224來留下 约20埃厚度的第一餘刻停止層224，並藉由殘留的第一韻 刻分止層224來保遵PM0S電晶體區204的半導體基底2〇〇 表面的矽化金屬層215。 如第13圖所示，接著覆蓋一層間介電層（inter七yer dielectric，ILD)242於NMOS電晶體區202的第二蝕刻停止 層228與PMOS電晶體區204的第三餘刻停止層238表面。 17 200834818 然後利用一圖案化光阻層（圖未示）作為蝕刻遮罩並進行一 非等向性蝕刻製程，去除部分層間介電層242、第二蝕刻 停止層228、第三蝕刻停止層238、高張應力薄膜220高壓 應力薄膜236及第一蝕刻停止層224，以於層間介電層242 中形成複數個接觸洞244，作為與其他元件連接的橋樑。 此外，根據本發明之另一實施例，本發明又可於NM〇s 電晶體區形成三層結構後另於PMOS電晶體區的PMOS電 曰曰體上直接覆蓋一高壓應力薄膜以形成一雙層結構。舉例 來况，本發明可於NM〇s電晶體232上形成由第一蝕刻停 止層224、——尚張應力薄膜226以及一第二姓刻停止層228 所構成的二層結構後直接覆蓋一高壓應力薄膜236於 NMOS電晶體區202的第二蝕刻停止層228與PM〇s電晶 體區204㈣第一触刻停止層224上。然後進行一钮刻製程， 去除NMOS電晶體區202與PM〇s電晶體區2〇4交界處的 同壓應力薄膜236，以於NMOS電晶體區202的高張應力 溥膜226與PMOS電晶體區204的高壓應力薄膜236之間 形成一開口 246,且開口 246係暴露出第一蝕刻停止層224 的表面，如第14圖所示。此做法即完成本發明的另一實施 例，亦即在顧OS電晶體232上形成一由第一姓刻停止層 224、高張應力薄膜226以及第二蝕刻停止層228所構成的 三層結構，然後在PMOS電晶體234上則形成一由第一蝕 刻停止層224及高壓應力薄膜236所構成的雙層結構。隨 18 200834818 、 電日日體232及PMOS電晶體234上形点一 層間介電層與複數個接趨 少成 β 觸，同，在此不另加贅述。值得注咅 的疋，覆蓋於PM0S雷曰騁f ，斤 " 有蚌合in / U體 的弟—關停止層224 錢作過料會被去除，而在此情況下本發明可直 高壓應力薄膜236於PM〇S電晶體234表面來形 成早層結構，此皆屬本發明所涵蓋之範圍。 電曰!較於習知製作應變矽互補式金氧半導體 電曰曰體的方法，本發明係先依序形成一第一姓刻停止芦、 一應力層以及一第二餘刻停止層於-第-電晶體與第：電 曰曰體上’織覆蓋―®案化光阻層於第-電晶體上，並利 用該圖案化光阻層來去除第二電晶體上方的第二蝕刻停止 ^與部分應力層。接著移除該圖案化光阻層，然後利用該 第-電晶體上的第二㈣停止層當作遮罩來去除第二電晶 體上剩餘的應力層。換句話說，相較於習知僅利用圖案化 光阻層來-次去除另一電晶體上的應力層’本發明係揭露 種兩^又式的飿刻方法，並藉由此方法來控制餘刻製程的 強度(magnitude)，以改善習知採用單一蝕刻步驟時因無法 控制敍刻製程的力量而容易過度侵蝕基底表面之秒化金屬 層的問題。 另外，本發明中的另一特徵，如先前之較佳實施例所 述’隶佳形成應力層的順序係先形成應力層於NMos電蓋 19 200834818 ^ 體區，然後再形成於PMOS電晶體區。由於覆蓋在NMOS 電晶體上的矽化金屬層⑼化丨)容易在光阻層去除時被氧 化，因此需先行形成該應力層以保護該矽化金屬層區域。 此外，本發明中的其他較佳實施例還包含有PMOS單 邊的單層結構(只有應力層）與NMOS的三層結構。基於上 述理由，由於NMOS必須先形成該三層結構以保護住矽化 • 金屬層區域，接著形成的PMOS可依照習用的方法形成應 力層，並與NMOS的應力層之間抱持一開口間隙即可。 此外，本發明另於製作雙接觸洞触刻停止層後段製程時 去除高張應力薄膜與高壓應力薄膜連接的部分區域，使高 張應力薄膜與高壓應力薄膜之間形成一距離，進而改善習 知覆蓋應力層時容易因應力層的堆疊而造成脫落與元件毀 才貝的問題。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範. 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第6圖為習知製作雙接觸洞蝕刻停止層於一應變 ^ 矽互補式金氧半導體電晶體之示意圖。 第7圖至第13圖為本發明製作雙接觸洞蝕刻停止層於一應 20 200834818 變石夕互補式金氧半導體電晶體之示意圖。 第14圖為本發明另一實施例製作雙接觸洞蝕刻停止層於 一應變矽互補式金氧半導體電晶體之示意圖。After removing the unreacted metal layer, a first residual stop layer 224 is then overlaid on the surface of the NMOS transistor 232, the PMOS transistor 234, and the shallow trench p 206, and then a plasma enhanced chemical vapor deposition (pEcvi^) is performed. The process is such that a high tensile stress film 226 is formed on the surface of the first etch stop layer 224. A second residual 228 is formed on the high tensile stress film 226 to complete a three-layered gentleman structure. Wherein the first I-spot stop layer 224 and the second-spot stop layer 228 may be composed of oxidized stone eve, and the high tensile stress film 226 is formed of nitrite and then perform a photoresist as shown in FIG. The coating, exposing, and developing processes are performed to form a patterned photoresist layer 230 and cover the entire NM〇s electrical: garment region 202. A tangent process is then performed, using patterned photoresist 屛Μ ^ ^ when 15 200834818 " A mask is applied to remove the second etch stop layer 228 overlying the PMOS transistor region 204 and a portion of the high tensile stress film 22A. As shown in FIG. 9, the patterned photoresist layer 23 is subsequently removed, and the NMOS transistor region 202 is utilized. Second etch stop layer 22 8 is used as a mask to remove the remaining high tensile stress film 226 and a portion of the first etch stop layer 224 of the PMOS transistor region 204. According to a preferred embodiment of the present invention, the present invention can be used to pass through the invisible process during the engraving process. Burning ((: as a control agent) makes the residual process easy to stop above the first moment stop layer 0, as shown in Figure 10, then proceed with another __ plasma enhanced chemical vapor deposition乂Privately: NMOS transistor region 202 and pmos transistor region 204 form a μ compressive stress film (hlgh 〇〇 ^ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The surface of the first stop stop layer 228 is covered, and the PMOS transistor region 204 is directly over the fourth (four) stop layer 224. A third stop stop layer 238 is then formed on the surface of the (four) stress film 236. , then, as shown in Fig. 11, 'performing a photoresist coating, exposing, and developing the coating spear to form the patterned photoresist layer 24 and covering the entire transistor region 2〇4. Then performing an etching process to utilize Patterned photoresist Jen 240 field mask to remove the cover of the Nm〇s transistor area The third layer is inscribed with a layer 238 and a portion of the high voltage stress film 236. As shown in FIG. 12, 'the patterned photoresist layer 240 is subsequently removed, and an etching process is performed to utilize the third etch stop layer of the PMOS transistor region 204. 238 is used as a mask to remove the high voltage stress film 236 remaining in the NMOS transistor region 202 and the high voltage stress film 236 at the interface of the NMOS transistor region 202 and the ??\4 8 transistor region 204 for the NMOS transistor region 202. An opening 246 is formed between the high tensile stress film 226 and the high voltage stress film 236 of the PMOS transistor region 204. The sides of the opening 246 may have different inclinations due to a single or secondary remnant procedure. In this embodiment, in particular, a side of the PMOS transistor 204 is adjacent to the side of the PMOS transistor 204 (single touch). . As previously described, the present invention can be used as a control agent during the etching process to allow the gas to burn (CH3F) to be applied to the first etch stop layer 224. For example, the present invention can pass a fluoromethyl burn during the etching process, and then remove a portion of the first residual stop layer 224 between the high tensile stress film 226 and the south compressive stress film 236 to leave a thickness of about 20 angstroms. The stop layer 224 is left for a while and the deuterated metal layer 215 of the surface of the semiconductor substrate 2 of the PMOS transistor region 204 is maintained by the remaining first engraving stop layer 224. As shown in FIG. 13, an interlayer dielectric layer (ILD) 242 is then overlying the second etch stop layer 228 of the NMOS transistor region 202 and the third residual stop layer 238 of the PMOS transistor region 204. surface. 17 200834818 Then, a patterned photoresist layer (not shown) is used as an etch mask and an anisotropic etching process is performed to remove portions of the interlayer dielectric layer 242, the second etch stop layer 228, and the third etch stop layer 238. The high tensile stress film 220 and the first etch stop layer 224 form a plurality of contact holes 244 in the interlayer dielectric layer 242 as a bridge connecting the other elements. In addition, according to another embodiment of the present invention, the present invention can form a three-layer structure in the NM〇s transistor region and directly cover a high-voltage stress film on the PMOS electrode body of the PMOS transistor region to form a pair. Layer structure. For example, the present invention can directly form a two-layer structure composed of a first etch stop layer 224, a tensile stress film 226, and a second last stop layer 228 on the NM〇s transistor 232. The high voltage stress film 236 is on the second etch stop layer 228 of the NMOS transistor region 202 and the PM 〇s transistor region 204 (four) first etch stop layer 224. Then, a button etching process is performed to remove the same compressive stress film 236 at the interface between the NMOS transistor region 202 and the PM〇s transistor region 2〇4, so as to the high tensile stress film 226 and the PMOS transistor region of the NMOS transistor region 202. An opening 246 is formed between the high voltage stress films 236 of 204, and the opening 246 exposes the surface of the first etch stop layer 224 as shown in FIG. In this way, another embodiment of the present invention is completed, that is, a three-layer structure composed of a first surname stop layer 224, a high tensile stress film 226, and a second etch stop layer 228 is formed on the OS transistor 232. Then, a two-layer structure composed of the first etch stop layer 224 and the high voltage stress film 236 is formed on the PMOS transistor 234. With the 18 200834818, the electric dipole 232 and the PMOS transistor 234, an interlayer dielectric layer and a plurality of junctions are gradually reduced to β-touch, and the same is not described herein. It is worthy of attention, covering the PM0S Thunder f, the pound " has the in / U body of the brother - off the stop layer 224 money will be removed, and in this case the invention can be straight high pressure stress film 236 is formed on the surface of the PM〇S transistor 234 to form an early layer structure, which is within the scope of the present invention. Electron 曰! Compared with the conventional method for fabricating strain 矽 complementary MOS semiconductor bodies, the present invention sequentially forms a first surname to stop the reed, a stress layer and a second residual stop layer. Forming a photoresist layer on the first transistor and the first transistor, and using the patterned photoresist layer to remove the second etch stop over the second transistor ^ With partial stress layers. The patterned photoresist layer is then removed and the remaining stress layer on the second transistor is removed using the second (four) stop layer on the first transistor as a mask. In other words, the stress layer on the other transistor is removed by using only the patterned photoresist layer as in the prior art. The present invention discloses a two-step etching method, and is controlled by this method. The strength of the process is modified to improve the problem of the conventionally etched metal layer of the substrate surface due to the inability to control the force of the etch process. In addition, another feature of the present invention, as described in the prior preferred embodiment, is that the stress layer is formed in the NMos cap 19 200834818 ^ body region and then formed in the PMOS transistor region. . Since the deuterated metal layer (9) coated on the NMOS transistor is easily oxidized when the photoresist layer is removed, the stress layer needs to be formed first to protect the deuterated metal layer region. In addition, other preferred embodiments of the present invention further comprise a three-layer structure of a PMOS single-sided single-layer structure (only stress layer) and NMOS. For the above reasons, since the NMOS must first form the three-layer structure to protect the germanium metal layer region, the formed PMOS can form a stress layer according to a conventional method and hold an open gap between the NMOS stress layer and the NMOS stress layer. . In addition, the present invention further removes a portion of the high tensile stress film and the high pressure stress film to form a distance between the high tensile stress film and the high pressure stress film during the process of fabricating the double contact hole etch stop layer, thereby improving the conventional covering stress. When the layer is layered, it is easy to cause the problem of falling off and destroying the components due to the stacking of the stress layers. The above is only the preferred embodiment of the present invention, and all changes and modifications made in accordance with the scope of the present application are intended to be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 6 are schematic views showing the fabrication of a double contact hole etch stop layer in a strain 矽 complementary MOS transistor. 7 to 13 are schematic views showing the fabrication of a double contact hole etch stop layer in the present invention 20 200834818. Figure 14 is a schematic view showing another embodiment of the present invention for fabricating a double contact hole etch stop layer in a strain 矽 complementary MOS transistor.
[ 主要元件符號說明】 100 半導體基底 102 NMOS電晶體區 104 PMOS電晶體區 106 淺溝隔離 108 NMOS閘極 110 PMOS閘極 112 襯墊層 114 閘極介電層 115 石夕化金屬層 116 源極/汲極區域 117 源極/ >及極區域 118 輕摻雜没極 119 輕摻雜没極 120 高張應力薄膜 122 圖案化光阻層 124 高壓應力薄膜 126 圖案化光阻層 128 層間介電層 130 接觸洞 132 NMOS電晶體 134 PMOS電晶體 200 半導體基底 202 NMOS電晶體區 204 PMOS電晶體區 206 .淺溝隔離 208 NMOS閘極 210 PMOS閘極 212 襯墊層 214 閘極介電層 215 石夕化金屬層 216 源極/没極區域 217 源極/没極區域 218 輕摻雜没極 219 輕摻雜没極 224 第一#刻停止層 226 高張應力薄膜 21 200834818 228 第二餘刻停止層 230 圖案化光阻層 232 NMOS電晶體 234 PMOS電晶體 236 高壓應力薄膜 238 第三儀刻停止層 240 圖案化光阻層 242 層間介電層 244 接觸洞 246 開口 22[Main component symbol description] 100 semiconductor substrate 102 NMOS transistor region 104 PMOS transistor region 106 shallow trench isolation 108 NMOS gate 110 PMOS gate 112 pad layer 114 gate dielectric layer 115 Shi Xihua metal layer 116 source / drain region 117 source / > and polar region 118 light doped immersion 119 light doped immersion 120 high tensile stress film 122 patterned photoresist layer 124 high pressure stress film 126 patterned photoresist layer 128 interlayer dielectric layer 130 contact hole 132 NMOS transistor 134 PMOS transistor 200 semiconductor substrate 202 NMOS transistor region 204 PMOS transistor region 206. shallow trench isolation 208 NMOS gate 210 PMOS gate 212 pad layer 214 gate dielectric layer 215 Shi Xi Metallization layer 216 source/nomogram region 217 source/drain region 218 lightly doped 219 lightly doped 224 first #刻止层层226 high tensile stress film 21 200834818 228 second residual stop layer 230 Patterned photoresist layer 232 NMOS transistor 234 PMOS transistor 236 High voltage stress film 238 Third etch stop layer 240 Patterned photoresist layer 242 Interlayer dielectric layer 244 Contact hole 246 Opening 22