TWI353038B - Method for fabricating strained-silicon cmos trans - Google Patents

Description

1353038 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for producing strain hard complementary MOS semiconductor crystals. [Prior Art] Iw is shrinking the line width of the semiconductor process, and the size of the m〇s transistor #+ is also constantly moving toward miniaturization. However, when the line width of the semiconductor process has developed to the bottleneck, how to enhance the load Sub-mobility to increase the speed of MOS transistors has become a major issue in the field of semiconductor technology. Among the currently known techniques, MOS transistors using strained silicon as a substrate have been used, which utilize yttrium (5) Ge) crystal constants different from single crystal 矽 (single. crystal Si) to make 矽The bismuth layer is structurally strained to form a strain enthalpy. Since the lattice of the enamel layer is often 〇atticec〇nstant), the ratio of the band structure of the 矽锗 layer changes, and the mobility of the carrier increases, so the speed of the M〇s transistor can be increased. . Referring to Figs. 1 to 4, Figs. 1 to 4 are schematic views showing the fabrication of a strain 矽 complementary MOS transistor. As shown in FIG. 1, first, a semiconductor substrate 1〇〇 separated by an NMOS transistor region 102 and a PMOS transistor region 104 in a shallow trench isolation (STI) 106 region, and each NMOS transistor region is provided. 102 and PMOS. Each of the transistor regions 104 has a gate structure. The NMOS gate junction 7 1353038 includes an NMOS gate 1〇8 and a gate dielectric layer U4 disposed between the NMOS gate 108 and the semiconductor substrate 100. The pm〇S gate structure includes a PMOS. A gate 11A and a gate dielectric layer 114 disposed between the pM〇s gate and the semiconductor substrate 100. Next, a biased sidewall spacer 112 composed of a silicon oxide layer or a nitride layer is formed on the sidewall surfaces of the NM0S gate 108 and the PMOS gate 110, respectively. I then perform an ion implantation process to form a light doping in each of the semiconductor substrate .100 around the NM0S gate 108 and the PM0S gate 110.

Lightly doped drain (LDD) 118 and 119. Then, a sidewall η] is formed on each of the sidewalls of the NMOS gate 108 and the PMOS gate 110. A further ion implantation process is then performed to form source/drain regions 116 and 117 around the sidewalls 113 of the NMOS transistor region 1〇2 and the PM0S. transistor region 104. A rapid rise and temperature annealing process is then performed, using a high temperature of 900 to 1050 ° C to activate the Lu dopant in the source/drain regions 116 and 117, and simultaneously repair the damaged semiconductor in each ion implantation process. The lattice structure of the surface of the substrate 100 forms an NMOS transistor 132 in the NMOS transistor region 〇2 and a PMOS transistor 134 in the PMOS transistor region 〇4. As shown in FIG. 2, the NMOS transistor region 1〇2 and the PMOS are used, and the gate structure of the transistor region 104 is used as a mask for an etching process so as not to be covered by the NMOS gate 108 and the PMOS gate 110. A recess 120 is formed in each of the semiconductor substrates 8 1353038 100. As shown in FIG. 3, a selective stray growth process is subsequently performed to fill the recess 120 of the NMOS transistor region 1 〇2 and the PMOS transistor region 104 with a smectite formed by bismuth telluride. 122. As shown in FIG. 4, a metal layer (not shown) made of nickel is overlaid on the NMOS transistor 132 and the PMOS transistor 134, and then subjected to a rapid thermal anneal (RTA) process. The portion of the metal layer that is in contact with the NMOS gate 108, the PMOS gate 11A, and the source/no-polar regions 116 and 117 reacts with the deuterated metal layer 115 to complete the self-aligned, metallurgical salicide process. It is worth noting that it is customary to fabricate strain-clamped complementary MOS devices. The transistor is usually formed with sidewalls on the sidewalls of the drain, and then in the wake-up OS transistor region and the relative source of the PMOS transistor region. The epitaxial layer is filled in the pole/drain region. Although this method can utilize the antimony telluride in the epitaxial layer to promote the movement of the carrier in the substrate, due to the barrier of the sidewall, the deuteration 11 cannot be particularly close to the channel region in the substrate, and thus the CM〇s electricity cannot be greatly improved. The performance of the crystal. SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a method of fabricating a strained 矽 complementary MOS transistor to improve the above-mentioned problems. 9 1353038 The present invention discloses a method of fabricating a strained-complementary-silicon CMOS transistor. First, the semiconductor substrate has a first active region for preparing a first transistor, at least one second active region for preparing a second transistor, and an insulating structure disposed on the first active region. The second active area

between. Then, at least one first gate structure is formed on the first active region and at least one second gate structure is formed on the second active region. Then forming a first sidewall around the first gate structure and the second gate structure and respectively forming a source and a drain region of the first transistor and a source and a drain of the second electrode Polar area. And subsequently removing the first gate structure and the first sidewall surrounding the second gate structure, covering a cover layer on the first transistor and the second transistor surface, and removing the surface of the second transistor Cover layer. Then performing an etching process for the second transistor

A recess is formed on and around each of the semi-conductors, and then a selective epitaxial growth (SEG) process is performed to form an epitaxial layer in the recess. Finally, the covering layer of the surface of the first transistor is removed. The present invention discloses a method of fabricating a strained-silicone CMOS transistor, which mainly utilizes the application of a stress layer and an epitaxial layer to enhance the overall performance of the NM0S transistor and the PMOS semiconductor. As described in the previous embodiments, the present invention may first cover a stressed mask layer on the NMOS transistor and the PMOS transistor, and then 1353038 remove the stress layer on the PMOS transistor, followed by 'the source of the PMOS transistor.

Improve the hole mobility of the PMOS transistor. In addition, the present invention can remove the sidewalls on the gate structures of the respective transistors before forming the mask layer. This method can make the stress layer on the subsequent cover transistor and the epitaxial layer filled in the substrate closer to the channel region of the transistor, thereby increasing the electron and hole mobility of the transistor. [Embodiment] Please refer to FIGS. 5 to 12, and FIGS. 5 to 12 are diagrams showing the present invention. A schematic diagram of a strain-clamp complementary MOS transistor is fabricated. As shown in FIG. 5, a semiconductor substrate 200 in which a NMOS transistor region 202 and a PMOS transistor region 204 are separated by a shallow trench isolation (STI) region 206 is provided, and each NMOS transistor region 202 and PMOS are provided. Each of the transistor regions 204 has a gate structure. The NMOS gate structure includes an NMOS gate 208 and a gate dielectric layer 214 disposed between the NMOS gate 208 and the semiconductor substrate 200. The PMOS gate structure includes a PMOS gate 210 and a PMOS gate. A gate dielectric layer 214 between the gate 210 and the semiconductor substrate 200. Then, an offset spacer 212 composed of a silicon oxide layer or a nitride layer is formed on the sidewall surfaces of the NMOS gate 208 and the PMOS gate 210, respectively. 1353038 then performing an ion implantation process to form a light doping in the NM〇s gate 2〇8 and the semiconductor substrate 2〇〇 around the PMOS gate 210.

Lightly doped drain (LDD) 218 and 219. Then, a sidewall spacer 2 j3β is formed on the sidewalls of the NM0S gate 208 and the PMOS gate 210, and then another ion implantation process is performed to form a periphery of the NMOS transistor region 202 and the sidewall spacer 213 of the PMOS transistor region 204. A source/drain region 216 and 217. A rapid thermal annealing process is then performed, using a high temperature of 900 to 1050 ° C to activate dopants in the source/drain regions 216 and 217, and simultaneously repairing the surface of the damaged semiconductor substrate 200 in each ion implantation process. The lattice structure is such that the NM0S transistor region 202 forms an NM0S transistor 232 and ? The 1^〇8 transistor region 204 forms a ???8 transistor 234. : As shown in FIG. 6, the sidewall spacers 213 located on the sidewalls of the NM0S gate 208 and the pM〇s gate 210 are then removed. Then, as shown in Fig. 7, a capping layer 220 is overlaid on the NM〇S transistor region 202 and the PMOS transistor 232 and the PMOS transistor 234 of the PMOS transistor region 204. In accordance with a preferred embodiment of the present invention, the masking layer 220 can be a layer of tantalum oxide composed of an oxide or a layer of stress composed of tantalum nitride. For example, the cover layer 220 can be a tensile stress

A high tensile stress film, and the NM0S transistor 232 of the present invention can enhance the electron mobility of the NM0S transistor 12 1353038 . 232 by the high tensile stress film. As shown in FIG. 8, the mask layer 220 located in the PM〇s transistor region 204 is removed, and then the mask layer 220 of the NMOS transistor region 202 and the PMOS gate 210 are used as a mask for an etching process. The top of the pM〇s gate 210 and the source/drain region 217 of the PMOS transistor region 204 each form a recess 224 » as shown in FIG. 9, and then a cleaning process is performed to remove the impurities remaining on the surface of the recess 224' And performing a sdective epitaxial growth (SEG) process to form a stray layer 226 ' in the recess 224. respectively. · As shown in FIG. 10, the surface of the NMOS transistor 232 is removed. Covering layer 220. As shown in Fig. 11, a sidewall 228 is then formed on the sidewall surfaces of the NMOS gate 208 and the PMOS gate 210, respectively. Then, a metal layer (not shown) made of nickel, cobalt, titanium, molybdenum or the like is overlaid on the NM〇s transistor 232 and the PMOS transistor 234, and then subjected to rapid thermal anneal (RTA). The process is such that the metal layer and the portion of the [^1〇8 gate 208, the PMOS gate 210, and the source/j: and the polar regions 216 and 117 are in contact with each other to form a shredded metal layer 215, and the self-aligned metal stone is completed. 13 1353038 . Salicide. As shown in Fig. 12, a contact hole etch stop layer 230 is formed on the NMOS transistor 232 and the PMOS transistor 234, and the I F is continuously subjected to the contact hole process. It is worth noting that the present invention removes the main sidewalls on the sidewalls of the gates when fabricating the strain-clamp complementary MOS Φ conductor transistors, as shown in Figure 6 and then at the source of the PMOS transistor region. In the /thole region, the epitaxial layer is inserted as shown in Figure 9 above. Since there is no sidewall barrier between the epitaxial layer and the channel region, the hole mobility of the PMQS transistor can be greatly increased by the germanium germanium in the epitaxial layer. In addition, while the worm layer is used to enhance the stress on the PMOS transistor, the present invention further covers a high tensile stress and thin 具有 with a tensile effect on the NM 〇s transistor, and thereby enhances the NMOS power by the film. The electron mobility of the crystal. Further, the present invention is not limited to the manufacturing steps previously described, and the present invention can adjust the time points formed by the doped regions or the side walls depending on the requirements of the product. For example, the present invention can form the sidewall 213 on the sidewalls of the gate structures 2〇8, 21〇 after forming the gates 208 and 210 of the NMOS and PMOS and the bias sidewall spacer 212, and directly perform an ion. The implantation process is performed to form the source/drain regions 216 and 217 of the NMOS transistor 232 and the PMOS transistor 234 in the semiconductor substrate 200. Secondly, the present invention can also be formed after the dummy sidewall spacer 212 is formed, and then Pm. The 电s transistor region 204 forms a lightly doped pole 219' and is removed from the mask layer 220 to form a lightly doped drain 218 in the NMOS transistor region 202. In addition, the present invention can be formed in the second sidewall 228. The source/drain regions 216, 217 of the NMOS transistor 232 and the PMOS transistor 234 are then formed. According to a preferred embodiment of the present invention, the above-described process steps can be matched to each other, for example, simultaneously in the same process or This is within the scope of the present invention. Referring to FIGS. 13 to 20, FIGS. 13 to 20 illustrate another embodiment of the present invention for fabricating a strain-clamp complementary metal oxide semiconductor. Schematic diagram of the transistor. As shown in Figure 13, first A semiconductor substrate 300 is provided which is separated by an NMOS transistor region 302 and a PMOS transistor region 304 by shallow trench isolation (STI) 306, and is provided on the NMOS transistor region 302 and the PMOS transistor region 304. Each of the NMOS gate structures includes an NMOS gate 308 and a gate dielectric layer 314 disposed between the NMOS gate 308 and the semiconductor substrate 300. The PMOS gate structure includes a PMOS gate. The gate 310 and a gate dielectric layer 314 are disposed between the PMOS gate 310 and the semiconductor substrate 300. Then, an oxide layer or a tantalum nitride layer is formed on the sidewall surfaces of the NMOS gate 308 and the PMOS gate 310. The offset spacers formed by the layers are 312 ° and then an ion implantation process is performed to form the NMOS gates 308 and 15 1353038 • the semiconductor substrate 300 around the PMOS gate 310. (lightly doped drain, LDD) 318 and 319. Then, a sidewall 3丨3 is formed on the sidewalls of the NM〇s gate 308 and the PMOS gate 310. Then another ion implantation process is performed to facilitate the NM0S transistor. Zone 3〇2 and the sidewall of the PMOS transistor region 304 A source/drain region 316 and 317 are formed around each of 313. A rapid thermal annealing process is then performed to activate the φ dopant in the source/drain regions 316 and 317 using a high temperature of 900 to 1050 °C. At the same time, the lattice structure of the surface of the damaged semiconductor substrate 300 in each ion implantation process is repaired to form an NMOS transistor 332 in the NM〇s transistor region 3〇2 and a pM in the PIyiOS transistor region 3〇4. 〇s transistor 334.

320 and stress layer 322. Then, a patterned photoresist layer (not shown) is used as a buffer layer of the S transistor region 304 to rapidly elevate the annealing process, and the high 1353038 • temperature is used to increase the tensile stress experienced by the channel region of the NMOS transistor. Then, as shown in Fig. 16, the remaining stress layer 322 and the pM〇s gate 310 are used as a mask for the etching process, so that the pM〇s gate 31〇•top and Ρ Ο 电 S transistor A groove 324 is formed in each of the source/drain regions 3丨7 of the region 3 04. ^ As shown in Fig. 17, a cleaning process is then performed to remove some impurities remaining on the surface of the recess 324 and a selective epitaxial growth (SEG) process is performed to form a recess 324. Stupid layer 326. As shown in Fig. 18, the buffer layer 320 and the stress layer .322 located in the nm〇S transistor region 302 are subsequently removed. Subsequently, a shihua metal barrier layer (such as ruthenium as block, SAB) (not shown) can be formed on a portion of the semiconductor substrate 300 and the NMOS transistor 332 and PMOS are not covered by the deuterated metal barrier layer. A deuterated metal layer 315 is formed on the crystal 334 as shown in FIG. In accordance with an embodiment of the present invention, the deuterated metal barrier layer can be formed of a buffer layer and a stress layer as previously described. As previously described, the production of 'Shi Xihua Metal 315 can be covered first - a metal layer (not shown) composed of materials such as recording, recording, enamel, and keying on NM〇s. Transistor and PMOS transistor. Then, a rapid thermal annealing (Γ _ 1353038 thermal anneal, RTA) process is performed to react the metal layer with the NMOS gate 308, the PMOS gate 310, and the source/drain regions 316 and 317 to form a shihua metal layer 315. , complete the self-alignment of the metallization process (salicide). Finally, as shown in FIG. 20, another stress layer may be deposited on the NMOS transistor 332 and the PMOS transistor 334 for product requirements as a contact hole stop stop layer (CESL) 328, which belongs to the present invention. The scope covered.

In summary, the present invention discloses a method for fabricating a strain-filled complementary silicon-based CMOS transistor, which mainly utilizes the application of a stress layer and an epitaxial layer to enhance the NM〇s transistor and The overall performance of a PMOS transistor. As described in the previous embodiments, the present invention may first cover a stress-containing mask layer on the NMOS transistor and the PMOS transistor, and then remove the stress layer on the PM〇s transistor and then on the source of the pM〇s transistor. Grooves are formed in the immersed region and filled with the worm layer, so that the stress layer promotes the electron mobility of the NMOS transistor by tensile stress while using the worm layer to improve the hole mobility of the PM 〇s transistor. . In addition, the present invention can remove the sidewalls on the gate structures before forming the mask layer. This method can make the stress layer on the subsequent cover transistor and the germanium layer filled in the substrate closer to the channel region of the transistor. And further enhance the electronic unit of the transistor 1353038 [Simple description of the drawings] Figures 1 to 4 are schematic diagrams of a strain-complementary MOS transistor fabricated by a conventional method. 5 to 12 are schematic views showing the fabrication of a strain-clamp complementary MOS transistor according to the present invention. 13 to 20 are schematic views showing the fabrication of a strain-clamp complementary MOS transistor according to another embodiment of the present invention. [Major component symbol description] 100 Semiconductor substrate 102 NMOS transistor region 104 PMOS transistor region 106 Shallow trench isolation 108 NMOS gate 110 PMOS gate 112 Bias side wall 113 Side wall sub-114 Gate dielectric layer 115 Shi Xihua metal Layer 116 source/drain region 117 source/drain region 118 lightly doped 119 light doped immersion 120 groove 122 worm layer 132 NMOS transistor 134 PMOS transistor 200 semiconductor substrate 202 NMOS transistor region 204 PMOS transistor region 206 shallow trench isolation 208 NMOS gate 210 PMOS gate 212 offset sidewall 213 sidewall 19 19 gate dielectric layer 215 Shi Xihua metal source source / drain region 217 source / nopole region Lightly doped immersed 219 lightly doped ruthenium cover layer 224 grooved worm layer 228 sidewall contact hole #刻止层层232 NMOS transistor PMOS transistor 300 semiconductor substrate NMOS transistor region 304 PMOS transistor region shallow trench isolation 308 NMOS gate PM0S gate 312 Bias sidewall spacer 314 Gate dielectric layer: Deuterated metal layer 316 Source/drain region Source/drain region 318 Lightly doped bungee light Stress buffer layer 320 layer 324 layer 328 a recess insect crystal touch contact holes engraved stop layer NMOS transistor 334 PMOS transistor 20

Claims (1)

1353038 X. Patent application scope: licon 1. A method for fabricating a _complementary MOS semiconductor (10) ained-silil CMOS) circuit, the financial method comprising the following steps: providing a semiconductor substrate having a semiconductor substrate for preparation - a first transistor, at least a first active region of the Bob & field king, is used for preparing - a first transistor, and a discontinuous · M · pull " VI · from the Λ * 粑 edge structure is provided in the first active region Between the two active regions; forming at least a first-closed-pole structure on the first active region and a second-second gate structure on the second active region; a first closed-pole structure and the periphery of the first-pole structure; 1 respectively forming a source and a secret region of the first-electrode crystal and a source and a gate region of the first-day solar body; removing the first-closed pole structure and the First side around the second pole structure Covering: covering the surface of the first transistor and the second transistor; removing the mask layer on the surface of the second transistor; and performing an etching process on the semiconductor layer for the second gate structure and the periphery Forming a recess in each of the body substrates; a selective epitaxial gr〇wth (SEG) process to shape the n-day layer in each of the grooves; and removing the surface of the first transistor Cover layer. 21 丄 353038 2. The method of claim 1, wherein the method further comprises: "di-first gate dielectric layer; and a first gate of the gate junction, disposed at the first gate 3. The method of claim 1, further comprising: a first gate dielectric layer; and a second gate disposed on the second gate On the dielectric layer. - Interpole junction 4. The method of claim 1 includes a bismuth type metal oxide semiconductor (NMOS) transistor, a bismuth type metal oxide semiconductor (PMOS) transistor. Wherein the first transistor and the second transistor comprise 5. The oxidized ash cover layer as claimed in the patent application. According to the item, the towel_cover layer is 6. Please refer to the patent scope - stress layer. The method of claim 1, wherein the capping layer is 7' as described in claim 6 of the patent application, a tantalum nitride stress layer. /8. The method of claim 6, wherein the stress layer is wherein the stress layer is 22^53038 ‘a high tensile stress film. 9. The method of claim 1, wherein the method further comprises: after forming the cover layer on the surface of the first transistor: • forming a second sidewall on the first gate structure and Surrounding the second gate structure; covering a metal layer on the surface of the first transistor and the second transistor; performing a rapid thermal anneal (RTA) process to the first transistor and the Forming a deuterated metal layer on the second transistor; and removing the unreacted metal layer. 10. The method of claim 9, wherein the method further comprises forming a contact hole to form a contact stop on the first transistor and the second transistor after forming the layer . 11. The method of claim 1, wherein the epitaxial layer comprises bismuth telluride. 12. A method of fabricating a strained-resistive-strained-silicon CMOS transistor, the method comprising the steps of: providing a semiconductor substrate having a first active region for preparing a first electrical a crystal, at least a second active region for preparing a 23 1353038 first transistor, and an active region; the insulating structure is disposed on the first active region and the first forming at least a first gate structure The first active region and the at least one second gate structure are formed on the second active region; and the sidewalls are respectively formed around the first gate structure and the second interpole structure; a source and a drain region of the transistor and a source and a drain region of the second transistor; sequentially covering the buffer layer and the stress layer on the surface of the first transistor and the #% second transistor; The buffer layer and the stress layer on the surface of the second transistor form a recess in each of the semiconductor substrates on and around the second gate structure; Selective epitaxial growth (SEG) to form an epitaxial layer in each of the recesses; and to remove the buffer layer and the stress layer on the surface of the first transistor. The method of claim 12, wherein the first interrogation structure further comprises: a first gate dielectric layer; and a first gate disposed on the first gate dielectric layer on. The method of claim 12, wherein the second gate 24 structure further comprises: a second gate dielectric layer; and a second gate disposed on the second gate dielectric layer on. 1 The method of claim 12, wherein the first electric 曰 匕 contains an iSf type metal oxide semiconductor (NM 〇 s) electro-crystal and the current P * 丨 〆 一 一 电 电 电 电 电t gold gas semiconductor (PMOS) transistor. The method of claim 12, wherein the yttrium oxide buffer layer. The method of claim 12, wherein the stress layer is a bismuth telluride stress layer. The method of claim 12, wherein the stress layer φ is a high tensile stress film. 19. The method of claim 12, wherein the method further comprises: covering the first transistor and the second transistor after removing the mask layer on the surface of the first transistor; Surface; performing a rapid thermal anneal (Rta) process to form a deuterated metal layer on the first transistor and the second transistor. And, 25 1353038, the unreacted metal layer is removed. 20. The method of claim 19, wherein the method further comprises forming a contact hole etch stop layer on the first transistor and the second transistor after forming the germanium metal layer. 21. The method of claim 12, wherein the epitaxial layer comprises bismuth telluride. 22. A method of fabricating a strained 矽 complementary MOS transistor, the method comprising the steps of: providing a semiconductor substrate having a first active region for preparing a -first transistor The at least one second active area is used to prepare a second transistor, and an insulating structure is disposed between the first active area and the first active area; Forming at least one first gate structure on the first active region and at least one second gate structure on the second active region; forming a source and a drain region of the first transistor and the second a source region and a drain region of the Raney body; a cover layer on the surface of the first transistor and the second transistor to remove the mask layer on the surface of the second transistor; a body-etching process to 4 grooves of the base material on and around the second gate structure; 4 26 丄 〜 selective selective growth growth (selective epitaxial growth (SEG) system to form a separate crystal in each of the grooves And removing the cover layer of the surface of the first transistor and the cover layer of the surface of the transistor to form a sidewall adjacent to the (four) structure and the second gate structure. The method of claim 4, wherein the first sigma, the sigma structure further comprises: a first gate dielectric layer; and a first gate disposed at the first gate On the dielectric layer. The second gate 24. The method of claim 22, further comprising: a second gate dielectric layer; and a second gate disposed on the second gate dielectric layer . The first electro-optic crystal and the second electro-optic crystal package 25. The method body according to claim 22, comprising a germanium-type gold-oxide semiconductor (NMOS) transistor, and a germanium-containing metal oxide semiconductor (PMOS) Crystal. Wherein the covering layer is as described in claim 22, which is a niobium oxide covering layer. 27 〇 / 38 / · If you want to apply the method described in Item 22, the cover layer is a stress layer. ^ For example, in the middle of the material, the stress layer is a tantalum nitride stress layer. The method of claim 27, wherein the stress layer is a high tensile stress film. 30. The method of claim 22, wherein the method further comprises: covering a metal layer on the first sidewall structure and the second gate structure a transistor and the surface of the second transistor; performing a rapid thermal anneal (RTA) process to form a metal layer on the first transistor and the second transistor; and removing the The metal layer of the reaction. 31. The method of claim 30, wherein the method further comprises forming a contact hole stop layer on the first transistor and the second transistor after forming the germanium metal layer. 32. The method of claim 22, wherein the epitaxial layer package 28 1353038 comprises a strontium fossil. Η—, 圊: