200814864 九、發明說明： •【發明所屬之技術領域】 本發明係有關於一種測試線路佈設方法，更詳而& 之，係有關-種佈設電性連接於相連之電路板與測試^路 板間的測試用訊號線之方法。 【先前技術】 按，瓜製造電路板之廠商，例如，以常見之主機板 (Mother Board，MB)來說，為確保所生產之主機 _好之品'諸性，均會在產品_前，於該主機=預= 些供檢測其產品特性之待測元件，並將主機板上之各個待 測元件對應電性連接於除錯測試（Debug)電路板之多個測 試接點，以使該測試電路板能針對主機板進行各種除錯測 試（如：元件參數測試、產品功能測試等），藉由除錯測試 而偵測出所有可能之錯誤，以做為進行改善之根據。 請參閱第1圖，在習知技術中，測試電路板12係以 肇共板方式聯結於待測之主機板丨〇，該測試電路板12及主 機板10間設有分界標示u。該主機板1〇上具有複數驅 動端101a、l〇2a、103a及與其分別對應之接收端1〇lb、 l〇2b、l〇3b ;而該測試電路板12上具有複數對應於該等 驅動端 101a、l〇2a、103a 及接收端 l〇ib、i〇2b、103b 之測試接點121、122、123。 佈設測試用訊號線之方法係自主機板上之驅動端 l〇la、l〇2a、l〇3a分別引出並佈設測試用訊號線i〇1A、 102A、103A，並電性連接至與各該驅動端i〇la、1〇2a、 5 19319 200814864 103a相對應之測試接點121、122、123上；且自上述接 .收端101b、102b、l〇3b上亦分別引出並佈設測試用訊號 線101B、102B、103B’並電性連接至與各該接收端、 102b、103b所相對應之測試接點121、122、123上，使 該驅動端 101a、102a、103a 及接收端 i〇ib、102b、103b 为別糟由该專測试用訊號線1 〇 1A、1 〇 2 A、10 3 A、1 〇 1B、 102B、1 〇3B相互電性連接於對應之測試接點121、122、 123上。如此，則電路板10上之各驅動端1〇la、1〇2a、 _ 103a及接收端l〇lb、l〇2b、103b與相對應之測試電路板 12上的測试接點121、12 2、12 3，得以透過該等測試用訊 號線 101A、102A、103A 及 101B、102B、103B 而形成完整 之導通迴路，俾以該測試電路板12對主機板1〇進行除錯 測試，以檢驗其品質特性。 惟’上述測試用訊號線之佈設方式存在有以下缺失： §測減電路板12對主機板1 〇測試完畢後，若電路板1 〇 義係無品質瑕疵且需要使用該電路板1〇時，便不再需要共 板聯結於該電路板1〇之測試電路板12,必需沿著設於該 測試電路板12及主機板1〇間之分界標示u予以切割（例 如採用V-cut技術），自電路板1〇及測試電路板〗2之頂 層切割掉部分厚度板材後，再將該測試電路板12沿著該 分界標示11折斷以脫離該電路板1 〇。 於折斷該測試電路板12後，前述測試用訊號線 101A、l〇2A、103A 及 101B、102B、103B 亦被從中切斷。 由於電路板10上之驅動端l〇la、l〇2a、103a與接收端 6 19319 200814864 101b、102b、103b係透過該等測試用訊號線1〇1A、1〇2A、 ‘ 103A及101B、102B、103B而分別電性連接至測試電路板 12上之測試接點121、122、123，因此，將使該電路板 10上的驅動端101a、102a、l〇3a與對應之接收端i〇ib、 102b、103b間之電性連接線路形成斷路。 因此，於後續使用該電路板1 〇前必須先對該電路板 10進行重新佈線，以修復中斷之電性連接線路，使該驅 動端101a、102a、103a重新電性連接於對應之接收端 _ l〇lb、102b、103b。然，重新佈線需耗費相當長的工作時 間與製程成本，故效率較低。 因此，如何克服上述習知技術之缺失，進而提供一種 =試線路佈設方法，以使佈設在電路板上之驅動端及接收 端間之訊號線具獨立性’避免因折斷測試電路板而導致電 路板上之驅動端與接收端間之電性連接線路中斷，並省去 =重新佈線製程而增加之卫時及製程成本，以提高效率， 實已成爲亟待解決之課題。 【發明内容】 繁於上述習知技術之缺失，本發明之主要目的在於 =種測職路佈設方法，以佈設電性連接於共板相連的 =板及賴電路㈣之測制訊號線，輕佈設於電路 斷2端及接收端間之訊號線路具獨立性，避免因折 號線板而導致電路板上之驅動端與接收端間之訊 本發明之另一目的係在於提供一種測試線路佈設方 19319 200814864 、法，俾提升電路板之電性連接品質。 本4明之又-目的在於提供一種測試線路佈 法，俾降低產品之製造成本。 °又方 為達上述目的及其他目的，本發明係提供— 路佈設方法，係用於佈設電性連接於共板相連的電 測，電路板之間的測試用訊號線，其中，該電路板上且= 數量相對應之複數驅動端及接 1 八有 今右斜庙缸《 牧队碲昍这測武電路板上則 叹有對應數1之複數測試接點，該賴線路佈設方 =康驅動端及接收端之對應關係設定起始點及二 !，：= =點及終點之設定於該電路板上佈設複數訊 電性連接相對應之各該驅動端與接收端；以及分別 佈a又自各该訊號線引出測 連接…一 分別對應電性 妾及測式電路板上所對應之測試接點。 上述職線路之佈設方法復可包括預先設定該電路 參 :::駆動端、接收端及該測試電路板之測試接點間之對應 上述電路板與測試電路板之間係具有一分界標示，以 供該測試電路板於測試完電路板後，可沿該分界標示將該 測试電路板折斷以脫離電路板。該分界標示係為一折邊劃 痕，但並不以此為限，其亦可例如為分界畫線。 上述測試用訊號線係佈設於該電路板及測試電路板 之底層：則共廠商配合置製程需要而予以切割(例如採用 V-cut或其他切割方式），自該電路板及測試電路板之頂 層切割掉部分厚度板材時，*會損及佈測試魏號線，而 19319 8 200814864 使該測試用訊號線保持電性連接之完整性，俾以該測試電 ♦‘路板對電路板進行除錯測試（Debug)工作。 再者，本發明之測試線路佈設方法，其技術特徵係於 電路板上之驅動端與其對應之接收端之間佈設訊號線，藉 由該訊唬線電性連接該驅動端與接收端，並自該訊號線上 引出並佈設測試用訊號線，以電性連接至驅動端與接收端 於測試電路板上所對應之測試接點。藉此，以使佈設在電 路板上之線路具獨立性，避免因折斷測試電路板而導致電 _路板上之驅動端與接收端間之訊號線路中斷，並省去因重 新佈線製程而增加之工時及製程成本，以提高效率。 【實施方式】 以下藉由具體實例說明本創作之實施方式，熟悉此技 蟄之人士可由本說明書所揭示之内容輕易地瞭解本創作 之其他優點與功效。 請麥閱第2A圖及第2B圖，係為本發明之測試線路佈 _設方法示意圖，本發明之測試線路佈設方法係可搭載於一 佈線軟體中，藉由該佈線軟體於設計一線路時，佈設電性 連接於共板相連的電路板2〇與測試電路板22之間的測試 用訊號線。 如第2A圖所示，該電路板2〇上具有複數驅動端 201a、202a、203a及該等驅動端分別對應之接收端2〇1卜 202b、203b，而該測試電路板22係對應於該等驅動端 201a、202a、203a及接收端201b、2〇2b、別扑具有複數 測試接點22卜222、223。且該測試電路板22係以共板 9 19319 200814864 方式聯結於電路板20，該電路板20與測試電路板22之 間設有一分界標示21，以因應後續製程之需要，而可沿 該分界標示21以V_cut或其他切割方式，自電路板20 及測試電路板22之頂層切割掉部分厚度板材後，再將該 測試電路22板沿著該分界標示21折斷以脫離該電路板 20。 該電路板20係例如為主機板（Mother Board，MB)，該 驅動端 20la、202a、203a 及接收端 201b、202b、203b _係例如為電子元件、晶片及其他線路等，該分界標示21 係為一折邊劃痕，但並不以此為限，其亦可例如一分界晝 線0 於電路板20上佈設測試用訊號線之步驟包括：藉由 佈線软體預先設定該電路板20上之驅動端2019/、202a、 203a及接收端201b、202b、203b與該測試電路板20上 之測試接點221、222、223間之對應關係，因設定對應關 0係之方式係為習知佈線軟體已有之技術，故在此不再贅 述；再將該等驅動端201a、202a、203a及對應之接收端 201b、202b、203b分別設定為電性連接於驅動端與接收 端間之訊號線的起始點及終點，並藉由佈線軟體根據起始 點及終點之設定，於電路板20上佈設電性連接於該驅動 端 201a、202a、203a 與對應之接收端 201b、202b、203b 間之訊號線201、202、203。其中，該等訊號線201、202、 203係佈設於電路板20上，詳而言之，該等訊號線201、 202、203均佈設於該分界標示21臨近於該電路板20之 10 19319 200814864 一侧0 ^ 如此，電路板20上之驅動端201a、202a、203a及所 對應之接收端201b、202b、203b，即可藉由上述之訊號 線201、202、203而相互電性連接，並形成完整且獨立的 訊號傳輸迴路。 請參閱第2B圖，藉由佈線軟體自上述驅動端201a、 202a、203a與對應之接收端201b、202b、203b間之訊號 線201、202、203上分別引出並佈設測試用訊號線201A、 _ 202A、203A以電性連接至驅動端201a、202a、203a與接 收端201b、202b、203b於測試電路板上所對應之測試接 點221、222、223。如此，該測試電路板22上之測試接 點221、222、223即電性連接於電路板20上之驅動端 201a、202a、203a 及接收端 201b、202b、203b。200814864 IX. Description of the invention: • [Technical field to which the invention pertains] The present invention relates to a method for laying a test circuit, and more particularly, and related to the arrangement of the electrical connection to the connected circuit board and the test board The method of testing the signal line. [Prior Art] According to the manufacturer of the circuit board, for example, in the case of the common motherboard (Mother Board, MB), in order to ensure the production of the host _ good product, all will be in front of the product _ The host=pre-testing the components to be tested for detecting the characteristics of the product, and electrically connecting each component to be tested on the motherboard to a plurality of test contacts of the debug test board, so that the host The test board can perform various debugging tests (such as component parameter test, product function test, etc.) on the motherboard, and all possible errors are detected by the debug test as a basis for improvement. Referring to FIG. 1 , in the prior art, the test circuit board 12 is coupled to the motherboard to be tested in a common mode, and a boundary mark u is disposed between the test circuit board 12 and the main board 10. The motherboard 1 has a plurality of driving ends 101a, 110a, 103a and receiving terminals 1?lb, l2b, l3b corresponding thereto; and the test circuit board 12 has a plurality corresponding to the driving Terminals 101a, 102a, 103a and test terminals 121, 122, 123 of the receiving ends l〇ib, i〇2b, 103b. The method for routing the test signal line is to take out the test signal lines i〇1A, 102A, 103A from the driving terminals l〇la, l〇2a, l〇3a on the motherboard, and electrically connect to each of them. The test terminals 121, 122, 123 corresponding to the driving terminals i〇la, 1〇2a, 5 19319 200814864 103a; and the test signals are respectively extracted and arranged from the receiving ends 101b, 102b, l3b The wires 101B, 102B, 103B' are electrically connected to the test contacts 121, 122, 123 corresponding to the receiving ends, 102b, 103b, so that the driving terminals 101a, 102a, 103a and the receiving end i〇ib 102b, 103b are electrically connected to the corresponding test contacts 121, 122 by the dedicated test signal lines 1 〇 1A, 1 〇 2 A, 10 3 A, 1 〇 1B, 102B, 1 〇 3B, 123 on. Thus, the driving terminals 1〇1a, 1〇2a, _103a and the receiving ends l〇1b, l〇2b, 103b on the circuit board 10 and the corresponding test contacts 121, 12 on the test circuit board 12 2, 12 3, through the test signal lines 101A, 102A, 103A and 101B, 102B, 103B to form a complete conduction loop, the test circuit board 12 for the motherboard 1〇 debug test to verify Its quality characteristics. However, there are the following shortcomings in the layout of the above test signal lines: § After the test board 12 has tested the motherboard 1 ,, if the board 1 has no quality and needs to use the board 1 ,, Therefore, the test circuit board 12 that is commonly connected to the circuit board 1 is no longer needed, and must be cut along the boundary mark u disposed between the test circuit board 12 and the motherboard 1 (for example, using V-cut technology). After the partial thickness of the board is cut from the top layer of the circuit board 1 and the test board 2, the test board 12 is broken along the boundary mark 11 to be separated from the board 1 . After the test circuit board 12 is broken, the test signal lines 101A, 102A, 103A, and 101B, 102B, and 103B are also cut off therefrom. Since the driving terminals l〇la, l〇2a, 103a and the receiving end 6 19319 200814864 101b, 102b, 103b on the circuit board 10 pass through the test signal lines 1〇1A, 1〇2A, '103A and 101B, 102B 103B is electrically connected to the test contacts 121, 122, 123 on the test circuit board 12, respectively, so that the drive terminals 101a, 102a, l3a on the circuit board 10 and the corresponding receiving end i〇ib The electrical connection lines between 102b and 103b form an open circuit. Therefore, the circuit board 10 must be re-routed before the subsequent use of the circuit board 1 to repair the interrupted electrical connection line, so that the driving end 101a, 102a, 103a is electrically connected to the corresponding receiving end _ L〇lb, 102b, 103b. However, rewiring takes a considerable amount of work time and process cost, so it is less efficient. Therefore, how to overcome the above-mentioned shortcomings of the prior art, and further provide a = test circuit layout method, so that the signal line disposed between the driving end and the receiving end of the circuit board is independent 'avoiding the circuit caused by breaking the test circuit board The electrical connection between the driving end and the receiving end of the board is interrupted, and the elimination of the re-wiring process and the increase of the maintenance time and the process cost to improve the efficiency have become an urgent problem to be solved. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, the main purpose of the present invention is to devise a method for laying a test route, and to arrange a signal line electrically connected to a common board and a circuit (four). The signal line disposed between the broken end of the circuit and the receiving end is independent to avoid the signal between the driving end and the receiving end of the circuit board. Another object of the present invention is to provide a test circuit layout. Fang 19319 200814864, law, 俾 improve the electrical connection quality of the circuit board. The purpose of this is to provide a test line layout that reduces the manufacturing cost of the product. In order to achieve the above and other objects, the present invention provides a method for laying a road for electrically connecting a test connected to a common board, and a test signal line between the boards, wherein the board On the same = the number of corresponding multi-drive end and connected to the eight-eight right-shoulder temple cylinder "Shepherd 碲昍 测 this test martial circuit board sighs the corresponding number of 1 test joints, the line layout side = Kang Corresponding relationship between the driving end and the receiving end sets the starting point and the second!, :== point and end point are set on the circuit board, and the respective driving end and the receiving end corresponding to the plurality of electrical connections are arranged; And the test connection is taken from each of the signal lines... one corresponding to the test contacts corresponding to the electrical and test circuit boards. The method for laying the above-mentioned service line may include pre-setting the circuit parameter::: a boundary between the test terminal and the test circuit board corresponding to the test end, the receiving end and the test circuit board, wherein the circuit board and the test circuit board have a boundary mark After the test circuit board is tested, the test circuit board can be broken along the boundary mark to be separated from the circuit board. The boundary mark is a hem scratch, but is not limited thereto, and it may also be, for example, a dividing line. The test signal line is disposed on the bottom layer of the circuit board and the test circuit board: the common manufacturer cuts it according to the process requirements (for example, using V-cut or other cutting methods), from the top of the circuit board and the test circuit board. When a part of the thickness of the sheet is cut, * will damage the cloth test Wei line, and 19319 8 200814864 keep the integrity of the test signal line with electrical connection, and debug the board with the test board Debug work. Furthermore, the test circuit layout method of the present invention is characterized in that a signal line is disposed between a driving end of the circuit board and a corresponding receiving end thereof, and the driving end and the receiving end are electrically connected by the signal line, and A test signal line is drawn from the signal line and electrically connected to the test contact corresponding to the driver end and the receiving end on the test circuit board. Therefore, the circuit disposed on the circuit board is independent, and the signal line between the driving end and the receiving end of the electric circuit board is interrupted due to breaking the test circuit board, and the rewiring process is omitted. Hours of work and process costs to increase efficiency. [Embodiment] Hereinafter, embodiments of the present invention will be described by way of specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention by the contents disclosed in the present specification. Please refer to FIG. 2A and FIG. 2B for a test circuit layout method according to the present invention. The test circuit layout method of the present invention can be mounted in a wiring software body, and the wiring software is used to design a line. The test signal line electrically connected between the circuit board 2〇 connected to the common board and the test circuit board 22 is disposed. As shown in FIG. 2A, the circuit board 2 has a plurality of driving terminals 201a, 202a, and 203a, and corresponding receiving terminals 2b, 202b, and 203b, and the test circuit board 22 corresponds to the The drive terminals 201a, 202a, 203a and the receiving ends 201b, 2〇2b and the other end have a plurality of test contacts 22, 222, 223. The test circuit board 22 is coupled to the circuit board 20 in a manner of a common board 9 19319 200814864. A demarcation mark 21 is disposed between the circuit board 20 and the test circuit board 22 to mark along the boundary according to the requirements of the subsequent process. 21 After cutting a portion of the thickness of the board from the top layer of the circuit board 20 and the test board 22 by V_cut or other cutting method, the test circuit 22 board is broken along the boundary mark 21 to be separated from the circuit board 20. The circuit board 20 is, for example, a Motherboard (MB), and the driving terminals 20la, 202a, and 203a and the receiving ends 201b, 202b, and 203b are, for example, electronic components, chips, and other lines. For a hem, but not limited thereto, the step of arranging the test signal line on the circuit board 20, for example, a boundary line 0, includes: presetting the circuit board 20 by the wiring software. Corresponding relationship between the driving terminals 2019/, 202a, 203a and the receiving terminals 201b, 202b, 203b and the test contacts 221, 222, 223 on the test circuit board 20 is set as a conventional wiring by setting the corresponding system The software has a technology, so it will not be described here; the driver terminals 201a, 202a, 203a and the corresponding receiving terminals 201b, 202b, 203b are respectively set to be electrically connected to the signal line between the driving end and the receiving end. The starting point and the end point are electrically connected between the driving end 201a, 202a, 203a and the corresponding receiving ends 201b, 202b, 203b on the circuit board 20 according to the setting of the starting point and the end point by the wiring software. Signal lines 201, 202, 203. The signal lines 201, 202, and 203 are disposed on the circuit board 20. In detail, the signal lines 201, 202, and 203 are disposed on the circuit board 20 adjacent to the circuit board 20. 19 19319 200814864 The driving ends 201a, 202a, 203a and the corresponding receiving ends 201b, 202b, 203b on the circuit board 20 can be electrically connected to each other by the above-mentioned signal lines 201, 202, 203, and Form a complete and independent signal transmission loop. Referring to FIG. 2B, the test signal lines 201A, _ are respectively drawn and arranged by the wiring software from the signal lines 201, 202, and 203 between the driving terminals 201a, 202a, and 203a and the corresponding receiving terminals 201b, 202b, and 203b. 202A, 203A are electrically connected to the test terminals 221, 222, 223 corresponding to the drive terminals 201a, 202a, 203a and the receiving ends 201b, 202b, 203b on the test circuit board. Thus, the test contacts 221, 222, 223 on the test circuit board 22 are electrically connected to the drive terminals 201a, 202a, 203a and the receiving terminals 201b, 202b, 203b on the circuit board 20.
於本實施例中，該測試用訊號線201A、202A、203A 係佈設於該電路板20及測試電路板22之底層或臨近底層 之佈線層上，以供廠商採用例如V-cut或其他切割方式沿 著該分界標不21自該該電路板2 0及測試電路板2 2之頂 層切割掉部分厚度板材後，不會損及佈設於底層或佈線層 上之測試用訊號線201A、202A、203A，而使該測試用訊 號線201A、202A、203A保持電性連接之完整性，俾以該 測試電路板22對電路板20進行除錯測試（Debug)工作。 再者，於測試電路板22對該電路板20進行測試後， 若經確認該電路板20係無瑕疵，且需使用該電路板20 時，則該測試電路板22已完成使命且不起作用，故只需 11 19319 200814864 % •沿著該分界標示21將該測試電路板22折斷以脫離該電路 •板20,此時該測試用訊號線2〇1A、2〇2A、2〇3A即被切斷； 而電路板20上之驅動端2〇ia、202a、203a與對應之接收 端201b、202b、203b間之訊號線2(Π、202、203依然保 持完整地電性連接關係，使該電路板2〇仍可以正常運作'。 本發明可避免習知技術在折斷測試電路板後，需於電 路f上進行重新佈線之缺點，免去重新佈線所需耗費之工 作蚪間，而提高工作效率並同時降低製程成本。 * 1述實施例僅為例示性說明本創作之原理及其功 1非驗限制本創作。任何熟習此項技藝之人士均可 盘=背本創作之精神及範嘴下，對上述實施例進行修飾 鼻因此’本創作之權利保護範圍，應以後述之申請 專利範圍為依據。 T月 【圖式簡單說明】 圖；以及 第2Α圖及第2Β圖係用以磲 方法t @ + .，、'員不本發明之測試線路佈設 數雷地、垂杜& . 圖係顯示於電路板上佈設複 數電性連接於驅動端與對庫 炎 圖，第mm#%-ή+ 收端間的訊號線之示意 ψ 〈鉅動端及接收端間的訊號 瓦上引出亚佈设測試用訊號線， 上之測試接點之示意圖。 ·讀連接至測試電路板 【主要元件符號說明】 10、20 電路板 第1圖係為習知技術中佈設測試用訊號線之示意 儀 19319 12 200814864 101a、102a、103a、201a、202a、203a 驅動端 101b、102b、103b、201b、202b、203b 接收端 ΗΠΑ、102A、103A、101B、102B、103B 測試用訊號線 11、 21 分界標示 12、 22 測試電路板 121、122、123、22卜 222、223 測試接點 201、202、203 訊號線 201A、202A、203A 測試用訊號線 13 19319In this embodiment, the test signal lines 201A, 202A, and 203A are disposed on the bottom layer of the circuit board 20 and the test circuit board 22 or adjacent to the underlying wiring layer for the manufacturer to adopt, for example, a V-cut or other cutting method. A portion of the thickness plate is cut from the top layer of the circuit board 20 and the test circuit board 2 2 along the demarcation mark 21, and the test signal lines 201A, 202A, and 203A disposed on the bottom layer or the wiring layer are not damaged. The test signal lines 201A, 202A, and 203A maintain the integrity of the electrical connection, and the test circuit board 22 performs a debug test on the circuit board 20. Moreover, after the test circuit board 22 tests the circuit board 20, if it is confirmed that the circuit board 20 is flawless and the circuit board 20 is to be used, the test circuit board 22 has completed the mission and does not function. Therefore, only 11 19319 200814864 % is needed. • The test circuit board 22 is broken along the boundary mark 21 to be separated from the circuit board 20. At this time, the test signal lines 2〇1A, 2〇2A, 2〇3A are The signal line 2 (Π, 202, 203) between the driving terminals 2〇ia, 202a, 203a on the circuit board 20 and the corresponding receiving ends 201b, 202b, 203b remains completely electrically connected. The circuit board 2 can still operate normally. The invention can avoid the disadvantages of the prior art that the circuit needs to be re-routed on the circuit f after breaking the test circuit board, and the work time required for rewiring is eliminated, and the work is improved. Efficiency and at the same time reduce the cost of the process. * The description of the example is only illustrative of the principle of this creation and its work is not limited to the creation of this work. Anyone who is familiar with this skill can use the spirit of the creation and the mouth of the book. Next, the above embodiment is modified to cause nasal 'The scope of protection of the rights of this creation shall be based on the scope of the patent application to be described later. T month [simple description of the schema]; and the second and second diagrams are used for the method t @ + ., The test circuit of the present invention is provided with a number of lightning grounds, and a plurality of diagrams are displayed on the circuit board, and a plurality of electrical connections are electrically connected to the driving end and the signal line between the mm#%-ή+ terminals. ψ “The signal line on the signal board between the giant terminal and the receiving end leads to the test signal line on the sub-distribution test board. The connection is connected to the test circuit board. [Main component symbol description] 10, 20 circuit board 1 is a schematic diagram for laying a test signal line in the prior art. 19319 12 200814864 101a, 102a, 103a, 201a, 202a, 203a Driving end 101b, 102b, 103b, 201b, 202b, 203b receiving end ΗΠΑ, 102A, 103A , 101B, 102B, 103B test signal line 11, 21 demarcation mark 12, 22 test circuit board 121, 122, 123, 22 222, 223 test contact 201, 202, 203 signal line 201A, 202A, 203A test signal Line 13 19319