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TW200603300A - Chip structure - Google Patents

Chip structure

Info

Publication number
TW200603300A
TW200603300A TW093124492A TW93124492A TW200603300A TW 200603300 A TW200603300 A TW 200603300A TW 093124492 A TW093124492 A TW 093124492A TW 93124492 A TW93124492 A TW 93124492A TW 200603300 A TW200603300 A TW 200603300A
Authority
TW
Taiwan
Prior art keywords
thin film
layer
layers
bump
dielectric layers
Prior art date
Application number
TW093124492A
Other languages
Chinese (zh)
Other versions
TWI236722B (en
Inventor
Mou-Shiung Lin
Chiu-Ming Chou
Original Assignee
Megic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Megic Corp filed Critical Megic Corp
Priority to US11/178,753 priority Critical patent/US8022544B2/en
Priority to US11/178,541 priority patent/US7465654B2/en
Application granted granted Critical
Publication of TWI236722B publication Critical patent/TWI236722B/en
Priority to US11/202,730 priority patent/US7452803B2/en
Publication of TW200603300A publication Critical patent/TW200603300A/en
Priority to US12/025,002 priority patent/US7462558B2/en
Priority to US12/202,342 priority patent/US7964973B2/en
Priority to US12/262,195 priority patent/US8581404B2/en
Priority to US13/098,379 priority patent/US8159074B2/en
Priority to US13/207,346 priority patent/US8519552B2/en

Links

Classifications

    • H10W72/012—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A chip structure includes a semiconductor substrate, multiple thin film dielectric layers, multiple thin film circuit layers, a passivation layer, a metal circuit layer and at least a bump. The semiconductor substrate has multiple electronic devices arranged in the surface layer thereof. The thin film dielectric layers are positioned over the semiconductor substrate and have multiple via holes. Each of the thin film circuit layers is positioned on one of the thin film dielectric layers. The thin film circuit layers are electrically connected with each other through the via holes and electrically connected to the electronic devices. The passivation layer is disposed over the thin film dielectric layers and the thin film circuit layers. The metal circuit layer is disposed over the passivation layer. The bump is arranged on the metal circuit layer or on a contact of the thin film circuit layer, wherein the bump is not adapted to be reflowed. In an embodiment, the metal circuit layer has a metal layer, such as gold layer, with a thickness larger than 1 micrometer. The material of the bump includes gold.
TW093124492A 2004-07-09 2004-08-12 Chip structure TWI236722B (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US11/178,753 US8022544B2 (en) 2004-07-09 2005-07-11 Chip structure
US11/178,541 US7465654B2 (en) 2004-07-09 2005-07-11 Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
US11/202,730 US7452803B2 (en) 2004-08-12 2005-08-12 Method for fabricating chip structure
US12/025,002 US7462558B2 (en) 2004-08-12 2008-02-02 Method for fabricating a circuit component
US12/202,342 US7964973B2 (en) 2004-08-12 2008-09-01 Chip structure
US12/262,195 US8581404B2 (en) 2004-07-09 2008-10-31 Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
US13/098,379 US8159074B2 (en) 2004-08-12 2011-04-29 Chip structure
US13/207,346 US8519552B2 (en) 2004-07-09 2011-08-10 Chip structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58684004P 2004-07-09 2004-07-09
US58859504P 2004-07-16 2004-07-16

Publications (2)

Publication Number Publication Date
TWI236722B TWI236722B (en) 2005-07-21
TW200603300A true TW200603300A (en) 2006-01-16

Family

ID=36678597

Family Applications (2)

Application Number Title Priority Date Filing Date
TW093124492A TWI236722B (en) 2004-07-09 2004-08-12 Chip structure
TW093138329A TWI284385B (en) 2004-07-09 2004-12-10 Chip structure and method for fabricating the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW093138329A TWI284385B (en) 2004-07-09 2004-12-10 Chip structure and method for fabricating the same

Country Status (1)

Country Link
TW (2) TWI236722B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119627018A (en) * 2024-02-02 2025-03-14 芯爱科技(南京)有限公司 Electronic packaging and method of manufacturing the same

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8148822B2 (en) 2005-07-29 2012-04-03 Megica Corporation Bonding pad on IC substrate and method for making the same
US8399989B2 (en) 2005-07-29 2013-03-19 Megica Corporation Metal pad or metal bump over pad exposed by passivation layer
US7990037B2 (en) 2005-11-28 2011-08-02 Megica Corporation Carbon nanotube circuit component structure
US8022552B2 (en) 2006-06-27 2011-09-20 Megica Corporation Integrated circuit and method for fabricating the same
TWI471958B (en) * 2006-09-06 2015-02-01 高通公司 Chip package structure and its process
US8193636B2 (en) 2007-03-13 2012-06-05 Megica Corporation Chip assembly with interconnection by metal bump

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119627018A (en) * 2024-02-02 2025-03-14 芯爱科技(南京)有限公司 Electronic packaging and method of manufacturing the same

Also Published As

Publication number Publication date
TW200603339A (en) 2006-01-16
TWI284385B (en) 2007-07-21
TWI236722B (en) 2005-07-21

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Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent