1284385 15625twf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種晶片結構及其製作方法，且特別是有關 於-種可以簡化製程步驟的晶片結構製作方法及其所雜的 結構。 . ... . . 【先前技術1 隨著資訊產品技術的突飛猛進，人類欲快速獲得千里以外的 資訊，已不是一件困難的事，企業競爭取得時效上的優勢，透 過建置高效率的資訊產品可以達到此目的。隨著資訊產品的推陳 出新與各種線路設計的整合’最新的單晶片普遍地提供比以往更籲 多的功能。由於半導體科技的曰新月異，銅製程的量產成功，再 加上透過電路的整合，大多數的訊號傳輸可以在同一單晶片内， 使得訊號的傳輸路徑可以縮短且晶片的效能可以改善。 為了配合積體電路的整合及晶片的封裝，可以在晶片從晶圓 薇製作完成送至凸塊廠之後，再形成金屬線路及凸塊於晶片之保 護層上，藉以將晶片的對外接點重新佈局，在保護層上形成金屬 線路及凸塊的步驟係大致上如下所述。 圖1至圖12緣示習知在半導趙晶圓上製作金屬線路及凸塊 之製程的剖面示意圖。請參照圖1 ,首先提供一半導體晶圓1〇〇， · 半導體晶圓100包括一半導體基底11〇、多數層薄膜介電層 122、124、126、多數層薄膜線路層132、134、136及一保護 層140。 … 半導體基底110具有多數個電子元件112，電子元件112 係配設在半導體基底110之主動表面114的表層，其中半導 體基底110比如是矽基底，透過摻雜五償或三價的離子，比 如是硼離子或磷離子，藉以形成多個電子元件112在半導體 基底110之表層，電子元件112比如是金屬氧化物半導體或 1284385 15625twf.doc/006 電晶體等。 多層之薄膜介電層122、124、126配置在半導體基底no 之主動表面114上，其中薄膜介電層122、124、126比如是 . · . . . . 氧矽化合物、氮矽化合物或氮氧矽化合物等，每一薄膜線路 層132、134、136係分別配置在其中一薄膜介電層122、124、 126上，其中薄膜線路層132、134、136的材質比如包括鋁、 銅或矽等。薄膜介電層122、124、126具有多數個導通孔121、 123、125，薄膜線路層132、134、136可以藉由薄膜介電層 122、124、126之導通孔121、123、125彼此電性連接，並 電性連接至電子元件112。 保護層140係配置在薄膜介電層122、124、126與薄膜 線路層132、134、136上，其中保護層140的厚度z —般係 大於0.35微米，且保護層14〇的結構比如係為一氮矽化合物 層、一氧矽化合物層、一磷矽玻璃層或至少一上述材質所構 成的複合層。保護層140具有多數個開口 142，暴露出位於 頂層之薄膜線路層136。 在圖2至圖6中，係:緣示在半導體晶圓之保護層上形成金屬 線路之製程的剖面示意圖。請參照圖2，首先可以利用濺鍍的方 式形成一底部金屬層152在半導體晶圓1〇〇之保護層140上及暴 露於保護層140之開口 142外的薄膜線路層136上。接著， 可以形成一光阻層16〇在底部金屬層152上，光阻層160具有一 開口 162 ’暴露出底部金屬層152，如圖3所示。接著，可以利 用電鍵的方式’形成線路圖案之金屬層154在光阻層160之開口 I62所暴露出的底部金屬層152上，如圖4所示。接著，再去除 光阻層160，如圖5所示。之後，再以線路圖案之金屬層154作 為姓刻遮罩，餘刻掉未被遮蓋的底部金屬層152，如圖6所示。 如此’由底部金屬層152及線路圖案之金屬層154所構成的金屬 1284385 · 15625twf.doc/006 線路150便製作完成。 請參照圖7，接下來可以形成一聚合物層170在金屬線路150 上及保護層140上，其中聚合物層170具有多個開口 172，暴露 出金屬線路150 〇 在圖8至圖12中，係繪示在半導體晶圓之保護層上形成也 塊之製程的剖面示意圖。請參照圖8，首先可以利用濺鍍的式 形成一底部金屬層182在聚合物層170上及暴露於聚合杨層170 之開口 172外的金屬線路150上。接著，可以形成一光阻層190 在底部金屬層182上，光阻層190具有一開口 192，暴露出底部 金屬層182，如圖9所示。接著，可以利用電鑛的方式，形成凸 塊圖案之金屬層184在光阻層190之開口 192所暴露出的底部金 屬層182上，如圖10所示。接著，再去除光阻層190，如圖11 所示。之後，再以凸塊圖案之金屬層184作為蝕刻遮罩，蝕刻掉 未被遮蓋的底部金屬層182，如圖12所示。如此，由底部金屬層 182及凸塊圖案之金屬層184所構成的凸塊180便製作完成。 請參照圖1至圖12，在形成金屬線路150及凸塊180時，均 需要先分別利用濺鍍的方式形成底部金屬層152、182 ,並且在形 成線路圖案之金屬層154及凸塊圖案之金屬層184之後，還要分 別利用蝕刻的方式，去除未被遮蔽的底部金屬層152、182，如此 共需進行兩次的濺鍍步驟及兩次的蝕刻步驟，故習知的形成金屬 線路150及凸塊180之步驟甚不具效率性。 【發明内容】 有鑒於此，本發明的目的就是在提供一種晶片結構製作方 法，可以將製作凸塊的步驟與製作金屬線路的步驟整合，藉以簡 化形成金屬線路及凸塊的製程步驟。 " 另外，本發明的目的就是在提供一種晶片結構製作方法，可 以形成厚度大於1微米的銅層或金層在半導體晶圓的保護層上， 1284385 15625twf.doc/006 以作為金屬線路，並且可以形成厚度大於3微米的金層或焊料層 在半導體晶圓的保護層上，以作為凸塊。 另外，本發明的目的就疋在提供一種晶片結構，其中金屬線 路包括厚度大於1 «義層或金層，凸括·錄3微来 的金層或焊料層。 另外’本發明的目的就是在提供一種晶片結構，其中金屬無 路包括厚度大於丨微米_層或錄，凸括_大於3微米 的金層或烊料層。 下 另外，本發明的目的就是在提供一種晶片結構，包括金屬後 路及凸塊，其中金屬線路可以位在保護層上，凸塊可以位在保 層之開口所暴露出之薄膜線路層上。 " 、為達成本發明的目的，本發明提出一種晶片結構製作方法， 首先’提供半導趙晶圓；接著，形成底部金屬層在半導趙曰 圓上；接著’形成具有線路圖案之第—金屬層在底部金屬= 上，接著，形成凸塊圖案之第二金屬層在第—金屬層上在 :成第-金屬層及第二金屬層之後，去除未被第屬層 蓋之底部金屬層。 增復 首先itn發的面目的，本發明提出一種晶片結構製作方法， 尸接著’形成線路圖案之第一金屬層在底部金n 著，形成凸塊圖案之第二金屬層在底部金屬層上；，嚴 去除未被第-金屬層及第二金屬層覆蓋之底部金屬層。再 首先月曰的圓目的，本發明提出一種晶片結構製作方法， 首先k供接著，形成底部金屬層在 士；接著，形成具有線路圖案及凸塊圖案之 屬層上；讀，再絲缝金制覆奴絲金/層底箱 1284385 · 15625twf.doc/006 為達成本發明的目的，本發明提出一種晶片結構製作方法， 首先’ ^供一半導趙晶圓，接著’形成第一金層在半導體晶 圓上，第一金層的厚度係大於1微米；接著，形成第二金^ 在第一金層上，第二金層的厚度係大於3微米。 為達成本發明的目的，本發明提出一種晶片結構製作方法, 首先，提供半導體晶圓；接著，形成底部金屬層在半導體晶 圓上；接著，形成第一金層在底部金屬層土，第一金層的$ 度係大於1微米；接著，形成第二金層在底部金屬層上，第 二金層的厚度係大於3微米；之後，再去徐未被第一金層及 第二金層覆蓋之底部金屬層。 為達成本發明的目的，本發明提出一種晶片結構製作方法， 首先，提供半導體晶圓；接著，形成金層在半導體晶圓上， 金層的厚度係大於1微米；接著，形成谭料層在金層上，焊 料層的厚度係大於3微米。 為達成本發明的目的，本發明提出一種晶片結;溝製作方法， 首先，提供半導體晶圓；接著，形成底部金屬層在半導體晶 圓上；接著，形成金層在底部金屬層上，金層的厚度係大= 1微米；接著，形成焊料層在底部金屬層上，焊料層的厚度 係大於3微米；之後，再去除未被金層及焊料層覆蓋之底部 金屬層。 一 為達成本發明的目的，本發明提出一種晶片結構製作方法， 首先，提供半導體晶圓；接著，形成銅層在半導體晶圓上， 銅層的厚度係大於1微米；接著，形成金層在銅層上，金層 的厚度係大於3微米。 為達成本發明的目的，本發明提出一種晶片結構製作方法， 首先，提供半導體晶圓；接著，形成底部金屬層在半導體晶 1284385 15625twf.doc/006 圓上；接著，形成銅層在底部金屬層上，銅層的厚度係大於 1微米；接著，形成金層在底部金屬層上，金層的厚声女 於3微米；之後，再去除未被鋼層及金層覆蓋之底部金H。 為達成本發明的目的，本發明提出一種晶片結構製作方法， 首先，提供半導體晶圓；揍著，形成銅層在半導體晶圓上， 銅層的厚度係大於1齡；接著，形成焊簡在銅層上， 料層的厚度係大於3微米。^ ^ ^ ^ ^ ^ ^ 為達成本發明的目的，本發明提出一種晶片結構製作方法， 首先，提供一半導體晶圓；接著，形成底部金屬層在半導體 晶圓上；接著，形成銅層在底部金屬層上，銅層的厚度係大 於1微米；接著，形成焊料層在底部金屬層上，焊料層的厚 度係大於3微米；之後，再去除未被銅層及焊料層覆蓋之底 部金屬層。 一 為達成本發明的目的，本發明提出一種晶片結;溝製作方法， 首先，提供半導體晶圓；接著，形成第一光阻層在半導體晶 圓上，第一光阻層具有開口，暴露出半導體晶圓；接著，形 成第一金屬層在第一光阻層之開口所暴露出的半導體晶圓 上；接著，去除該第一光阻層；接著，形成第二光阻層在第 一金屬層上，第二光阻層具有開口，暴露出第一金屬層；接 著，形成第二金屬層在第二光阻層之開口所暴露出的第一金 屬層上；接著，去除第二光阻層。 為達成本發明的目的，本發明提出一種晶片結構，包括半 導體基底、多數層薄膜介電層、多數層薄膜線路層、保護層、 圖案化金屬層及凸塊。半導體基底具有電子元件，電子元件 係配設在該半導體基底之主動表面的表廣。薄膜介電層配置 在半導體基底之主動表面上，其中薄膜介電層具有導通孔， 1284385 15625twf.doc/006 每一薄膜線路廣係分別配置在其中一薄膜介電層上，且薄膜 線路層藉由導通孔彼此電性連接，並電性連接至電子元件， 保護層配置在薄膜介電脣與薄膜線路層上^圖案化金屬屠配 置在薄膜介電層與薄膜線路層上，且圖案化金屬層包括厚度 大於1微米的金層或銅層，其中圖案化金屬層包括金屬線路。 凸塊位於圖案化金羼層上，且凸塊包括厚度大於3的焊 料層或金層。 為達成本發明的目的，本發明提出一種晶片結構，包括半 導體基底、多數層薄膜介電層、多數層薄膜線路層、保護層、 金屬線路及凸塊。半導體基底具有電子元件，電子元件係配 設在該半導體基底之主動表面的表層。薄膜介電層配置^半 導艎基底之主動表面上，其中薄膜介電層具有導通孔，每一 薄膜線路層係分別配置在其中一薄膜介電層上，且薄膜線路 層藉由導通孔彼此電性連接，並電性連接至電子元件，保嗖 層配置在薄膜介電層與薄膜線路層上，保護層具有開口，'暴 露出頂層之薄膜線路層之接點。金屬線路配置在薄膜介電層 與薄膜線路層上，且金屬線路包括厚度大於丨微米的金層或 銅層。凸塊位於薄膜線路層之接點上，且凸塊包括厚度大於 3微米的焊料層或金層。 、 為達成本發_目的，本發明提出—種晶片結構，包括半 導體基底、多數層薄膜介電層、多數層薄膜線路層、保護層、 金屬線路及凸塊。半導體基底具有電子元件，電子元件係配 設在該半導縣底之主動表面的表層。薄膜介電層配置在半 導體基底之主動表面上，其中薄膜介電層具有導通孔，每一 薄膜線路層係分雜置在其中_薄膜介電廣上，且薄膜線 層藉由導通孔彼此電性連接，並電性連接至電子^件，保護 1284385 15625twf.doc/006 層配置在薄膜介電層與薄膜線路層上，保護層具有開口，暴 露出頂層之溥膜線路層之接點。金屬線路配置在薄媒介電層 與薄膜線路層上，且金屬線路的厚度係大於丨微米，凸塊^ 位於薄膜線路層之接點上。 為讓本發明之上述和其他目的、特徵和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 .... ' . 首先，介紹本發明之其中一種晶片結構製作方法，僅需藉由 一道步驟形成一層的底部金屬層，便可以在接下來的步驟中形成 金屬線路及凸塊，如此可以簡化製程步驟。 二、晶片結楫製作方法的第一實你.备丨 1·製作金屬線路及凸塊的第一種方法 圖13至圖21纟會示依照本發明第一實施例中在半導艘晶圓上 製作金屬線路及凸塊之第一種製作方法的剖面示意圖。請參照圖 13，首先提供一半導體晶圓200，半導體晶圓2〇〇包括一半導體 基底210、多數層薄膜介電層222、224、226、多數層薄膜線 路層232、234、236及一保護層240。 半導體基底210具有多數個電子元件212，電子元件212 係配設在半導趙基底210之主動表面214的表層，其中半導 體基底210比如是矽基底，透過摻雜五價或三價的離子，比 如是硼離子或磷離子，藉以形成多個電子元件212在半導體 基底210之表層，電子元件212比如是金屬氧化物半導體元 件、電晶體或其他類型之電子元件等。 多層之薄膜介電層222、224、226配置在半導體基底210 之主動表面214上，其中薄膜介電層222、224、226比如是 氧矽化合物、氮矽化合物或氮氧矽化合物等，每一薄膜線路 層232、234、236係分別配置在其中一薄膜介電層222、224、 12 1284385 1 S62Stwf.doc/006 226上，其中薄膜線路層232、234、236的材質比如包括鋁、 銅或矽等。薄膜介電層222、224、226具有多數個導通孔221、 2M、2M，薄膜線路層232、234 v 236可以轉由薄膜介電層 222、224、226之導通孔221、公3、225彼此電性連接,並 電性連接至電子元件212。 保護層240係配置在薄膜介電層222、224、226與薄膜 線路層232、234、236上，其中保護層240的厚度z —般係 大於0.35微米，且保護層240的結構比如係為一氮矽化合物 層、一氧矽化合物層、一鱗矽玻璃層或至少一上述对質所構 成的複合層。保護層240具有多數個開口 242 ,暴露出位於 頂層之薄膜線路層236之接點236a、236b。 請參照圖14 ’在提供半導體晶圓2〇〇之後，可以利用濺鍵的 方式形成底部金屬層250在半導體晶圓之保護層240上及暴露於 保護層240之開口 242外的薄膜線路層236之接點上，在此 過程中’比如包括先濺鍍黏著/阻障層在半導體晶圓2⑻之保 護層240上及暴露於保護層240之開口 242外的薄膜線路層236 上，接著再濺鍍種子層在黏著/阻障層上，黏著/阻障層及種子 層的材質係敘述如後，在此便不再贅述。 接著，可以形成光阻層260在底部金屬層252上，光阻層260 具有開口 262，暴露出底部金屬層252，如圖15所示。接著， 可以利用電鍍的方式，形成金屬層254在光阻層26〇之開口 262 所暴露出的底部金屬層252上，如圖16所示，其中金屬層254 包括線路，案254a及接墊圖案254b，金屬層254之線路圖案254a 電性連接薄膜線路層236之接點236a，且在保護層240上延 伸；金屬層254之接墊圖案254b電性連接薄膜線路層236之 接點236b，且位在薄膜線路層236之接點236b上。 疋義平面1000，平面1000係大致上平行於半導體基 13 1284385 15625twf.doc/006 底210之主動表面214，請參照圖16A，其繪示圖16中金屬 層254之線路圖案254a及接墊圖案254b投影至平面1000上 的示意圖0金屬層254之線路圖案2543投影至平面1〇〇〇上的 延伸距離(圖16A中路徑10從p點延伸至q點的距離)比如係 大於500微米，或者比如係大於800微米，或者比如係大於 1200微米；金屬層254之線路圖案254a投影至平面1〇〇〇上 的面積（圖16A中線路爾案254a之畫斜線的區域)比如係大於 30,000平方微米，或者比如係大於8〇 〇〇〇平方微米，或者比 如係大於150,000平方微米。 接著’可/以將光阻層260去除，暴露出底部金屬層252 ,如 圖17所示。之後，可以再形成光阻層27〇在底部金屬層2幻上 及金屬層254上，光阻層270具有開口 272，暴露出金屬層254 之線路圖案254a及接墊圖案254b，如圖18所示。 “接著，可以利用電鍍的方式形成作為凸塊之金屬層28〇在 光阻層270之口 272所暴露出之金屬層254的線路圖案254a 上及接墊圖案254b上，如圖19所示。值得注意的是，每一凸 ^ 280投影至平面1〇〇〇上的面積比如係小於如，麵平方微 ΐ方^比如係小於2〇,000平方微米，或者比如係小於咖00 接著 可以去除光阻層270 ,暴露出底部金屬層252 ,如 的方々in接著，再以金屬層254作為蝕刻罩壁，透過蝕刻 除並未被金屬層254覆蓋之底部金屬層252的 層252 阻障^，僅留下位在金屬層254下的底部金屬 可以進行迴=步 當凸塊28G包括焊料層時，接下來還 表面(未繪示）。、’驟’使得凸塊280的頂面可以形成圓滑的 後可以進行單切的步驟，此時切割刀會沿著半導體 1284385 15625twf.doc/006 晶圓200之切割道(seribe_line)來切割半導體晶亂2〇〇，藉以 形成多個獨立的晶片結構205。 在上述的製程中，金屬線路250係由濺鍍製程所形成的 底部金屬層252及電鍍製程所形成之金屬層254的線路圖案 254a所構成，而凸塊280係僅由電鍍製程所形成的金展層所 構成’相較於習知形成金屬線路及凸塊的製程，本發明在製 作凸塊280時，可以省去濺鍍製程，故可以簡化形成金屬線 路250及凸塊280的步驟。 2·金屬線路及接墊之結構 請參照圖21，金屬線路250係由濺鍍製程所形成的底部 金屬層252及電鍵製程所形成的金屬層254之線路圖案254a 所構成，接墊251係由濺鍍製程所形成的底部金屬層252及 電鍍製程所形成的金屬層254之接墊圖案254b所構成，且接 墊251的金屬層結構係相同於金屬線路250的金屬層結構, 詳細結構係如下所述。 A·金屬線路及接塾之第一種金屬層結構 請參照圖22,其繪示依照本發明第一實施例之金屬線路 及接墊之第一種金孱層結構的剖面示意圖，其中在形成底部 金屬層252時，比如係先利用濺鍍製程形成黏著/阻障屠 2521a，接著再利用濺鍍的方式形成作為種子層之金層2521b 於黏著/阻障層2521a上，其中黏著/阻障層2521a之材質比如 係為鈦、鈦鎢合金、鈦氮化合物、鈕或鈕氮化合物等。在形 成金屬層254時，比如係利用電鍍的方式形成厚度X大於1 微米的金層在底部金屬層252之種子層2521b上。 B·金屬線路及接墊之第二種金屬層結構 請參照圖23，其繪示依照本發明第一實施例之金屬線路 及接墊之第二種金屬層結構的剖面示意圖，其中在形成底部 15 1284385 15625twf.doc/006 金屬層252時，比如係先利用濺鍍製程形成黏著/阻障層 2522a ’接著再利用滅鍍的方式形成作為種子層之銅層2522b 於黏著/阻障層2522a上’其中黏著/阻障層2522a之材質比如 係為鉻、鈦、鈦鎢合金、鈦氮化合物、鈕或钽氮化合物等, 或者黏著/阻障層2522a亦可以是藉由依序沉積鉻層及鉻銅合 金層而成’其中鉻銅合金層係位在鉻層上。在形成金屬層254 時，比如係利用電鍍的方式形成厚度：大於1徽米的铜層在 底部金屬層252之種子層2522b上。 C·金屬線路及接整之第三種金屬層結構 請參照圖24,其繪示依照本發明第一實施例之金屬線路 及接墊之第三種金屬層結構的剖面示意圖，其中在形成底部 金屬層252時，比如係先利用濺鍍製程形成黏著/阻障層 2523a，接著再利用濺鍍的方式形成作為種子層之銅層2523b 於黏著/阻障層2523a上，其中黏著/阻障層说如之材質比如 係為鉻、鈦、鈦鶴合金、鈦氮化合物、组或组氮化合物等， 或者黏著/阻障層2523a亦可以是藉由依序沉祕層及絡銅合 金層而成’其中鉻銅合金層係位在鉻層上。在形成金屬層254 時’比如疋先湘電鍵的方式形成厚度χ大於i微耗銅層 2543a在底部金屬層252之種子層2523b上，接著再利用電 鍍的方式形成鎳層2543b在銅層2543a上。 D·金屬線路及接墊之第四種金屬層結構 請參照圖25，其繪示依照本發明第—實闕之金屬線路 及^塾之第四種金屬層結構的剖面示意圖，其中在形成底部 金層25j時，比如係先利用濺鍍製程形成黏著/阻障層 2524^’接著再利用滅鍵的方式形成作為種子層之銅層 2524b 於黏著/阻障層252如上，其中黏著/阻障層2s24a之材質比如 係為鉻、鈦、鈦鶴合金、錢化合物、纽或减化合物等， 16 1284385 15625twf.doc/006 或者黏著/阻障層2524a亦可以是藉由依序沉積鉻層及鉻銅合 金層而成，其中鉻銅合金層係位在鉻層上。在形成金屬層254 時’比如是先利用電鍍的方式形成厚度X大於1微米的銅層 2544a在底部金屬層252之種子層2524b上，接著再利甩電 鍍的方式形成鎳層2544b在銅層2544a上，之後再利用電鍵 的方式形成金層2544c在鎳層2544b上。 3·凸塊之結構 在上述之第一實施例中，凸塊280係電鍵在金屬層234 之線路圖案254a上及接藝圖案254b上，凸塊280之金屬層 的詳細結構比如係如下所述。 A·第一種凸塊結構 凊參照圖26 ’其緣不依照本發明第一實施例之第一種凸 塊結構的剖面示意圖。在形成凸塊280時，比如係利用電鍵 製程形成厚度y大於3微米的金層2801在金屬層254之線路 圖案254a上及接墊圖案254b上，其中金層2801可以直接接 觸地形成在具有圖22至圖25所示之金屬層結構的金屬線路 250上或接墊251上。作為凸塊280用途之金層2801比如是 直接接觸地形成在頂部表面材質係為金或銅的金屬線路250 上或接墊251上，此時金屬線路250及接墊251比如係具有 如圖22、圖23或圖25所示之金屬層結構。 B·第二種凸塊結構 請參照圖27，其繪示依照本發明第一實施例之第二種凸 塊結構的剖面示意圖。在形成凸塊280時，比如可以利用電 鍍製程先形成鎳層2802a在金屬層254之線路圖案254a上及 接墊圖案254b上，其中凸塊280之鎳層2802a比如可以直接 接觸地形成在具有圖22至圖25所示之金屬層結構的金屬線 路250上或接墊251上；接著，可以再利用電鍍製程形成厚 17 1284385 15625twf.doc/006 度y大於3微米的金層2802b在鎳層2802a上。 C·第三種凸塊結構 5月參照圖28 ’其緣不依照本發明第一實施例之第二種凸 塊結構的剖面示意圖。在形成凸塊280時，比如係利用電鍍 製程先形成鎳層2803a在金屬層254之線路圖案254a上及接 墊圖案254b上，其中凸塊280 <鎳層2803a比如可以直接接 觸地形成在具有圖22至圖25所示之金屬層結構的金屬線路 250上或接墊251上；接著再利用電鍍製程形成厚度y大於3 微米的焊料層2803b在鎳層2803a上，其中焊料層28031>的 材質比如是錫鉛合金、錫、錫銀合金或錫銀銅合金等。 D·第四種凸塊結構 請參照圖29，其繪示依照本發明第一實施例之第四種凸 塊結構的剖面不意圖。在形成凸塊280時，比如係利用電鍛 製程先形成銅層2804a在金屬層254之線路圖案254a上及接 墊圖案254b上，其中凸塊280之銅層2804a比如可以直接接 觸地形成在具有圖22至圖25所示之金屬展結構的金屬線路 250上或接墊251上。接著，可以再利用電鍍製程形成鎳層 2804b在銅層2804a。接著，可以再利用電鍍製程形成厚度y 大於3微米的焊料層2804c在鎳層2804b上，其中焊料層2804c 的材質比如是錫鉛合金、錫、錫銀合金或錫銀銅合金等。 4·製作金屬線路及凸塊的第二種方法 上述第一種製作方法與第二種製作方法的最大差異點係 為形成光阻層及去除光阻層的步驟，在上述第一種方法中， 係在形成用於定義凸塊之形狀及位置的光阻層之前，先將用 於定義金屬線路之形狀及位置的光阻層去除，然而本發明的 應用並不限於此，亦可以係如下述的第二種製作方法所述。 圖30至圖33缘示依照本發明第一實施例中在半導體晶圓上 1284385 1 S625twf.doc/006 製作金屬線路及凸塊之第二種製作方法的剖面示意圖，其中圖3〇 至圖33係接續圖π的步驟。 在形成金屬層254之後，如圓16所示，可以再形成光阻 層270在金屬層254上及光阻層260上，如圖33所示，其中光 阻層270具有開口 272，暴露出金屬層254之線路圖案254&及接 墊圖案254b。接著，可以利用電鍍的方式形成作為凸塊之金屬 層280在光阻層270之開口 272所暴露出之金屬層254的線 路圖案254a上及接墊圖案2541)上，如圖31所示，其中每一凸 塊280投影至平面1〇〇〇上的面積比如係小於3〇 〇〇〇平方微 米，或者比如係小於2〇,〇〇〇平方微米，或者比如係小於15 〇〇〇 平方微米。 ' 接著，可以依序去除光阻層270、260 ,暴露出底部金屬 層252,如圖32所示。接著，再以金屬層254作為蝕刻罩壁， 透過蝕刻的方式依序去除未被金屬層254覆蓋之底部金屡層 252的種子層及黏著/阻障層，僅留下位在金屬層254下的底 部金屬層252，如圖33所示。當凸塊280包括焊料層時，接 下來還可以進行迴焊的步驟，使得凸塊28〇的頂面可以形成 圓滑的表面(未綠示）。 之後，可以進行單切的步驟，此時切割刀會沿著半導體 晶圓200之切割道(scribe_iine)來切割半導體晶圓2〇〇，藉以 形成多個獨立的晶片結構205。 在上述的製程中，金屬線路250係由濺鍵製程所形成的 底部金屬層252及電鍍製程所形成之金屬層254的線路阖案 254a所構成’而凸塊280係僅由電鍍製程所形成的金屬層所 構成，相較於習知形成金屬線路及凸塊的製程，本發明在製 作凸塊280時，可以省去濺鍍製程，故可以簡化形成金屬線 路250及凸塊280的步驟。 1284385 15625twf.doc/006 另外，就金屬線路、接墊及凸塊的結構而言，係如同前述之 第2點及第3點所述，在此便不再贅述。 ^製作金屬線路及第一種形式之柱狀凸塊的第一種方法 毘外，本發明的製程亦可以結合製作柱狀凸塊的製輊, 如圖34至圖38所示，其獪示依照本發明第一實施例中在半導 體晶圓上製作金屬線路及第一種形式之柱狀凸塊的第一種製作方 法之剖面示意圓，其中圖34至圖38係接續圖17鈞步驟。 在具有線路圖案254a及揍墊圖案254b的金屬層254製 作完成之後，如圖17所示，還可以形成光阻層270在底部金 屬層252上及金屬層254上，光阻層270具有開口 272，暴露出 金屬層254之線路圖案254a及接塾圖案254b，如圖34所示。 請繼續參照圖34 ,接著可以利用電鍍的方式依序形成金屬 柱292及焊料層296在光阻層270之開口 272所暴露出之金 屬層254的線路圖案254a上及接墊圖案254b上，其中在形成 金屬柱292時，比如係利用電鍍製程依序形成底部金屬層 293、柱狀金屬層294及防崩落層295。底部金屬層293之材 質比如係為鎳，其中由鎳所構成之底部金屬層293比如可以 直接接觸地形成在具有圖22至圖25所示之金屬層結構的金 屬線路250上或接墊251上；當在形成柱狀金屬層294時， 比如是利用電鍍的方式形成厚度介於8微米至1〇〇微米的銅 層在底部金屬層293上，或者比如是利用電鍍的方式形成厚 度介於8微米至1〇〇微米之含鉛量高的錫鉛合金層在底部金 屬層293上，當在形成防崩落層295時，比如是利用電鑛的 方式形成厚度介於1微米至10微米的錄層在柱狀金屬層294 上。在本實施例中，焊料層2%的材質比如係為錫鉛合金、 ，、錫銀合金或錫銀銅合金等，焊料層296可以直接接觸地 形成在金屬柱292之鎳層295上，且位在光阻層270之開口 20 1284385 15625twf.doc/006 272 中。 接著，可以去除光阻層270，暴露出底部金屬層252，如 圖35所示。接著，可以從金屬柱292的側壁蝕刻金屬柱292 之柱狀金屬層294，使得柱狀金屬層294投影至平面1000上 的面積可以小於防崩落層295或焊料層296投影至平面1000 上的面積，且防崩落層295之下表面的邊緣可以暴露於外， 如圖36所示。接著，再以金屬層254作為蝕刻軍壁,透過蝕 刻的方式依序去除未被金展層254覆蓋之底部金屬層252的 種子層及黏著/阻障層，僅留下位在金屬層254下的底部金屬 層252，如圖37所示。接下來，還可以進行迴焊的步驟，使 得焊料層296的頂面可以形成圓滑的表面，如圖38所示，至 此便元成製作凸塊290的製程。在本實施例中，凸塊290可 以包括底部金屬層293、柱狀金屬層294、防崩落層295及焊 料層296 〇 之後，可以進行單切的步驟，此時切割刀會沿著半導體 晶圓200之切割道(scribe-line)來切割半導體晶圓2〇〇，藉以 形成多個獨立的晶片結構205。 清參照圖38 ’在本實施例中，由於金屬柱292之柱狀金 屬層294的橫向尺寸係小於防崩落層295的橫向尺寸，因此 當在進行迴焊製程時，由焊料層296所溶化的焊料並不會沿 著柱狀金屬層294的侧壁流下，故可以避免發生焊料層296 崩落的情形。 在上述的製程中，凸塊290係僅由電鍍製程即可形成底 部金屬層293、柱狀金屬層294、防崩落層295及焊料層296， 可以省去減鍍製程，故形成凸塊290的步驟可以簡化。 然而，在實際運作上，亦可以省去底部金屬層293的配 置，亦及材質比如係為銅或是含鉛量高的錫鉛合金之柱狀金 21 1284385 15625twf.doc/006 屬層294可以直接接觸地形成在金屬層254的線路圓案254a 上及接墊圖案254b上，如圖39所示。在較佳的情況下，材質 為銅的柱狀金屠層294係適於直接接觸地形成在頂部表面材 質係為銅、鎳或金的金屬線路250上或接墊251上，此時金 屬線路250及接整251比如係具有如圖22至圖25所示之金 屬層结構。 6·製作金屬線路及第一種形式之柱狀凸塊的第二種方法 此外，本發明的製程亦可以結合製作柱狀凸塊的製程, 如圖40及圖41所示，其繪示依照本發明第一實施例中在丰導 體晶圓上製作金屬線路及第一種形式之柱狀凸塊的第二種製作方 法之剖面示意圖，其中圖40及圖41係接續圖16的步驟。 在具有線路圖案254a及接墊圖案2541)的金屬層254製 作完成之後，如圖16所示，可以再形成光阻層270在光阻層 260上及金屬層254上，光阻層270具有開口 272 ,暴露出金屬 層254之線路圖案254a及接塾圖案254b，如圖40所示。 請繼續參照圖40,接著可以利用電鍍的方式依序形成金屬 柱292及焊料層296在光阻層270之開口 272所暴露出之金 屬層254的線路圖案254a上及接墊圖案2541)上，其中在形成 金屬柱292時，比如係利用電鍍製程依序形成底部金屬層 293、柱狀金屬層294及防崩落層295。底部金屬層293之材 質比如係為鎳，其中由鎳所構成之底部金屬層293比如可以 直接接觸地形成在具有圖22至圖25所示之金a廢纟士槿的金 屬線路250上或接墊251上；當在形成柱狀金屬脣;;4時， 比如是利用電鍵的方式形成厚度介於8微米至1〇〇微米的鋼 層在底部金屬層293 Ji，或者比如是利用電鍍的方式形成厚 度介於8微米至100微米之含錯量高的锡錯合金層在底部金 屬層293上；當在形成防崩落層295時，比如是利用電鍵的 22 1284385 15625twf.doc/006 方式形成厚度介於l微米至10微米的鎳層在柱狀金屬層294 上。在本實施例中，焊料層29(S的材質比如係為錫鉛合金、 錫、錫銀合金或錫銀銅合金等，且焊料層296可以直接接觸 地形成在金屬柱292之鎳層295上，且位在光阻層270之開 口 272 中0 . .. .. 接著’可以依序去除光阻層270、260，暴露出底部金屬 層252，如圖41所示。在接下來的步驟中，係如圖36至圓38 所示，且相關說明在前述的第5點中已有詳盡的說明，在此 便不再贅述。此外，在利用第二種方法形成金屬柱292時， 亦可以省去電鍍底部金屬層293的步驟，如圖39所示，相關 說明在前述之第5點中已有敘述，在此便不再贅述。 7·製作金屬線路及第二種形式之柱狀凸塊的第一種方法 圖42至圖46繪示依照本發明第一實施例中在半導體晶圓 上製作金屬線路及第二種形式之柱狀凸塊的第一種製作方法之剖 面示意圖，其中圖42至圖46係接續圖17的步驟。 在具有線路圖案254a及接墊圖案254b的金屬層254製 作完成之後，如圖17所示，還可以形成光阻層270在底部金 屬層252上及金屬層254上，光阻層270具有開口 272，暴露出 金屬層254之線路圖案254a及接塾圖案254b，如圖42所示。 請繼續參照圖42，接著可以利用電鍍的方式形成金屬柱292 在光阻層270之開口 272所暴露出之金屬層254的線路圓案 254a上及接墊圖案254b上，其中在形成金屬柱292時，比如 係利用電鍍製程依序形成底部金屬層293、柱狀金屬層294 及防崩落層295。底部金屬層293之材質比如係為鎳，其中 由鎳所構成之底部金屬層293比如可以直接接觸地形成在具 有圖22至圖25所示之金屬層結構的金屬線路250上或接整 251上；當在形成柱狀金屬層294時，比如是利用電鍍的方 23 1284385 15625twf.doc/006 式形成厚度介於8微米至100微米的銅層在底部金屬層293 上、’或者比如是利用電鍍的方式形成厚度介於8微米至1〇〇 微米之含鉛量高的錫鉛合金層在底部金屬層293上」當在形 成防崩落層295時，比如是利用電鍍的方式形成厚度介於1 微米至10微米的鎳層在柱狀金屬層294上a 山揍著，形成光阻層275在光阻層270上及金屬柱292之 防崩落層295上，如圖43所示，其中光阻層275具有開口 276， 暴露出金屬柱292之防崩落層295，值得注意的是，光阻層275 之開口 276的橫向尺寸係小於金屬柱292的橫向尺寸。接著， 可以形成焊料層296在光阻層275之開口 276所暴露出之金 屬柱292的防崩落層295上，如圖44所示，其中焊料層296 的材質比如係為錫鉛合金、錫、錫銀合金或錫銀銅合金等。 接著，可以依序去除光阻層275、270，暴露出底部金屬 層252，如圈45所示。接著，再以金屬層254作為蝕刻罩壁, 透過蝕刻的方式依序去除未被金屬層254覆蓋之底部金屬層 252的種子層及黏著/阻障層，僅留下位在金屬層254下的底 部金屬層252，如圖46所示，至此便完成製作凸塊291的製 程，其中凸塊291包括底部金屬層293、柱狀金屬層294、防 崩落層295及焊料層296。 之後，可以進行單切的步驟，此時切割刀會沿著半導體 晶圓200之切割道(scribe-line)來切割半導體晶圓200,藉以 形成多個獨立的晶片結構205。 請參照圖46，當在進行接合半導體晶圓200及一基板(未 繪示)時，由於凸塊291之焊料層296的橫向尺寸係小於金屬 枉292的橫向尺寸，因此即使在基板之焊罩層的開口係為甚 小的情況下，凸塊291之焊料層296亦可以輕易地插入到基 板之焊罩層的開口中，並與基板之焊罩層的開口所暴露出的 24 1284385 15625twf.doc/006 接點連接。 在上述的製程中，凸塊291係僅由電鍍製程即可形成底 部金屬層293、柱狀金屬層294、防崩落層295及焊料層296 , 可以省去濺鍍製程，故形成凸塊291的步輝可以簡化。 然而，在實際運作上，亦可以省去底部金屬層293的配 置，亦及材質比如係為銅或是含錯量高的錫銘合金之柱狀金 屬層294可以直接接觸地形成在金屬層254的線路圖案254a 上及接整圖案254b上’如圓47所示。在較佳的情況下，材質 為銅的柱狀金屬層294係適於直接接觸地形成在頂部表面材 質係為銅或金的金屬線路250上或接墊251上，此時金屬線 路250及接墊251比如係具有如圖22、圖23及圖25所示之 金屬層結構。 8·製作金屬線路及第二種形式之柱狀凸塊的第二種方法 圖48至圖52繪示依照本發明第一實施例中在半導體晶圓 上製作金屬線路及第二種形式之柱狀凸塊的第二種製作方法之剖 面不意圖’其中圖48至圖52係接續圓16的步驟。 在具有線路圖案254a及接墊圖案254b的金屬層254製 作完成之後，如圖16所示，還可以形成光阻層270在光阻層 260上及金屬層254上，光阻層270具有開口 272，暴露出金屬 層254之線路圖案254a及接墊圖案254b，如圖48所示。 請繼續參照圖48，接著可以利用電鍍的方式形成金屬柱292 在光阻層270之開口 272所暴露出之金屬層254的線路圖案 254a上及接墊圖案254b上，其中在形成金屬柱292時，比如 係利用電鍍製程依序形成底部金屬層293、柱狀金屬層294 及防崩落層295。底部金屬層293之材質比如係為錄，其中 由鎳所構成之底部金屬層293比如可以直接接觸地形成在具 有圖22至圖25所示之金屬層結構的金屬線路250上或接塾 25 1284385 15625twf.doc/006 251上；當在形成柱狀金屬層294時，比如是利用電鍍的方 式形成厚度介於8微米至1〇〇微米的銅層在底部金屬層293 上’或者比如是利用電鍍的方式形成厚度介於8微米至100 微米之含鉛量高的錫鉛合金層在底部金屬層293上:當在形 成防崩落層295時，比如是利用電鍍的方式形成厚度介於1 微米至10微米的鎳層在柱狀金屬層294上。 接著，形成光阻層275在光阻層270上及金屬柱292之 防崩落層295上，如圖49所示，其中光阻層275具有開口 276 , 暴露出金屬柱292之防崩落層295,值得注意的是，光阻層275 之開口 276的橫向尺寸係小於金展柱292的橫向尺寸。接著， 可以形成焊料層296在光阻層275之開口 276所暴露出之金 屬柱292的防崩落層295上，如圖50所示，其中焊料層296 的材質比如係為錫鉛合金、錫、錫銀合金或錫銀銅合金等。 接著，可以依序去除光阻層275、270、260，暴露出底 部金屬層252，如圖51所示。接著，再以金屬層254作為钕 刻罩壁，透過蝕刻的方式依序去除未被金屬層254覆蓋之底 部金屬層252的種子層及黏著/阻障層，僅留下位在金屬層254 下的底部金屬層252，如圖52所示。 之後，可以進行單切的步驟，此時切割刀會沿著半導體 晶圓200之切割道(scribe-line)來切割半導體晶圓2〇〇，藉以 形成多個獨立的晶片結構205。 請參照圖52 ,由於凸塊291之烊料層296的橫向尺寸係 小於金屬柱292的橫向尺寸，因此即使在基板之焊罩層的開 口係為甚小的情況下，凸塊291之焊料層296亦可以輕易地 插入到基板之焊罩層的開口中，並與基板之焊罩層的開口所 暴露出的接點連接。 此外，在利用第二種方法形成金屬柱292時，亦可以省 26 1284385 15625twf.doc/006 去電鍵底部金屬層293的步驟’如圖47所示’相關說明在前 述之第7點中已有敘述，在此便不再贅述。 9.聚合物層的配置 在前述的第一實施例中均是將金屬線路直接接觸地形成 在保護層上，然而本發明的應用並不限於此，亦可以形成聚 合物層在金屬線路與半導體晶圓之保護層之間，如圖53所 示，其繪示依照本發明第一實施例中保護層上具有金脣線路、 凸塊及聚合物層之晶片結構的剖面示意圖。 清參照圖53 ’在提供半導體晶圓200之後，可以形成聚 合物層245在半導體晶圓200之保護層240上，聚合物層245 具有多個開口 246，暴露出頂層之薄膜線路層236，金屬線路 250及接墊251可以透過聚合物層245之開口 246及保護層240 之開口 242連接頂層之薄膜線路層246。聚合物層245的厚 度k比如係大於1微米’且聚合物層245的材質比如是聚亞 醢胺(polyimide ’ PI)、苯基環丁稀(benzoCyCi〇butene，ACB)、 聚亞芳香基_(parylene)、多孔性介電材質或彈性體等。 10·金屬線路的功能 A·金屬線路係作為晶片結構之凸塊位置重配置之用 請參照圖21、圖39、圖46、圖47、圖52及圖53，藉 由金屬線路250可以重配置凸塊28〇、290、291的佈局位置， 金屬線路250係連接凸塊280、290、291及薄膜線路層246 之接點’其中與此接點電性連接之凸塊280、290、291的佈 局位置係相異於此接點的佈局位置。如此，金屬線路25〇可以 作為重配置佈局之用，亦即藉由金屬線路25()可以調整凸塊28〇 置位置或疋調整凸塊2⑹的電性順序⑼^娜丨評批放)。 ，電性上而言’位在半導體基底210之表層的電子元件 12可以輸出一電子訊號，經由薄膜線路層232、234、236、 27 1284385 15625twf.doc/006 金屬線路242及凸塊280、290、291可以傳輸至外界電路, 比如是基板或另一半導體晶片；或者，比如是基板或另一半 導體晶片的外界電路可以經由凸塊280、290、291、金屬線 路242及薄膜線路層236、234、232傳輸訊號至半導體基底 210之表層的電子元件212。 B·金展線路係作為晶片結構之内部訊號傳輸之用 圓54及圖55緣示依照本發明第一實施例之晶片結構的剖 面示意圖。請參照圖54及圖55，金屬線路242係作為晶片結 構205内部訊號傳輸之用，亦即電子元件212之其中一個(比 如是電子元件212a)係適在輸出一電子訊號，此電子訊號經由 薄膜線路層232、234、236並穿過保護層240後，傳輸至金 屬線路250，接著再穿過保護層24〇 ,並經由薄膜線路層236、 234、232傳輸至其他的電子元件212之至少其中一個(比如是1284385 15625twf.doc/006 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer structure and a method of fabricating the same, and more particularly to a method for fabricating a wafer structure which can simplify a process step and Miscellaneous structure. . . . . [Prior Art 1 With the rapid advancement of information products technology, it is not a difficult thing for humans to quickly obtain information thousands of miles away. The competitive advantage of enterprises is achieved through the establishment of efficient information. Products can do this. With the advancement of information products and the integration of various circuit designs, the latest single-chips generally offer more features than ever before. Due to the rapid development of semiconductor technology, the mass production of copper processes is successful, and through the integration of circuits, most of the signal transmission can be in the same single chip, so that the transmission path of the signal can be shortened and the performance of the chip can be improved. In order to cooperate with the integration of the integrated circuit and the package of the wafer, the wafer can be transferred from the wafer to the bump factory, and then the metal lines and bumps are formed on the protective layer of the wafer, thereby re-attaching the external contacts of the wafer. The layout, the steps of forming metal lines and bumps on the protective layer are generally as follows. 1 to 12 are schematic cross-sectional views showing a process of fabricating metal lines and bumps on a semiconductor wafer. Referring to FIG. 1 , a semiconductor wafer 1 is first provided. The semiconductor wafer 100 includes a semiconductor substrate 11 , a plurality of thin film dielectric layers 122 , 124 , and 126 , and a plurality of thin film circuit layers 132 , 134 , and 136 . A protective layer 140. The semiconductor substrate 110 has a plurality of electronic components 112, which are disposed on the surface layer of the active surface 114 of the semiconductor substrate 110, wherein the semiconductor substrate 110 is, for example, a germanium substrate, and is doped with five- or trivalent ions, such as Boron ions or phosphorus ions are formed to form a plurality of electronic components 112 on the surface of the semiconductor substrate 110. The electronic components 112 are, for example, metal oxide semiconductors or 1284385 15625 twf.doc/006 transistors. The plurality of thin film dielectric layers 122, 124, 126 are disposed on the active surface 114 of the semiconductor substrate no, wherein the thin film dielectric layers 122, 124, 126 are, for example, an oxonium compound, a hydrazine compound or a nitrogen oxide. Each of the thin film dielectric layers 132, 134, and 136 is disposed on one of the thin film dielectric layers 122, 124, and 126, and the material of the thin film wiring layers 132, 134, and 136 includes, for example, aluminum, copper, or tantalum. . The thin film dielectric layers 122, 124, and 126 have a plurality of via holes 121, 123, and 125. The thin film wiring layers 132, 134, and 136 can be electrically connected to each other through the via holes 121, 123, and 125 of the thin film dielectric layers 122, 124, and 126. The connection is made and electrically connected to the electronic component 112. The protective layer 140 is disposed on the thin film dielectric layers 122, 124, 126 and the thin film wiring layers 132, 134, 136, wherein the thickness z of the protective layer 140 is generally greater than 0.35 micrometers, and the structure of the protective layer 14 is, for example, a composite layer composed of a nitrogen arsenide compound layer, an oxonium compound layer, a phosphonium glass layer or at least one of the above materials. The protective layer 140 has a plurality of openings 142 exposing the thin film wiring layer 136 at the top layer. In Figs. 2 to 6, a schematic cross-sectional view showing a process of forming a metal line on a protective layer of a semiconductor wafer is shown. Referring to FIG. 2, a bottom metal layer 152 may be first formed on the protective layer 140 of the semiconductor wafer 1 and on the thin film wiring layer 136 exposed outside the opening 142 of the protective layer 140 by sputtering. Next, a photoresist layer 16 may be formed on the bottom metal layer 152. The photoresist layer 160 has an opening 162' to expose the bottom metal layer 152, as shown in FIG. Next, the metal pattern 154 of the wiring pattern can be formed by means of a key bond on the bottom metal layer 152 exposed by the opening I62 of the photoresist layer 160, as shown in FIG. Next, the photoresist layer 160 is removed, as shown in FIG. Thereafter, the metal pattern 154 of the line pattern is masked as a surname, leaving the uncovered bottom metal layer 152, as shown in FIG. Thus, the metal 1284385 · 15625twf.doc/006 line 150 composed of the bottom metal layer 152 and the metal pattern 154 of the wiring pattern is completed. Referring to FIG. 7, a polymer layer 170 may be formed on the metal line 150 and the protective layer 140, wherein the polymer layer 170 has a plurality of openings 172 exposing the metal lines 150 in FIGS. 8 to 12, A schematic cross-sectional view showing a process for forming a block on a protective layer of a semiconductor wafer. Referring to Figure 8, a bottom metal layer 182 can first be formed on the polymer layer 170 and exposed to the metal lines 150 outside the openings 172 of the polymeric poplar layer 170 by sputtering. Next, a photoresist layer 190 can be formed on the bottom metal layer 182. The photoresist layer 190 has an opening 192 exposing the bottom metal layer 182 as shown in FIG. Next, the metal pattern 184 of the bump pattern can be formed on the bottom metal layer 182 exposed by the opening 192 of the photoresist layer 190 by means of electric ore, as shown in FIG. Next, the photoresist layer 190 is removed, as shown in FIG. Thereafter, the unmasked bottom metal layer 182 is etched away by using the bump pattern metal layer 184 as an etch mask, as shown in FIG. Thus, the bump 180 composed of the bottom metal layer 182 and the metal layer 184 of the bump pattern is completed. Referring to FIG. 1 to FIG. 12, in forming the metal line 150 and the bump 180, the bottom metal layers 152 and 182 are respectively formed by sputtering, and the metal layer 154 and the bump pattern forming the line pattern are required. After the metal layer 184, the unmasked bottom metal layers 152, 182 are removed by etching, respectively, so that two sputtering steps and two etching steps are required, so that the conventional metal lines 150 are formed. The steps of bumps 180 are less efficient. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a wafer structure fabrication method in which the steps of fabricating bumps and the steps of fabricating metal traces can be integrated to simplify the process steps of forming metal traces and bumps. In addition, the object of the present invention is to provide a method for fabricating a wafer structure, which can form a copper layer or a gold layer having a thickness of more than 1 μm on a protective layer of a semiconductor wafer, 1284385 15625 twf.doc/006 as a metal line, and A gold or solder layer having a thickness greater than 3 microns can be formed over the protective layer of the semiconductor wafer to serve as a bump. Further, it is an object of the present invention to provide a wafer structure in which a metal wiring layer includes a gold layer or a solder layer having a thickness of more than 1 «layer or gold layer, and a slab of 3 micro. Further, it is an object of the present invention to provide a wafer structure in which the metal-free layer includes a gold layer or a tantalum layer having a thickness greater than 丨 micron _ layer or recorded, convex _ greater than 3 μm. Further, it is an object of the present invention to provide a wafer structure including a metal back and bumps wherein the metal lines can be placed on the protective layer and the bumps can be placed on the thin film wiring layer exposed by the openings of the protective layer. < In order to achieve the object of the present invention, the present invention provides a method for fabricating a wafer structure, first of all 'providing a semi-conductive wafer; then, forming a bottom metal layer on the semi-conducting circle; then forming a metal having a line pattern The layer is on the bottom metal =, and then the second metal layer forming the bump pattern is on the first metal layer after the first metal layer and the second metal layer are removed, and the bottom metal layer not covered by the first layer is removed. The invention further provides a method for fabricating a wafer structure, wherein the corpse is followed by a first metal layer forming a line pattern at the bottom, and a second metal layer forming a bump pattern on the bottom metal layer; The bottom metal layer not covered by the first metal layer and the second metal layer is strictly removed. Firstly, in the first round of the moon, the present invention proposes a method for fabricating a wafer structure. First, k is supplied to form a bottom metal layer, and then a layer having a line pattern and a bump pattern is formed; reading, re-stitching gold In order to achieve the object of the present invention, the present invention provides a method for fabricating a wafer structure, first of all 'for half of the wafer, and then 'forming the first gold layer in the semiconductor crystal On the circle, the thickness of the first gold layer is greater than 1 micron; then, a second gold is formed on the first gold layer, the thickness of the second gold layer being greater than 3 microns. In order to achieve the object of the present invention, the present invention provides a method for fabricating a wafer structure. First, a semiconductor wafer is provided; then, a bottom metal layer is formed on the semiconductor wafer; then, a first gold layer is formed on the bottom metal layer, first The gold layer has a degree of more than 1 micrometer; then, a second gold layer is formed on the bottom metal layer, and the thickness of the second gold layer is greater than 3 micrometers; thereafter, the first gold layer and the second gold layer are not removed. Cover the bottom metal layer. In order to achieve the object of the present invention, the present invention provides a method for fabricating a wafer structure. First, a semiconductor wafer is provided; then, a gold layer is formed on the semiconductor wafer, and a thickness of the gold layer is greater than 1 micrometer; and then, a tan layer is formed. On the gold layer, the thickness of the solder layer is greater than 3 microns. In order to achieve the object of the present invention, the present invention provides a wafer junction; a trench fabrication method, first, a semiconductor wafer is provided; then, a bottom metal layer is formed on the semiconductor wafer; then, a gold layer is formed on the bottom metal layer, and the gold layer The thickness is greater than 1 micron; then, a solder layer is formed on the bottom metal layer, the thickness of the solder layer being greater than 3 microns; thereafter, the bottom metal layer not covered by the gold layer and the solder layer is removed. In order to achieve the object of the present invention, the present invention provides a method for fabricating a wafer structure. First, a semiconductor wafer is provided; then, a copper layer is formed on the semiconductor wafer, and the thickness of the copper layer is greater than 1 micrometer; and then, a gold layer is formed. On the copper layer, the thickness of the gold layer is greater than 3 microns. In order to achieve the object of the present invention, the present invention provides a method of fabricating a wafer structure. First, a semiconductor wafer is provided; then, a bottom metal layer is formed on the semiconductor crystal 1284385 15625 twf.doc/006 circle; then, a copper layer is formed on the bottom metal layer. The thickness of the copper layer is greater than 1 micrometer; then, the gold layer is formed on the bottom metal layer, and the thick layer of the gold layer is 3 micrometers; after that, the bottom gold H not covered by the steel layer and the gold layer is removed. In order to achieve the object of the present invention, the present invention provides a method for fabricating a wafer structure. First, a semiconductor wafer is provided. Next, a copper layer is formed on the semiconductor wafer, and the thickness of the copper layer is greater than 1 year. Then, a solder pattern is formed. On the copper layer, the thickness of the layer is greater than 3 microns. ^ ^ ^ ^ ^ ^ ^ In order to achieve the object of the present invention, the present invention provides a method of fabricating a wafer structure, first, providing a semiconductor wafer; then, forming a bottom metal layer on the semiconductor wafer; and subsequently, forming a copper layer at the bottom On the metal layer, the thickness of the copper layer is greater than 1 micrometer; then, a solder layer is formed on the bottom metal layer, and the thickness of the solder layer is greater than 3 micrometers; thereafter, the bottom metal layer not covered by the copper layer and the solder layer is removed. In order to achieve the object of the present invention, the present invention provides a wafer junction; a trench fabrication method, first, a semiconductor wafer is provided; then, a first photoresist layer is formed on the semiconductor wafer, and the first photoresist layer has an opening to expose a semiconductor wafer; then, forming a first metal layer on the semiconductor wafer exposed by the opening of the first photoresist layer; then, removing the first photoresist layer; and then forming a second photoresist layer on the first metal a second photoresist layer having an opening exposing the first metal layer; then forming a second metal layer on the first metal layer exposed by the opening of the second photoresist layer; and then removing the second photoresist Floor. To achieve the objects of the present invention, the present invention provides a wafer structure comprising a semiconductor substrate, a plurality of thin film dielectric layers, a plurality of thin film wiring layers, a protective layer, a patterned metal layer, and bumps. The semiconductor substrate has electronic components, and the electronic components are disposed on a wide surface of the active surface of the semiconductor substrate. The thin film dielectric layer is disposed on the active surface of the semiconductor substrate, wherein the thin film dielectric layer has a via hole, and each of the thin film lines is disposed on one of the thin film dielectric layers, and the thin film circuit layer is borrowed. The conductive vias are electrically connected to the electronic components, and the protective layer is disposed on the thin film dielectric lip and the thin film wiring layer. The patterned metal is disposed on the thin film dielectric layer and the thin film wiring layer, and the patterned metal is patterned. The layer comprises a gold or copper layer having a thickness greater than 1 micron, wherein the patterned metal layer comprises a metal line. The bumps are on the patterned metal ruthenium layer and the bumps comprise a solder layer or a gold layer having a thickness greater than three. To achieve the objects of the present invention, the present invention provides a wafer structure comprising a semiconductor substrate, a plurality of thin film dielectric layers, a plurality of thin film wiring layers, a protective layer, metal lines, and bumps. The semiconductor substrate has electronic components that are disposed on a surface layer of the active surface of the semiconductor substrate. The thin film dielectric layer is disposed on the active surface of the semiconductor substrate, wherein the thin film dielectric layer has via holes, and each of the thin film wiring layers is disposed on one of the thin film dielectric layers, and the thin film wiring layers are connected to each other through the via holes. Electrically connected and electrically connected to the electronic component, the protective layer is disposed on the thin film dielectric layer and the thin film wiring layer, and the protective layer has an opening, and the contact of the thin film circuit layer of the top layer is exposed. The metal lines are disposed on the thin film dielectric layer and the thin film wiring layer, and the metal wiring includes a gold layer or a copper layer having a thickness greater than 丨 micron. The bumps are located on the contacts of the thin film wiring layer, and the bumps include a solder layer or a gold layer having a thickness greater than 3 microns. In order to achieve the present invention, the present invention provides a wafer structure including a semiconductor substrate, a plurality of thin film dielectric layers, a plurality of thin film wiring layers, a protective layer, metal lines, and bumps. The semiconductor substrate has electronic components that are disposed on the surface of the active surface of the semiconducting county. The thin film dielectric layer is disposed on the active surface of the semiconductor substrate, wherein the thin film dielectric layer has via holes, and each of the thin film circuit layers is mixed therein, the thin film dielectric is wide, and the thin film layer is electrically connected to each other through the via holes. The connection is electrically connected to the electronic component, and the protection layer 1284385 15625twf.doc/006 is disposed on the thin film dielectric layer and the thin film circuit layer, and the protective layer has an opening to expose the contact of the top layer of the ruthenium circuit layer. The metal lines are disposed on the thin dielectric layer and the thin film wiring layer, and the thickness of the metal lines is greater than 丨 micron, and the bumps are located at the junctions of the thin film wiring layers. The above and other objects, features and advantages of the present invention will become more <RTIgt; [Embodiment] First, a method for fabricating a wafer structure of the present invention will be described. Only by forming a layer of the bottom metal layer in one step, metal lines and bumps can be formed in the next step. This simplifies the process steps. Second, the first method of the method of making a wafer crucible. The first method for fabricating metal lines and bumps. FIG. 13 to FIG. 21B show the wafer in a semi-guide wafer according to the first embodiment of the present invention. A schematic cross-sectional view of a first method of fabricating metal lines and bumps. Referring to FIG. 13, a semiconductor wafer 200 is first provided. The semiconductor wafer 2 includes a semiconductor substrate 210, a plurality of thin film dielectric layers 222, 224, and 226, and a plurality of thin film circuit layers 232, 234, and 236. Layer 240. The semiconductor substrate 210 has a plurality of electronic components 212 disposed on a surface layer of the active surface 214 of the semiconductor substrate 210. The semiconductor substrate 210 is, for example, a germanium substrate, and is doped with pentavalent or trivalent ions, such as It is a boron ion or a phosphorus ion, thereby forming a plurality of electronic components 212 on the surface layer of the semiconductor substrate 210, such as a metal oxide semiconductor device, a transistor or other type of electronic component. The plurality of thin film dielectric layers 222, 224, 226 are disposed on the active surface 214 of the semiconductor substrate 210, wherein the thin film dielectric layers 222, 224, 226 are, for example, oxonium compounds, arsenide compounds or oxynitride compounds, etc. The film circuit layers 232, 234, and 236 are respectively disposed on one of the thin film dielectric layers 222, 224, 12 1284385 1 S62Stwf. doc / 006 226, wherein the material of the thin film circuit layers 232, 234, 236 includes, for example, aluminum, copper or Hey. The thin film dielectric layers 222, 224, 226 have a plurality of via holes 221, 2M, 2M, and the thin film wiring layers 232, 234 v 236 can be transferred from the via holes 221 of the thin film dielectric layers 222, 224, 226, the public 3, 225 to each other. Electrically connected and electrically connected to the electronic component 212. The protective layer 240 is disposed on the thin film dielectric layers 222, 224, 226 and the thin film wiring layers 232, 234, 236, wherein the thickness z of the protective layer 240 is generally greater than 0.35 micrometers, and the structure of the protective layer 240 is, for example, one. a composite layer of a nitrogen arsenide compound layer, an oxonium compound layer, a squamous glass layer or at least one of the above-mentioned opposite materials. The protective layer 240 has a plurality of openings 242 exposing the contacts 236a, 236b of the thin film wiring layer 236 at the top layer. Referring to FIG. 14 ' after the semiconductor wafer 2 is provided, the thin film wiring layer 236 of the bottom metal layer 250 on the protective layer 240 of the semiconductor wafer and exposed outside the opening 242 of the protective layer 240 may be formed by sputtering. At the junction, in the process, for example, the first sputter adhesion/barrier layer is on the protective layer 240 of the semiconductor wafer 2 (8) and the thin film wiring layer 236 exposed outside the opening 242 of the protective layer 240, and then splashed. The plating seed layer is on the adhesion/barrier layer, and the materials of the adhesion/barrier layer and the seed layer are described later, and will not be described here. Next, a photoresist layer 260 can be formed over the bottom metal layer 252, and the photoresist layer 260 has openings 262 that expose the bottom metal layer 252, as shown in FIG. Then, the metal layer 254 can be formed on the bottom metal layer 252 exposed by the opening 262 of the photoresist layer 26 by electroplating, as shown in FIG. 16, wherein the metal layer 254 includes the wiring, the case 254a and the pad pattern. 254b, the circuit pattern 254a of the metal layer 254 is electrically connected to the contact 236a of the thin film circuit layer 236, and extends over the protective layer 240; the pad pattern 254b of the metal layer 254 is electrically connected to the contact 236b of the thin film circuit layer 236, and It is located on the junction 236b of the thin film wiring layer 236. The plane 1000 is substantially parallel to the active surface 214 of the semiconductor substrate 13 1284385 15625 twf.doc/006 bottom 210. Please refer to FIG. 16A, which illustrates the circuit pattern 254a and the pad pattern of the metal layer 254 of FIG. The extension pattern of the line pattern 2543 of the schematic 0 metal layer 254 projected onto the plane 1000 onto the plane 1000 is projected to the plane 1〇〇〇 (the distance of the path 10 extending from the p point to the q point in FIG. 16A) is, for example, greater than 500 μm, or For example, it is greater than 800 microns, or such as greater than 1200 microns; the area of the line pattern 254a of the metal layer 254 is projected onto the plane 1〇〇〇 (the area of the diagonal line of the line 254a in FIG. 16A), for example, greater than 30,000 square microns. Or, for example, greater than 8 square microns, or such as greater than 150,000 square microns. The photoresist layer 260 can then be removed/exposed to expose the bottom metal layer 252 as shown in FIG. Thereafter, a photoresist layer 27 may be formed on the bottom metal layer 2 and the metal layer 254. The photoresist layer 270 has an opening 272 to expose the line pattern 254a and the pad pattern 254b of the metal layer 254, as shown in FIG. Show. "Next, a metal layer 28 as a bump may be formed by electroplating on the wiring pattern 254a of the metal layer 254 exposed by the opening 272 of the photoresist layer 270 and on the pad pattern 254b, as shown in FIG. It is worth noting that the area of each convex 280 projected onto the plane 1 比如 is, for example, less than, for example, the square of the square ^ square ^ is less than 2 〇 10,000 square micrometers, or, for example, less than the coffee 00 can then be removed The photoresist layer 270 exposes the bottom metal layer 252, and then the metal layer 254 is used as an etch mask to remove the layer 252 of the bottom metal layer 252 that is not covered by the metal layer 254. Only the bottom metal located under the metal layer 254 can be backed up. When the bump 28G includes the solder layer, the surface is further (not shown). The 'cursion' allows the top surface of the bump 280 to form a smooth surface. A single-cut step can then be performed, at which point the dicing blade cuts the semiconductor ridges along the seribe_line of the semiconductor 1284385 15625 twf.doc/006 wafer 200, thereby forming a plurality of individual wafer structures 205. In the above process The metal line 250 is composed of a bottom metal layer 252 formed by a sputtering process and a wiring pattern 254a of the metal layer 254 formed by the plating process, and the bump 280 is formed only by a gold layer formed by an electroplating process. Compared with the conventional process for forming metal lines and bumps, the present invention can eliminate the sputtering process when the bumps 280 are formed, so that the steps of forming the metal lines 250 and the bumps 280 can be simplified. Referring to FIG. 21, the metal line 250 is formed by a bottom metal layer 252 formed by a sputtering process and a circuit pattern 254a of a metal layer 254 formed by a key bonding process. The pad 251 is formed by a sputtering process. The bottom metal layer 252 and the pad pattern 254b of the metal layer 254 formed by the electroplating process are formed, and the metal layer structure of the pad 251 is the same as the metal layer structure of the metal line 250. The detailed structure is as follows. Referring to FIG. 22, a first schematic view of a first metal layer structure of a metal circuit and a pad according to a first embodiment of the present invention is shown in FIG. In the case of the metal layer 252, for example, the adhesion/barrier 2521a is formed by a sputtering process, and then a gold layer 2521b as a seed layer is formed on the adhesion/barrier layer 2521a by sputtering, wherein the adhesion/barrier is formed. The material of the layer 2521a is, for example, titanium, titanium tungsten alloy, titanium nitride compound, button or nitrogen compound, etc. When the metal layer 254 is formed, for example, a gold layer having a thickness X greater than 1 μm is formed by electroplating in the bottom metal layer. Referring to FIG. 23, a second metal layer structure of the metal circuit and the pad according to the first embodiment of the present invention is shown in FIG. A cross-sectional view in which a bottom layer 15 1284385 15625 twf.doc/006 metal layer 252 is formed, for example, a sputtering/barrier layer 2522a is formed by a sputtering process, and then a copper layer 2522b as a seed layer is formed by means of de-plating. The adhesive/barrier layer 2522a has a material such as chromium, titanium, titanium tungsten alloy, titanium nitride compound, button or bismuth nitride compound, or adhesion/barrier layer 2522a. By sequentially deposited chromium layer and the chromium copper alloy layer formed 'wherein the chromium-based copper alloy layer on the chromium layer bits. In forming the metal layer 254, for example, a thickness is formed by electroplating: a copper layer of more than 1 mark is placed on the seed layer 2522b of the bottom metal layer 252. Referring to FIG. 24, a third schematic diagram of a third metal layer structure of a metal circuit and a pad according to a first embodiment of the present invention, wherein a bottom portion is formed In the case of the metal layer 252, for example, an adhesion/barrier layer 2523a is formed by a sputtering process, and then a copper layer 2523b as a seed layer is formed on the adhesion/barrier layer 2523a by sputtering, wherein the adhesion/barrier layer For example, the material is such as chromium, titanium, titanium alloy, titanium nitride, group or group of nitrogen compounds, or the adhesion/barrier layer 2523a can also be formed by sequentially secreting layers and copper alloy layers. The chrome-copper alloy layer is located on the chrome layer. When the metal layer 254 is formed, a thickness χ is formed on the seed layer 2523b of the bottom metal layer 252 by a thickness χ greater than i, and then a nickel layer 2543b is formed on the copper layer 2543a by electroplating. . D. Metal circuit and the fourth metal layer structure of the pad. Please refer to FIG. 25, which is a cross-sectional view showing the structure of the fourth metal layer and the fourth metal layer structure according to the first embodiment of the present invention. In the case of the gold layer 25j, for example, the adhesion/barrier layer 2524' is formed by a sputtering process, and then the copper layer 2524b as a seed layer is formed on the adhesion/barrier layer 252 as described above, wherein the adhesion/barrier is formed. The material of the layer 2s24a is, for example, chromium, titanium, titanium alloy, money compound, neon or subtractive compound, etc., 16 1284385 15625twf.doc/006 or the adhesion/barrier layer 2524a may also be deposited by sequential deposition of chromium layer and chromium copper. The alloy layer is formed, wherein the chrome-copper alloy layer is on the chromium layer. When the metal layer 254 is formed, for example, a copper layer 2544a having a thickness X greater than 1 μm is first formed on the seed layer 2524b of the bottom metal layer 252 by electroplating, and then a nickel layer 2544b is formed on the copper layer 2544a by means of electroplating. The gold layer 2544c is formed on the nickel layer 2544b by means of a key. 3. Structure of the bumps In the first embodiment described above, the bumps 280 are electrically connected to the circuit pattern 254a of the metal layer 234 and the art pattern 254b. The detailed structure of the metal layer of the bumps 280 is as follows. . A. First bump structure 凊 Referring to Fig. 26 is a schematic cross-sectional view showing the first bump structure not according to the first embodiment of the present invention. When the bumps 280 are formed, for example, a gold layer 2801 having a thickness y greater than 3 μm is formed on the wiring pattern 254a of the metal layer 254 and the pad pattern 254b by a key bonding process, wherein the gold layer 2801 can be formed in direct contact with the pattern. 22 to the metal line 250 of the metal layer structure shown on FIG. 25 or to the pad 251. The gold layer 2801 used as the bump 280 is formed, for example, in a direct contact manner on the metal line 250 whose top surface material is gold or copper or on the pad 251. At this time, the metal line 250 and the pad 251 have a structure as shown in FIG. 22, for example. The metal layer structure shown in Fig. 23 or Fig. 25. B. Second Bump Structure Referring to Figure 27, there is shown a cross-sectional view of a second bump structure in accordance with a first embodiment of the present invention. When the bumps 280 are formed, for example, a nickel layer 2802a may be formed on the circuit pattern 254a of the metal layer 254 and the pad pattern 254b by using an electroplating process, wherein the nickel layer 2802a of the bumps 280 may be formed in direct contact with, for example, a pattern. 22 to the metal line structure of the metal layer 250 shown in FIG. 25 or on the pad 251; then, the plating process can be further used to form a gold layer 2802b having a thickness of 17 1284385 15625 twf.doc / 006 degrees y greater than 3 microns in the nickel layer 2802a on. C. Third Bump Structure A cross-sectional view of the second bump structure in which the edge is not in accordance with the first embodiment of the present invention is referred to in Fig. 28 of the present invention. When the bumps 280 are formed, for example, a nickel layer 2803a is formed on the wiring pattern 254a of the metal layer 254 and the pad pattern 254b by an electroplating process, wherein the bumps 280 are formed. < Nickel layer 2803a may be formed, for example, directly on metal wiring 250 having the metal layer structure shown in Figs. 22 to 25 or on pad 251; then, an electroplating process is used to form solder layer 2803b having a thickness y of more than 3 μm. On the nickel layer 2803a, the material of the solder layer 28031> is, for example, tin-lead alloy, tin, tin-silver alloy or tin-silver-copper alloy. D. Fourth Bump Structure Referring to Figure 29, there is shown a cross-sectional view of a fourth bump structure in accordance with a first embodiment of the present invention. When the bumps 280 are formed, for example, a copper layer 2804a is formed on the circuit pattern 254a of the metal layer 254 and the pad pattern 254b by an electric forging process, wherein the copper layer 2804a of the bumps 280 can be formed, for example, in direct contact with The metal wiring 250 of the metal structure shown in Figs. 22 to 25 or the pad 251. Next, a nickel layer 2804b can be formed in the copper layer 2804a by an electroplating process. Then, a solder layer 2804c having a thickness y greater than 3 μm can be further formed on the nickel layer 2804b by using an electroplating process, wherein the material of the solder layer 2804c is, for example, tin-lead alloy, tin, tin-silver alloy or tin-silver-copper alloy. 4. Second method for fabricating metal lines and bumps The greatest difference between the first fabrication method and the second fabrication method is the step of forming a photoresist layer and removing the photoresist layer, in the first method described above. Before the photoresist layer for defining the shape and position of the bump is formed, the photoresist layer for defining the shape and position of the metal trace is removed. However, the application of the present invention is not limited thereto, and may be as follows. The second method of fabrication is described. 30 to FIG. 33 are schematic cross-sectional views showing a second method of fabricating a metal line and a bump on a semiconductor wafer in accordance with a first embodiment of the present invention, wherein FIG. 3A to FIG. 33 are used. Follow the steps of Figure π. After forming the metal layer 254, as shown by the circle 16, the photoresist layer 270 may be further formed on the metal layer 254 and the photoresist layer 260, as shown in FIG. 33, wherein the photoresist layer 270 has an opening 272 to expose the metal. Line pattern 254 & and pad pattern 254b of layer 254. Then, a metal layer 280 as a bump can be formed by electroplating on the line pattern 254a of the metal layer 254 exposed by the opening 272 of the photoresist layer 270 and on the pad pattern 2541), as shown in FIG. The area of each bump 280 projected onto the plane 1 比如 is, for example, less than 3 〇〇〇〇 square microns, or such as less than 2 〇, 〇〇〇 square microns, or such as less than 15 〇〇〇 square microns. Next, the photoresist layers 270, 260 may be sequentially removed to expose the bottom metal layer 252 as shown in FIG. Then, the metal layer 254 is used as an etching mask, and the seed layer and the adhesion/barrier layer of the bottom gold layer 252 not covered by the metal layer 254 are sequentially removed by etching, leaving only the metal layer 254. The bottom metal layer 252 is as shown in FIG. When the bump 280 includes a solder layer, the step of reflowing can be performed so that the top surface of the bump 28 can form a smooth surface (not shown in green). Thereafter, a single-cut step can be performed in which the dicing blade cuts the semiconductor wafer 2 along the scribe line of the semiconductor wafer 200 to form a plurality of individual wafer structures 205. In the above process, the metal line 250 is formed by the bottom metal layer 252 formed by the sputtering process and the wiring pattern 254a of the metal layer 254 formed by the electroplating process, and the bump 280 is formed only by the electroplating process. The metal layer is formed. Compared with the conventional process for forming metal lines and bumps, the present invention can eliminate the sputtering process when the bumps 280 are formed, so that the steps of forming the metal lines 250 and the bumps 280 can be simplified. 1284385 15625twf.doc/006 In addition, the structure of the metal lines, pads and bumps is as described in points 2 and 3 above, and will not be described here. ^ The first method of fabricating a metal line and a columnar bump of the first form is externally, and the process of the present invention can also be combined with the process of making a columnar bump, as shown in FIGS. 34 to 38. A cross-sectional schematic circle of a first method of fabricating a metal line and a first type of stud bump on a semiconductor wafer in accordance with a first embodiment of the present invention, wherein FIGS. 34-38 are continued from FIG. After the metal layer 254 having the line pattern 254a and the pad pattern 254b is completed, as shown in FIG. 17, a photoresist layer 270 may be formed on the bottom metal layer 252 and the metal layer 254, and the photoresist layer 270 has an opening 272. The line pattern 254a and the interface pattern 254b of the metal layer 254 are exposed as shown in FIG. Referring to FIG. 34, the metal pillars 292 and the solder layer 296 may be sequentially formed by electroplating on the line pattern 254a of the metal layer 254 exposed by the opening 272 of the photoresist layer 270 and the pad pattern 254b. When the metal pillars 292 are formed, for example, the bottom metal layer 293, the columnar metal layer 294, and the anti-disintegration layer 295 are sequentially formed by an electroplating process. The material of the bottom metal layer 293 is, for example, nickel, and the bottom metal layer 293 composed of nickel can be formed, for example, directly on the metal line 250 having the metal layer structure shown in FIGS. 22 to 25 or on the pad 251. When forming the columnar metal layer 294, for example, a copper layer having a thickness of 8 μm to 1 μm is formed on the bottom metal layer 293 by electroplating, or is formed by electroplating, for example, by a thickness of 8 A tin-lead alloy layer having a high lead content of 1 μm to 1 μm on the bottom metal layer 293, when forming the anti-crash layer 295, for example, using an electric ore to form a thickness of 1 μm to 10 μm The layer is on the columnar metal layer 294. In this embodiment, the material of the solder layer 2% is, for example, a tin-lead alloy, a tin-silver alloy or a tin-silver-copper alloy, and the solder layer 296 may be directly contacted on the nickel layer 295 of the metal pillar 292, and It is located in the opening 20 1284385 15625twf.doc/006 272 of the photoresist layer 270. Next, the photoresist layer 270 can be removed to expose the bottom metal layer 252, as shown in FIG. Next, the pillar metal layer 294 of the metal pillar 292 may be etched from the sidewall of the metal pillar 292 such that the area projected onto the plane 1000 by the pillar metal layer 294 may be smaller than the area projected onto the plane 1000 by the collapse prevention layer 295 or the solder layer 296. And the edge of the lower surface of the anti-disintegration layer 295 may be exposed, as shown in FIG. Then, the metal layer 254 is used as an etching wall, and the seed layer and the adhesion/barrier layer of the bottom metal layer 252 not covered by the gold layer 254 are sequentially removed by etching, leaving only the metal layer 254. The bottom metal layer 252 is as shown in FIG. Next, a step of reflowing can be performed so that the top surface of the solder layer 296 can form a smooth surface, as shown in Fig. 38, and thus the process of forming the bumps 290 is performed. In this embodiment, after the bump 290 can include the bottom metal layer 293, the columnar metal layer 294, the anti-disruption layer 295, and the solder layer 296, a single-cut step can be performed, where the dicing blade is along the semiconductor wafer. A scribe-line of 200 cuts the semiconductor wafer 2 to form a plurality of individual wafer structures 205. Referring to FIG. 38', in the present embodiment, since the lateral dimension of the columnar metal layer 294 of the metal post 292 is smaller than the lateral dimension of the anti-disintegration layer 295, it is melted by the solder layer 296 when the reflow process is performed. The solder does not flow down along the sidewall of the columnar metal layer 294, so that the occurrence of the solder layer 296 falling apart can be avoided. In the above process, the bump 290 can form the bottom metal layer 293, the columnar metal layer 294, the anti-crash layer 295 and the solder layer 296 only by the electroplating process, and the deplating process can be omitted, so that the bumps 290 are formed. The steps can be simplified. However, in actual operation, the configuration of the bottom metal layer 293 can also be omitted, and the material is, for example, copper or a tin-lead alloy with a high lead content. The columnar gold 21 1284385 15625 twf.doc/006 Direct contact is formed on the line circle 254a of the metal layer 254 and on the pad pattern 254b as shown in FIG. In a preferred case, the columnar gold layer 294 of copper is suitable for direct contact on the metal line 250 of the top surface material of copper, nickel or gold or the pad 251. 250 and 251 have, for example, a metal layer structure as shown in FIGS. 22 to 25. 6. Second method for fabricating a metal line and a columnar bump of the first form. In addition, the process of the present invention can also be combined with a process for fabricating a columnar bump, as shown in FIGS. 40 and 41, which is depicted in accordance with A cross-sectional view of a second method of fabricating a metal line and a first type of stud bump on a conductive conductor wafer in accordance with a first embodiment of the present invention, wherein FIGS. 40 and 41 are subsequent to the steps of FIG. After the metal layer 254 having the wiring pattern 254a and the pad pattern 2541) is completed, as shown in FIG. 16, the photoresist layer 270 may be further formed on the photoresist layer 260 and the metal layer 254, and the photoresist layer 270 has an opening. 272, the line pattern 254a and the interface pattern 254b of the metal layer 254 are exposed, as shown in FIG. Referring to FIG. 40, the metal pillars 292 and the solder layer 296 may be sequentially formed by electroplating on the line pattern 254a of the metal layer 254 exposed by the opening 272 of the photoresist layer 270 and the pad pattern 2541). When the metal pillars 292 are formed, for example, the bottom metal layer 293, the columnar metal layer 294, and the anti-disintegration layer 295 are sequentially formed by an electroplating process. The material of the bottom metal layer 293 is, for example, nickel, and the bottom metal layer 293 composed of nickel may be formed in direct contact with the metal line 250 having the gold a waste scorpion shown in FIG. 22 to FIG. On the pad 251; when forming the columnar metal lip; 4, for example, using a key to form a steel layer having a thickness of 8 μm to 1 μm in the bottom metal layer 293 Ji, or for example, by means of electroplating Forming a high-missing tin-alloy layer having a thickness of 8 μm to 100 μm on the bottom metal layer 293; when forming the anti-crack layer 295, for example, a thickness is formed by using a 22 1284385 15625 twf.doc/006 method of a bond A layer of nickel between 1 micrometer and 10 micrometers is on the columnar metal layer 294. In the present embodiment, the solder layer 29 (the material of S is, for example, tin-lead alloy, tin, tin-silver alloy or tin-silver-copper alloy, etc., and the solder layer 296 can be formed in direct contact with the nickel layer 295 of the metal pillar 292. And located in the opening 272 of the photoresist layer 270 0 . . . . . . . . . then the photoresist layer 270, 260 can be removed sequentially, exposing the bottom metal layer 252, as shown in Figure 41. In the next step , as shown in FIG. 36 to circle 38, and the related description has been described in detail in the above-mentioned fifth point, and will not be described again here. Further, when the metal pillar 292 is formed by the second method, The step of electroplating the bottom metal layer 293 is omitted, as shown in FIG. 39, and the related description has been described in the above-mentioned fifth point, and will not be described again here. 7. The metal wiring and the second form of the columnar convex are produced. FIG. 42 to FIG. 46 are schematic cross-sectional views showing a first method of fabricating a metal line and a columnar bump of a second form on a semiconductor wafer in accordance with a first embodiment of the present invention, wherein 42 to 46 are the steps subsequent to Fig. 17. The wiring pattern 254a is connected After the metal layer 254 of the pattern 254b is completed, as shown in FIG. 17, a photoresist layer 270 may be formed on the bottom metal layer 252 and the metal layer 254. The photoresist layer 270 has an opening 272 to expose the metal layer 254. The pattern 254a and the interface pattern 254b are as shown in Fig. 42. Referring to Fig. 42, the wiring pattern 254a of the metal layer 254 exposed by the opening 272 of the photoresist layer 270 may be formed by electroplating. The upper and the pad patterns 254b, wherein the metal pillars 292 are formed, for example, the bottom metal layer 293, the columnar metal layer 294, and the anti-disruption layer 295 are sequentially formed by an electroplating process. The material of the bottom metal layer 293 is, for example, nickel. The bottom metal layer 293 composed of nickel may be formed, for example, in direct contact on the metal wiring 250 having the metal layer structure shown in FIGS. 22 to 25 or on the finishing 251; when the columnar metal layer 294 is formed. For example, a copper layer having a thickness of 8 μm to 100 μm is formed on the bottom metal layer 293 by using an electroplated square 23 1284385 15625 twf.doc/006, or a thickness of 8 is formed by, for example, electroplating. A tin-lead alloy layer having a high lead content of 1 to 10 μm on the bottom metal layer 293" when forming the anti-crash layer 295, for example, forming a nickel layer having a thickness of 1 μm to 10 μm by electroplating On the columnar metal layer 294, a mountain is formed, and a photoresist layer 275 is formed on the photoresist layer 270 and the anti-crack layer 295 of the metal pillar 292, as shown in FIG. 43, wherein the photoresist layer 275 has an opening 276, which is exposed. Out of the anti-disintegration layer 295 of the metal post 292, it is noted that the lateral dimension of the opening 276 of the photoresist layer 275 is less than the lateral dimension of the metal post 292. Then, a solder layer 296 can be formed on the anti-crash layer 295 of the metal pillar 292 exposed by the opening 276 of the photoresist layer 275, as shown in FIG. 44, wherein the solder layer 296 is made of tin-lead alloy, tin, or the like. Tin-silver alloy or tin-silver-copper alloy. Next, the photoresist layers 275, 270 can be sequentially removed to expose the bottom metal layer 252 as shown by the circle 45. Then, the metal layer 254 is used as an etching mask, and the seed layer and the adhesion/barrier layer of the bottom metal layer 252 not covered by the metal layer 254 are sequentially removed by etching, leaving only the bottom under the metal layer 254. The metal layer 252, as shown in FIG. 46, has thus completed the process of fabricating the bumps 291, wherein the bumps 291 include a bottom metal layer 293, a columnar metal layer 294, a collapse prevention layer 295, and a solder layer 296. Thereafter, a single-cut step can be performed in which the dicing blade cuts the semiconductor wafer 200 along the scribe-line of the semiconductor wafer 200, thereby forming a plurality of individual wafer structures 205. Referring to FIG. 46, when the semiconductor wafer 200 and a substrate (not shown) are bonded, since the lateral dimension of the solder layer 296 of the bump 291 is smaller than the lateral dimension of the metal crucible 292, even the solder mask of the substrate In the case where the opening of the layer is small, the solder layer 296 of the bump 291 can also be easily inserted into the opening of the solder mask layer of the substrate and exposed to the opening of the solder mask layer of the substrate by 24 1284385 15625 twf. Doc/006 Contact connection. In the above process, the bump 291 can form the bottom metal layer 293, the columnar metal layer 294, the anti-crack layer 295 and the solder layer 296 only by the electroplating process, and the sputtering process can be omitted, so that the bump 291 is formed. Steps can be simplified. However, in actual operation, the configuration of the bottom metal layer 293 can also be omitted, and the material such as copper or a columnar metal layer 294 containing a high amount of tin alloy can be directly contacted to form the metal layer 254. 'on line pattern 254a and on pattern 254b' is shown as circle 47. In a preferred case, the columnar metal layer 294 made of copper is suitable for direct contact on the metal line 250 of the top surface material of copper or gold or the pad 251, and the metal line 250 is connected. The pad 251 has, for example, a metal layer structure as shown in FIGS. 22, 23, and 25. 8. A second method of fabricating a metal trace and a second form of stud bumps. FIGS. 48-52 illustrate a metal trace and a second form of post on a semiconductor wafer in accordance with a first embodiment of the present invention. The cross section of the second fabrication method of the bumps is not intended to be 'the steps of Figs. 48 to 52 to join the circle 16. After the metal layer 254 having the wiring pattern 254a and the pad pattern 254b is completed, as shown in FIG. 16, a photoresist layer 270 may be formed on the photoresist layer 260 and the metal layer 254, and the photoresist layer 270 has an opening 272. The line pattern 254a and the pad pattern 254b of the metal layer 254 are exposed as shown in FIG. Referring to FIG. 48, the metal pillars 292 may be formed on the wiring pattern 254a of the metal layer 254 exposed by the opening 272 of the photoresist layer 270 and the pad pattern 254b by electroplating, wherein the metal pillars 292 are formed. For example, the bottom metal layer 293, the columnar metal layer 294, and the anti-disintegration layer 295 are sequentially formed by an electroplating process. The material of the bottom metal layer 293 is recorded, for example, wherein the bottom metal layer 293 composed of nickel can be formed in direct contact with the metal line 250 having the metal layer structure shown in FIGS. 22 to 25 or the interface 25 1284385. 15625twf.doc/006 251; when forming the columnar metal layer 294, for example, by electroplating, a copper layer having a thickness of 8 μm to 1 μm is formed on the bottom metal layer 293' or by electroplating, for example. A method of forming a tin-lead alloy layer having a high lead content of 8 micrometers to 100 micrometers on the bottom metal layer 293: when forming the anti-crash layer 295, for example, by electroplating to a thickness of 1 micron to A 10 micron nickel layer is on the columnar metal layer 294. Next, a photoresist layer 275 is formed on the photoresist layer 270 and the anti-crash layer 295 of the metal pillar 292, as shown in FIG. 49, wherein the photoresist layer 275 has an opening 276 exposing the anti-crash layer 295 of the metal pillar 292. It is noted that the lateral dimension of the opening 276 of the photoresist layer 275 is less than the lateral dimension of the gold pillar 292. Then, a solder layer 296 can be formed on the anti-crash layer 295 of the metal pillar 292 exposed by the opening 276 of the photoresist layer 275, as shown in FIG. 50, wherein the solder layer 296 is made of tin-lead alloy, tin, or the like. Tin-silver alloy or tin-silver-copper alloy. Next, the photoresist layers 275, 270, 260 may be sequentially removed to expose the bottom metal layer 252, as shown in FIG. Then, the metal layer 254 is used as the engraving mask wall, and the seed layer and the adhesion/barrier layer of the bottom metal layer 252 not covered by the metal layer 254 are sequentially removed by etching, leaving only the metal layer 254. The bottom metal layer 252 is as shown in FIG. Thereafter, a single-cut step can be performed in which the dicing blade cuts the semiconductor wafer 2 along the scribe-line of the semiconductor wafer 200, thereby forming a plurality of individual wafer structures 205. Referring to FIG. 52, since the lateral dimension of the bump layer 296 of the bump 291 is smaller than the lateral dimension of the metal pillar 292, the solder layer of the bump 291 is even if the opening of the solder mask layer of the substrate is small. 296 can also be easily inserted into the opening of the solder mask layer of the substrate and connected to the contacts exposed by the openings of the solder mask layer of the substrate. In addition, when the metal pillar 292 is formed by the second method, the step of removing the bottom metal layer 293 of the pole by 26 1284385 15625 twf.doc/006 can also be omitted as shown in FIG. 47. The narrative will not be repeated here. 9. Configuration of Polymer Layer In the foregoing first embodiment, the metal lines are formed in direct contact with the protective layer. However, the application of the present invention is not limited thereto, and a polymer layer may be formed in the metal line and the semiconductor. Between the protective layers of the wafer, as shown in FIG. 53, a schematic cross-sectional view of a wafer structure having gold lip lines, bumps, and polymer layers on the protective layer in accordance with the first embodiment of the present invention is shown. Referring to Figure 53, after the semiconductor wafer 200 is provided, a polymer layer 245 can be formed over the protective layer 240 of the semiconductor wafer 200. The polymer layer 245 has a plurality of openings 246 exposing the top film layer 236, metal. The line 250 and the pad 251 can be connected to the top film line layer 246 through the opening 246 of the polymer layer 245 and the opening 242 of the protective layer 240. The thickness k of the polymer layer 245 is, for example, greater than 1 micron' and the material of the polymer layer 245 is, for example, polyimide 'PI, benzoCyCi〇 butene (ACB), polyarylene _ (parylene), porous dielectric material or elastomer. 10. The function of the metal line A. The metal line is used as the bump position relocation of the wafer structure. Referring to FIG. 21, FIG. 39, FIG. 46, FIG. 47, FIG. 52 and FIG. 53, the metal line 250 can be reconfigured. The layout positions of the bumps 28〇, 290, and 291, the metal lines 250 are connected to the bumps 280, 290, and 291 and the contact points of the thin film wiring layer 246, wherein the bumps 280, 290, and 291 are electrically connected to the contacts. The layout position is different from the layout position of this contact. Thus, the metal line 25 can be used as a reconfiguration layout, that is, the position of the bump 28 can be adjusted by the metal line 25 () or the electrical order of the bump 2 (6) can be adjusted (9). Electrically, the electronic component 12 located on the surface of the semiconductor substrate 210 can output an electronic signal via the thin film wiring layers 232, 234, 236, 27 1284385 15625 twf. doc / 006 metal wiring 242 and bumps 280, 290 291 can be transmitted to an external circuit, such as a substrate or another semiconductor wafer; or an external circuit such as a substrate or another semiconductor wafer can be via bumps 280, 290, 291, metal lines 242, and thin film wiring layers 236, 234 The 232 transmits the signal to the electronic component 212 of the surface layer of the semiconductor substrate 210. B. Jinzhan circuit is used as internal signal transmission for wafer structure. Circle 54 and Fig. 55 are schematic cross-sectional views showing the structure of the wafer in accordance with the first embodiment of the present invention. Referring to FIG. 54 and FIG. 55, the metal line 242 is used for signal transmission inside the wafer structure 205, that is, one of the electronic components 212 (such as the electronic component 212a) is adapted to output an electronic signal, and the electronic signal is transmitted through the film. The circuit layers 232, 234, 236 pass through the protective layer 240, are transferred to the metal line 250, then pass through the protective layer 24, and are transferred to at least the other electronic components 212 via the thin film wiring layers 236, 234, 232. One (for example
電子元件212b)。同時，透過位在金屬線路25〇上的凸塊28C 亦可以將由電子元件212a所輸出的電子訊號傳送至外界電路 構件(未纷示） 值得注意的是，金屬線路250可以是直接接觸地形成在 保遵層240上，如目54所示；或者，亦可以先形成聚合物層 245在保遵層240上，接著再形成金屬線路25〇在聚合物層245 土、，如圖55所示。另外，就凸塊的形式而言，亦可以是類似 刖述之柱狀凸塊的樣式，在此便不再贅述。 C·金屬線路係作為晶片結構之電源匯流排或接地匯流排 之用 & - Γ』6巧57緣示依照本發明第—實施例之晶片結構的剖 線路25G可以與薄膜線路層之薄膜電源匯 電’連接’作為晶片結構2〇5之電源匯流排；同時， 透過凸塊28G還可轉—外界電_件(未㈣)之電源匯流 1284385 15625twf.doc/006 排電性連接’其中外界電路構件比如是基板或是另娜導體 晶片。或者，金屬線路250亦可以與薄膜線路層之薄膜接地 匯流排235電性連接，作為晶片結構2〇5 <接地匯流排;同 時，透過凸塊280還可以與一外界電路構件(未繪示)之接地 匯流排電性連接，其中外界電路構件比如是基板或是另一半 導體晶片。 值得注意的是，金屬線路250可以是直接接觸地形成在 保護層240上，如圖56所示；或者，亦可以先形成聚合物層 245在保護層240上，接著再形成金屬線路250在聚合物層245 上，如圖57所示。另外，就凸塊的形式而言，亦可以是類似 則述之柱狀凸塊的樣式’在此便不再贅述。 D·金屬線路係作為外界電路構件之訊號傳輸、電源匯流 排或接地匯流排之用 圖58及圖59繪示依照本發明第一實施例之晶片結構的剖 面示意圖，其中金屬線路250並未連接頂層的薄膜線路層236。 當金屬線路250係作為外界電路構件(未繪示)之訊號傳輸之用 時，外界電路構件可以輸出一電子訊號，經由凸塊280a傳輸 至金屬線路250，之後再經由凸塊280b傳輸至外界電路構件。 此外，金屬線路250亦可以作為外界電路冓件之電源匯流排 或接地匯流排。 值得注意的是，金屬線路250可以是直接接觸地形成在 保護層240上，如圖58所示；或者，亦可以先形成聚合物層 245在保護層240上，接著再形成金屬線路250在聚合物層245 上，如圖59所示。另外，就凸塊的形式而言，亦可以是類似 前述之柱狀凸塊的樣式，在此便不再贅述。 二^、晶片結構Μ作方法的第二實施例 圖60至圖66繪示依照本發明第二實施例中在半導體晶圓上 29 1284385 15625twf.doc/006 製作金屬線路及凸塊的剖面示意圖。請參照圖60，首先提供一半 導體晶圓200,半導體晶圓200包括一半導體基底210、多數 層薄膜介電層222、224、226、多數層薄膜線路層232 V234、 236及一保護層240，其詳細結構在第一實施例的第^點中有 詳盡的敘述，在此便不再贅述。 請參照圖60，在提供半導體晶圓200之後，可以利用濺鍍 的方式形成底部金屬層250在半導體晶圓之保護層240上及暴露 於保護層240之開口 242外的薄膜線路層236之接點236a、 236b上，在此過程中，比如包括先濺鍍黏著/阻障層在半導體 晶圓200之保護層240上及暴露於保護層240之開口 242外的 薄膜線路層236上，接著再濺錄種子層在黏著/阻障層上，黏 著/阻障層及種子層的材質係敘述如後，在此便不再贅述。 接著，可以形成光阻層260在底部金屬層252上，光阻層260 具有開口 262，暴露出底部金屬層252，如圖60所示。接著， 可以利用電鍍的方式，形成金屬層254在光阻層26〇之開口 262 所暴露出的底部金屬層252上，如圖61所示，其中金屬層254 比如係為線路圖案的樣式，金屬層254係電性連接薄膜線路層 236之接點236a，且在保護層240上延伸。定義一平面川〇〇， 平面1〇〇〇係大致上平行於半導體基底210之主動表面214 , 其中線路圖案之金屬層254投影至平面1000上的延伸距離比 如係大於5GG微米，或者比如係大於_微米，或者比如係 大於1200微米；金屬層254之線路圖案254a投影至平面1〇00 上的面積比如係大於30，_平方微米，或者比如係大於8〇，_ 平方微米，或者比如係大於15〇,〇〇〇平方微米。 接著，可以將光阻層260去除，暴露出底部金屬層252 ,如 圖62所示。之後，可以再形成光阻層27〇在底部金屬層说上 及金屬層254上’光阻層270具有開口 272，暴露出位在薄膜線 30 1284385 15625twf.doc/006 路層236之接點236b上的底部金屬層252，如圖63所示。 接著，可以利用電鍍的方式形成凸塊圖案之金屬層282在 光阻層270之開口 272所暴露出之底部金屬層252上 ，如圖64 所示。值得注意的是，每一凸塊圖案之金屬層282投影至平 面1000上的面積比如係小於30,000平方微米，或者比如係 小於20,000平方微米，或者比如係小於15,000平方辨米。 接著，可以去除光阻層270，暴露出底部金屬層252，如 圓65所示。接著，再以線路圖案之金屬層254及凸塊圖案之 金屬層282作為餘刻罩壁’透過钮刻的方式依序去除未被全 屬層254、282覆蓋之底部金屬層252的種子層及黏著/阻障 層，僅留下位在金屬層254、282下的底部金屬層252，如圖 66所示。當凸塊圖案之金屬層282包括焊料層時，接下来還 可以進行迴焊的步驟，使得金屬層282的頂面可以形成圓滑 的表面(未纟會示）。 之後，可以進行單切的步驟，此時切割刀會沿著半導體 晶圓200之切割道(scribe-line)來切割半導體晶圓200 ,藉以 形成多個獨立的晶片結構205。 在上述的製程中，金屬線路250係由濺鍍製程所形成的 底部金屬層252及電鍍製程所形成之金屬層254所構成，凸 塊280係由濺鍍製程所形成的底部金屬層252及電鍍製程所 形成之金屬層282所構成。由於金屬線路250及凸塊280之 底部金屬層252係由同一道濺鍍步驟所形成，故可以簡化形 成金屬線路250及凸塊280的步驟。 2.金屬線路之結構 請參照圖66，金屬線路250係由濺鍍製程所形成的底部 金屬層252及電鍍製程所形成的金屬層254所構成，詳細結 構係如下所述。 31 1284385 15625twf.doc/006 Α·金羼線路之第一種金屬層結構 請參照圏67，其_健本_第二實補之金屬線路 之第-種金屬層結構的剖面示㈣，其中在形絲部金屬廣 252時，比如係先利用濺鍍製程形成黏著/阻障層252a，接著 再利用濺鍍的方式形成材質為金或銅的種子層252b於黏著/ 阻障層252a上，其中黏著/阻障層252a之材質比如係為絡、 鈦、鈦鎢合金、鈦氮化合物、鈕或组氮化合物等，或者黏著/ 阻障層252a亦可以是藉由依序沉積鉻層及路銅合金層而成， 其中鉻銅合金層係位在鉻層上。在形成金屬層254時，比如 係利用電賴方式軸厚度X大於丨微米的金層在底部金屬 層252之種子層252b上。 B·金屬線路之第二種金屬層結構 清參照圖68，其繪示依照本發明第二實施例之金屬線路 之第二種金屬層結構的剖面示意圖，其中在形成底部金屬層 252時，比如係先利用濺鍍製程形成黏著/阻障層252a，接著 再利用減:鍵的方式形成材質為銅或金之種子層252b於黏著/ 阻障層252a上，其中黏著/阻障層252a之材質比如係為鉻、 鈦、鈦鎢合金、鈦氮化合物、钽或鈕氮化合物等，或者黏著/ 阻障層252a亦可以是藉由依序沉積鉻層及鉻銅合金層而成， 其中鉻銅合金層係位在鉻層上。在形成金屬層254時，比如 係利用電鍍的方式形成厚度大於丨微米的銅層在底部金屬層 252之種子層252b上。 C·金屬線路之第三種金屬層結構 ，參照圓69，其繪示依照本發明第二實施例之金屬線路 之第三種金屬層結構的剖面示意圖，其中在形成底部金屬層 252時’比如係先利用濺鍵製程形成黏著/阻障層252a,接著 再利用賤鍵的方式形成材質為銅或金的種子層252b於黏著/ 32 1284385 15625twf.doc/006 阻障層252a上’其中黏著/阻障層252a之材質比如係為鉻、 鈦、鈥鎢合金、鈦氮化合物、组或鈕氮化合物等，或者黏著/ 阻障層252a亦可以是藉由依序沉積鉻層及鉻銅合金層而成， 其中鉻銅合金層係位在鉻層上。在形成金屬層254時，比如 是先利用電鍍的方式形成厚度大於1微米的銅層254知在底 部金屬層252之種子層2522b上，接著再利用電鍍的方式形 成錄層2543b在銅層2543a上。 D·金屬線路之第四種金屬層結構 請參照圖70,其繪示依照本發明第二實施例之金屬線路 之第四種金屬層結構的剖面示意圖，其中在形成底部金屬層 252時，比如係先利用濺鍍製程形成黏著/阻障層252a，接著 再利用濺鍍的方式形成材質為銅或金的種子層252b於黏著/ 阻障層252a上，其中黏著/阻障層252a之材質比如係為鉻、 鈦、鈦鎮合金、鈦氮化合物、组或钽氮化合物等，或者黏著/ 阻障層252a亦可以是藉由依序沉積鉻層及鉻銅合金層而成， 其中鉻銅合金層係位在鉻層上。在形成金展層254時，比如 是先利用電鍍的方式形成厚度大於1微米的銅層2544a在底 部金屬層252之種子層2522b上，接著再利用電鍍的方式形 成錄層2544b在銅層2544a上，之後再利用電鍍的方式形成 金層2544c在鎳層2544b上。 3·凸塊之結構 請參照圖66，凸塊280係由濺鍍製程所形成的底部金屬 層252及電鍍製程所形成的金屬層282所構成，詳細結構係 如下所述。 Α·第一種凸塊結構 v月參照圖71 ’其繪不依照本發明第二實施例之第一種凸 塊結構的剖面示意圖，其中在形成底部金屬層252時，比如 33 1284385 l5625twf.doc/006 係先利用濺鍍製程形成黏著/阻障層252a，接著再利用滅鑛的 方式形成材質係為金或銅的種子層252b於黏著/阻障層252a 上’其中黏者/阻障層252a之材質比如係為絡、鍊、欽鶴合 金、鈦氮化合物、组或钽氮化合物等，或者黏著/阻陳層252a 亦可以是藉由依序沉積鉻層及鉻銅合金層而成，其中鉻鋼合 金層係位在鉻層上。在形成凸塊圖案之金屬層282時，比如 係利用電鍵的方式形成厚度y大於3微米的金層在底部金屬 層252之種子層252b上。在實際應用上，如圖η所示之凸 塊280可以搭配具有如圖67至圖70所示之金屬層鈐槿的令 屬線路250形成在半導體晶圓200上。 B·第二種凸塊結構 請參照圖72,其繪示依照本發明第二實施例之第二種凸 塊結構的剖面示意圖，其中在形成底部金屬層252時，比如 係先利用滅鍵製程形成黏著/阻障層252a，接著再利用濺錄的 方式形成材質為銅或金的種子層252b於黏著/阻障層252a 上’其中黏著/阻障層252a之材質比如係為鉻、鈦、鈦鎢合 金、鈦氮化合物、钽或鈕氮化合物等，或者黏著/阻障層252a 亦可以是藉由依序沉積鉻層及鉻銅合金層而成，其中鉻鋼合 金層係位在鉻層上。在形成凸塊圖案之金屬層282時，比如 是先利用電鍍的方式形成銅層2822a在底部金屬層252之種 子層252b上，接著再利用電鍍的方式形成鎳層282处在鋼層 2822a上，接著再利用電鍍的方式形成厚度y大於3微米的 焊料層2822c在鎳層2822b上，其中焊料層2822c的材質比 如是錫鉛合金、錫、錫銀合金或錫銀銅合金等。在實際應用 上，如圖72所示之凸塊280可以搭配具有如圖67至圖7〇所 示之金屬層結構的金屬線路250形成在半導體晶圓2〇〇上。 4·製作金屬線路及第一種形式之柱狀凸塊的方法 34 1284385 15625twf.doc/006 此外，本發明的製程亦可以結合製作柱狀凸塊的製程， 如圖73至圖77所示，其繪示依照本發明第二實施例中在半導 艘晶圓上製作金屬線路及第一種形式之柱狀凸堍的剖面示意圖， 其中圖至圖73係接續圖62的步驟。 在線路圖案之金屬層254製作完成之後’如圖62所示， 還可以形成光阻層270在底部金屬層252上及金屬廣254上， 光阻層270具有開口 272,暴露出位在薄膜線路層236之接點236b 上的底部金屬層252，如圖73所示，其中底部金屬層252的 結構比如係雷同圖67至圖72所示之包括黏著/阻障層252a 及種子層252b之底部金屬層252的結構，在此便不再贅述。 請繼續參照圖73，接著可以利用電鍍的方式依序形成金屬 柱292及焊料層296在光阻層270之開口 272所暴露出之底 部金屬層252上，其中在形成金屬柱292時，比如係利甩電 鍍製程依序形成柱狀金屬層294及防崩落層295。當在形成 柱狀金屬層294時，比如是利用電鍍的方式形成厚度介於8 微米至100微米的銅層在底部金屬層252上，或者比如是利 用電鍍的方式形成厚度介於8微米至1〇〇微米之含船量高的 錫船合金層在底部金屬層252上；當在形成防崩落層295時， 比如是利用電鍍的方式形成厚度介於1微米至1〇微米的鎳層 在柱狀金屬層294上。在本實施例中，焊料層296的材質比 如係為錫鉛合金、錫、錫銀合金或錫銀銅合金等，焊料層296 可以直接接觸地形成在金屬柱292之錄層295上，且位在光 阻層270之開口 272中。 接著，可以去除光阻層270 ,暴露出底部金屬層252 ,如 圖74所示。接著，可以從柱狀金屬層294的侧壁蝕刻柱狀金 屬層294，使得柱狀金屬層294投影至平面1000上的面積可 以小於防崩落層295或焊料層296投影至平面i〇〇Q上的面 35 1284385 15625twf.doc/006 積，且防崩落層295之下表面的邊緣可以暴露於外，如圖75 所示。接著，再以金屬層254及柱狀金屬層294作為蝕刻罩 壁，透過蝕刻的方式依序去除未被金屬層254及枉狀金屬層 294覆蓋之底部金屬層252的種子層及黏著/阻障層，僅留下 位在金屬層254下及柱狀金屬層294下的底部金屬層252， 如圖76所示。接下來，還可以進行迴焊的步驟，使得焊料層 296的頂面可以形成圓滑的表面，如圖77所示，至此便完成 製作凸塊290的製程。如上所述，凸塊290可以包括金屬柱 292及焊料層296，在本實施例中，金屬柱292比如是由底部 金屬層252、柱狀金屬層294及防崩落層295所構成。 請參照圖77，在本實施例中，由於金屬柱292之柱狀金 屬層294的橫向尺寸係小於防崩落層295的橫向尺寸，因此 當在進行迴焊製程時，由焊料層296所熔化的焊料並不會沿 著柱狀金屬層294的側壁流下，故可以避免發生焊料層296 崩落的情形。 之後’可以進行單切的步驟，此時切割刀會沿著半導體 晶圓200之切割道(scribe-iine)來切割半導體晶圓2〇〇 ,藉以 形成多個獨立的晶片結構205。 在上述的製程中，金屬線路250係由濺鍍製程所形成的 底部金屬層252及電鍍製程所形成之金屬層254所構成，柱 狀凸塊290係由濺鍍製程所形成的底部金屬層252及電鍍製 程所形成之柱狀金屬層282、防崩落層294及焊料層296所 構成。由於金屬線路250及柱狀凸塊290之底部金屬層252 係由同一道減鍍步驟所形成，故可以簡化形成金屬線路25〇 及柱狀凸塊290的步驟。 5·製作金屬線路及第二種形式之柱狀凸塊的方法 圖78至圖82繪示依照本發明第二實施例中在半導體晶圓 36 1284385 15625twf.doc/006 上製作金屬線路及第二種形式之柱狀凸塊的剖面示意圖，其中圖 78至圖82係接續圖62的步驟。 在線路圖案之金屬層254製作完成之後，如阖62所示， 還可以形成光阻層270在底部金屬層252上及金屬層254上， 光阻層270具有開口 272,暴露出位在薄膜線路層236之接點236V 上的底部金屬層252 ’如圖78所不’其中底部金屬層252的 結構比如係雷同圖67至圖72所示之包括黏著/阻障展252a 及種子層252b之底部金屬層252的結構，在此便不再贅述。 請繼續參照圖78，接著可以利用電鍍的方式形成金屬柱292 在光阻層270之開口 272所暴露出之底部金屠層252上，其鲁 中在形成金屬柱292時，比如係利用電鍍的方式依序形成柱狀 金屬層294及防崩落層295在光阻層270之開口 272所暴露 出之底部金屬層252上；當在形成柱狀金屬層294時，比如是 利用電鍍的方式形成厚度介於8微米至1〇〇微米的銅層在底 部金屬層252上，或者比如是利用電鍍的方式形成厚度介於 8微米至100微米之含鉛量高的錫鉛合金層在底部金屬層252 上，當在形成防崩落層295時，比如是利用電鍍的方式形成 厚度介於1微米至10微米的鎳層在柱狀金屬層294上。 接著，形成光阻層275在光阻層270上及防崩落層295籲· 上:如圖79所不，其中光阻層2乃具有開口 276，暴露出防 崩落層295，值得注意的是，光阻層275之開口 276的橫向 尺寸係小於柱狀金屬層294及防崩落層295的橫向尺寸。接 著，可以形成焊料層296在光阻層275之開口 276所暴露出 之防崩落層295上，如圖8〇所示，其中焊料層2%的材質比 如係為錫^合金、踢、錫銀合金祕銀銅合金等。 接著，可以依序去除光阻層275、270，暴露出底部金屬 層252 ’如圖81所不。接著，再以金屬層254及柱狀金屬層 37 1284385 15625twf.doc/006 294作為蝕刻罩壁，透過蝕刻的方式依序去除未被金屬層254 及柱狀金屬層294覆蓋之底部金屬層252之種子層及黏著/阻 障層，僅留下位在金屬層254下及柱狀金屬層294下的底部 金屬層252,如圖82所示，至此便完成製作凸塊291的製程。 如上所述，柱狀凸塊291可以包括金屬柱292及焊料層296 , 在本實施例中，金屬柱292比如是由底部金屬層252、柱狀 金屬層294及防崩落層295所構成。 之後，可以進行單切的步驟，此時切割刀會沿著半導體 晶圓200之切割道(scribe-line)來切割半導體晶圓200，藉以 形成多個獨立的晶片結構205。 請參照圖82,當在進行接合晶片結構205及一基板(未 繪示）時，由於柱狀凸塊291之焊料層296的橫向尺寸係小於 金屬柱292的橫向尺寸，因此即使在基板之焊罩層的開口係 為甚小的情況下，柱狀凸塊291之焊料層296亦可以輕易地 插入到基板之焊罩層的開口中，並與基板之焊罩層的開口所 暴露出的接點連接。 在上述的製程中，金屬線路250係由濺鍍製程所形成的 底部金屬層252及電鍍製程所形成之金屬層254所構成，柱 狀凸塊291係由濺鍍製程所形成的底部金屬層252及電鍍製 程所形成之柱狀金屬層282、防崩落層294及焊料層296所 構成。由於金屬線路250及柱狀凸塊291之底部金屬層252 係由同一道濺鍍步驟所形成，故可以簡化形成金屬線路250 及柱狀凸塊291的步驟。 6·凸塊、金屬線路與聚合物層之間的厚度關係 在第二實施例中，如圖66、圖77及圖82所示，金屬線 路250係暴露在外且直接接觸地形成在保護層240上，金屬 線路250可以連接暴露在保護層240之開口 242外的薄膜線 38 1284385 15625twf.doc/006 路層236之接點。凸塊280係直接接觸地形成在保護層240 之開口 242所暴露出之薄膜線路層236的接點上。值得注意 的是，凸塊280、290、291的厚度bl、b2、b3係大於金屬線 路250的厚度c。然而，本發明的應用並不限於弗，請參照 圖83，凸塊280的厚度b4亦可以是等於金屬線路250的厚 度c ;以此類推，當前述之柱狀凸塊290、291取代凸塊280 時，柱狀凸塊290、291的厚度亦可以是等於金屬線路250的 厚度c 〇 在圖84及圖85中，金屬線路250係直接接觸地形成在 保護層240上，一聚合物層245係形成在金屬線路250上及 保護層240上，藉以保護金屬線路250。凸塊280係直接接 觸地形成在保護層240之開口 242所暴露出之薄膜線路層236 的接點上。值得注意的是，在圖84中，凸塊280的厚度b5 係大於金屬線路250與聚合物層245所加總的厚度(c+d)，以 此類推，當前述之柱狀凸塊290、291取代凸塊280時，柱狀 凸塊290、291的厚度亦可以是大於金屬線路250與聚合物層 245所加總的厚度。在圖85中，凸塊280的厚度b6係小於 金屬線路250與聚合物層245所加總的厚度(c+d)，以此類推， 當前述之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、 291的厚度亦可以是小於金屬線路250與聚合物層245所加 總的厚度。 在圖86、圖87及圖88中，聚合物層247係位於保護層 240上，聚合物層247具有多個開口 248，大致上係對準保護 層240之開口 242，並暴露出頂層之薄膜線路層236的接點。 金屬線路250係形成在聚合物層247上，並且經由聚合物層 247之開口 248及保護層240之開口 242連接至薄膜線路層236 的接點。凸塊280係直接接觸地形成在保護層240之開口 242 39 1284385 15625twf.doc/006 所暴露出之薄膜線路層236的接點上。值得注意的是，在圖 86中，凸塊280的厚度b7係大於金屬線路250與聚合物層247 所加總的厚度(c+e)，以此類推，當前述之柱狀凸塊290、291 取代凸塊280時，柱狀凸塊290、291的厚度亦可以是大於金 屬線路250與聚合物層247所加總的厚度。在圖87中，凸塊 280的厚度b8係大致上相同於金屬線路250與聚合物層247 所加總的厚度(c+e)，以此類推，當前述丈柱狀凸塊290、291 取代凸塊280時，柱狀凸塊290、291的厚度亦可以是等於金 屬線路250與聚合物層247所加總的厚度。在圖88中，凸塊 280的厚度b9係大於金屬線路250與聚合物層247所加總的 厚度(c+e)，以此類推，當前述之柱狀凸塊290、291取代凸 塊280時，柱狀凸塊290、291的厚度亦可以是大於金蜃線路 250與聚合物層247所加總的厚度。 在圖89及圖90中，聚合物層247係位於保護層240上， 聚合物層247具有多個開口 248 ,大致上係對準保護層240 之開口 242，並暴露出頂層之薄膜線路層236的接點。金屬 線路250係形成在聚合物層247上，並且經由聚合物層247 之開口 248及保護層240之開口 242連接至薄膜線路層236 的接點。聚合物層245係位於金屬線路250上及聚合物屠247 上，用以保護金屬線路250。凸塊280係直接接觸地形成在 保護層240之開口 242所暴露出之薄膜線路層236的接點上。 值得注意的是，在圖89中，凸塊280的厚度M0係小於金屬 線路250與聚合物層245、247所加總的厚度(c+d+e)，以此 類推，當前述之柱狀凸塊290、291取代凸塊280時，柱狀凸 塊290、291的厚度亦可以是小於金屬線路250與聚合物層 245、247所加總的厚度；在圖90中，凸塊280的厚度bll 係大於金屬線路250與聚合物層245、247所加總的厚度 1284385 15625twf.doc/006 (c+d+e) ’以此類推，當前述之柱狀凸塊290、291取代凸塊280 時，柱狀凸塊290、291的厚度亦可以是小於金屬線路25〇與 聚合物層245、247所加總的厚度。 、 在圖91及圖92中，聚合物層247係位於保護層240上， 聚合物層247具有多個開口 248，大致上對準保護層24〇之 開口 242，並暴露出頂層之薄膜線路層236的接點。金屬線 路250係形成在聚合物層247上，並且經由聚合物層247之 開口 248及保護層240之開口 242連揍至薄膜線路層236的 接點。凸塊280係直接接觸地形成在保護層240之開口 242 及聚合物層247之開口 248所暴露出之薄膜線路層236的接 點上。值得注意的是，在圖91中，凸塊280凸出於外的厚度 M2係相同於金屬線路250的厚度c，以此類推，當前述之柱 狀凸塊290、291取代凸塊280時，柱狀凸塊290、291凸出 於外的厚度亦可以是相同於金屬線路250與聚合物層245、247 所加總的厚度；在圖92中，凸塊280凸出於外的厚度bl3係 大於金屬線路250的厚度c，以此類推，當前述之柱狀凸塊 290、291取代凸塊280時，柱狀凸塊290、291凸出於外的 厚度亦可以是大於金屬線路250與聚合物層245、247所加總 的厚度。 在圖93及圖94中，聚合物層247係位於保護層240上， 聚合物層247具有多個開口 248,大致上係對準保護層240 之開口 242，並暴露出頂層之薄膜線路層236的接點。金屬 線路250係形成在聚合物層247上，且可以經由聚合物層247 之開口 248及保護層240之開口 242連接至薄膜線路層236 的接點。聚合物層245係位於金屬線路250上及聚合物層247 上，用以保護金屬線路250。凸塊280係直接接觸地形成在 保護層240之開口 242及聚合物層247之開口 248所暴露出 1284385 15625twf.doc/006 之薄膜線路層236的接點上。值得注意的是，在圖93中，凸 塊280凸出於外的厚度M4係小於金屬線路250與聚合物層 245所加總的厚度(c+d)，以此類推，當前述之柱狀凸棟290、 291取代凸塊280時，柱狀凸塊290、291凸出於外的厚度亦 可以是相同於金屬線路25〇與聚合物層245所加總的厚度; 在圖94中，凸塊280凸出於外的厚度M5係大於金屬線路250 與聚合物層245所加總的厚度(c+d)，以此類推，當前述之柱 狀凸塊290、291取代凸塊280時，柱狀凸塊290、201凸出 於外的厚度亦可以是大於金屬線路250與聚合物層245所加 總的厚度。 在上述圖84至圖94的實施例中，聚合物層245、247的 材質比如是聚醯亞胺（polyimide，pi)、苯基環丁稀 (benzocydobutene，BCB)、聚亞芳香基醚(parylene)、多孔性 介電材質或彈性體等，且聚合物層245、247的厚度d、e比 如係大於1微米。 7·金屬線路的功能 A·金屬線路係作為晶片結構之内部訊號傳輸之用 請參照圖66、圖77、圖82及圖83至圖94,金屬線路250 係作為晶片結構205之内部訊號傳輸之用，亦即電子元件212 之其中一個（比如是電子元件212a)係適在輸出一電子訊號， 此電子訊號經由薄膜線路層232、234、236並穿過保護層240 後，傳輸至金屬線路250，接著再穿過保護層24〇 ,並經由薄 膜線路層236、234、232傳輸至其他的電子元件 212之至少 其中一個（比如是電子元件212b)。 B·金屬線路係作為晶片結構之電源匯流排或接地匯流排 之用 圖95至圖107繪示依照本發明第二實施例之晶片結構的 42 1284385 15625tw£doc/006 剖面示意圖，其中金屬線路250可以與薄膜線路層之薄膜電源 匯流排235電性連接，作為晶片結構2〇5之電源匯流^，可' 以電性連揍至電源電壓源：或者，金屬線路25〇亦可以與薄 膜線路層之薄膜接地匯流排235電性連接，作為晶片結構2〇5 之接地匯流排，可以電性連接至接地電壓源。 、請參照圖95 ,金羼線路250係暴露在外且直接接觸地形 成在保遵層240上，金孱線路250可以連接暴露在保護層“ο 之開口 242外的薄膜線路層236之接點。凸塊28〇係直接接 觸地形成在保護層240之開口 242所暴露出之薄膜線路層236 的接點上。值得注意的是，凸塊280的厚度bl6係大於金展籲 線路250的厚度c ;以此類推，當前述之柱狀凸塊29〇、291 取代凸塊280時，柱狀凸塊290、291的厚度亦可以是等於金 屬線路250的厚度c。然而，本發明的應用並不限於此，請 參照圖96，凸塊280的厚度bl7亦可以是等於金屬線路250 的厚度c ;以此類推，當前述之柱狀凸塊29〇、291取代凸塊 280時’柱狀凸塊290、291的厚度亦可以是等於金屬線路250 的厚度e 〇 在圖97及圖98中，金屬線路250係直接接觸地形成在 保護層240上，一聚合物層245係形成在金屬線路250上及修 保護層240上，藉以保護金屬線路250。凸塊280係直接接 觸地形成在保護層240之開口 242所暴露出之薄膜線路層236 的接點上。值得注意的是，在圖97中，凸塊280的厚度bl8 係大於金屬線路250與聚合物層245所加總的厚度(c+d)，以 此類推，當前述之柱狀凸塊290、291取代凸塊280時，柱狀 凸塊290、291的厚度亦可以是大於金屬線路250與聚合物層 245所加總的厚度。在圖98中，凸塊280的厚度M9係小於 金屬線路250與聚合物層245所加總的厚度(c+d)，以此類推， 43 1284385 15625twf.doc/006 當前述之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、 291的厚度亦可以是小於金屬線路25〇與聚合物層245所加 總的厚度。 在圖99、圖100及圖101中，聚合物層247係位於保護 層240上，聚合物層247具有多個開口 248，大致上係對準 保護層240之開口 242，並暴露出頂層之薄膜線路詹236的 接點。金屬線路250係形成在聚合物層247上，並且經由聚 合物層247之開口 248及保護層240之開口 242連接至薄膜 線路層236的接點。凸塊280係直接接觸地形成在保護層240 之開口 242所暴露出之薄膜線路層236的接點上。值得注意 的是，在圖99中，凸塊280的厚度b20係大於金屬線路250 與聚合物層247所加總的厚度(c+e)，以此類推，當前述之柱 狀凸塊290、291取代凸塊280時，柱狀凸塊290、291的厚 度亦可以是大於金屬線路250與聚合物層247所加總的厚度。 在圖100中，凸塊280的厚度b21係大致上相同於金屬線路 250與聚合物層247所加總的厚度(c+e)，以此類推，當前述 之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、291 的厚度亦可以是等於金屬線路250與聚合物層247所加總的 厚度。在圖101中，凸塊280的厚度b22係大於金屬線路25〇 與聚合物層247所加總的厚度(c+e)，以此類推，當前述之柱 狀凸塊290、291取代凸塊280時，柱狀凸塊290、291的厚 度亦可以是大於金屬線路250與聚合物層247所加總的厚度。 在圖102及圖103中，聚合物層247係位於保護層240 上，聚合物層247具有多個開口 248,大致上係對準保護層24〇 之開口 242，並暴露出頂層之薄膜線路層236的接點。金屬 線路250係形成在聚合物層247上，並且經由聚合物層247 之開口 248及保護層240之開口 242連接至薄膜線路層236 1284385 15625twf.doc/006 的接點。聚合物層245係位於金屬線路250上及聚合物層247 上，用以保護金屬線路250。凸塊280係直接接觸地形成在 保護層240之開口 242所暴露出之薄膜線路層236的接點上。 . · · 值得注意的是，在圖102中，凸塊280的厚度b23係小於金 屬線路250與聚合物層245、247所加總的厚度(c+d+e)，以 此類推，當前述之柱狀凸塊290、291取代凸塊280時，柱狀 凸塊290、291的厚度亦可以是小於金屬線路250與聚合物層 245、247所加總的厚度；在圖1〇3中，凸塊280的厚度b24 係大於金屬線路250與聚合物層245、247所加總的厚度 (c+d+e)，以此類推，當前述之柱狀凸塊290、291取代凸塊280 時，柱狀凸塊290、291的厚度亦可以是小於金屬線路250與 聚合物層245、247所加總的厚度。 在圖104及圖105中，聚合物層247係位於保護層240 上，聚合物層247具有多個開口 248，大致上對準保護層240 之開口 242,並暴露出頂層之薄膜線路層236的接點。金屬 線路250係形成在聚合物層247上，並且經由聚合物層247 之開口 248及保護層240之開口 242連接至薄膜線路層236 的揍點。凸塊280係直接接觸地形成在保護層240之開口 242 及聚合物層247之開口 248所暴露出之薄膜線路層236的接 點上。值得注意的是，在圖104中，凸塊280凸出於外的厚 度b25係相同於金屬線路250的厚度c，以此類推，當前述 之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、291 凸出於外的厚度亦可以是相同於金屬線路250與聚合物層 245、247所加總的厚度；在圖105中，凸塊280凸出於外的 厚度b26係大於金屬線路250的厚度c，以此類推，當前述 之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、291 凸出於外的厚度亦可以是大於金屬線路250與聚合物層245、 45 1284385 15625twf.doc/006 247所加總的厚度。 在圖106及圖107中，聚合物層247係位於保護廣240 上’聚合物層247具有多個開口 248,大致上係對準保護層240 之開口 242 ’並暴露出頂層之薄族線路層236的接點。金屬 線路250係形成在聚合物層247上，且可以經由聚合物層247 之開口 248及保護層240之開口 242連接至薄膜線路層236 的接點。聚合物層245係位於金屬線路250上及聚合物層247 上，用以保護金屬線路250。凸塊280係直接接觸地形成在 保護層240之開口 242及聚合物層247之開口 248所暴露出 之薄膜線路層236的接點上。值得注意的是，在圖1〇6中， 凸塊280凸出於外的厚度b27係小於金屬線路250與聚合物 層245所加總的厚度(c+d)，以此類推，當前述之柱狀凸塊29〇、 291取代凸塊280時，柱狀凸塊290、291凸出於外的厚度亦 可以是相同於金屬線路250與聚合物層245所加總的厚度； 在圖107中，凸塊280凸出於外的厚度b28係大於金屬線路 250與聚合物層245所加總的厚度(c+d)，以此類推，當前述 之柱狀凸塊290、291取代凸塊280時，柱狀凸塊29〇、291 凸出於外的厚度亦可以是大於金屬線路250與聚合物層245 所加總的厚度。 在上述圖95至圖107的實施例中，聚合物層245、247 的材質比如是聚醯亞胺（polyimide，PI)、苯基環丁烯 (benzocyclobutene，BCB)、聚亞芳香基醚(parylene)、多孔性 介電材質或彈性邀等，且聚合物層245、247的厚度d、e比 如係大於1微米。 C·金屬線路係作為訊號傳輸線路、電源匯流排或接地匯流 排之用，其中金屬線路係利用頂層之薄膜線路層電性連接凸塊 請參照圖108至圖121，其繪示依照本發明第二實施例之晶 46 1284385 15625twf.doc/006 片結構的剖面示意圖，其中金屬線路250係利用頂層之薄膜線路 層236連接凸塊280,金屬線路層250比如係作為訊號傳輸線路、 電源匯流排或揍地匯流排之用。金屬線路250係位於锯護層 240上，且經由保護層240之開口 242電性連接於薄膜線路 層236之接點237a。凸塊280係位在保護層240之開口 242 所暴露出的薄膜線路層236之接點237b上。薄膜線路層236 具有一連接線路237，連接接點237a、237b，使得金屬線路 250可以透過連接線路237及接點237a、237b電性連接凸塊 280。請參照圖109，其繪示連接線路237及接點237a、237b 的上視示意圖，在較佺的情況下，連接線路237的延伸距離s 比如是小於500微米。 請參照圖108至圖121，當金屬線路250比如是作為訊號傳 輸線路時，電子元件212之其中一個(比如是電子元件212a) 所輸出的電子訊號可以經由薄膜線路層232、234、236並穿 過保護層240後，傳輸至金屬線路250，接著再穿過保護層 240,並經由薄膜線路層236之連接線路237傳輸至凸塊260。 或者，由凸塊260所接收的電子訊號，可以穿過保護層240 傳輸至薄膜線路236之連接線路237，接著再穿過保護層240 傳輸至金屬線路250，然後再穿過保護層240，並經由薄膜線路 層236、234、232傳輸至電子元件212之至少其中一俩(比如 是電子元件212a)。當金屬線路250比如是作為電源匯流排時， 金屬線路250可以經由薄膜線路層236之連接線路237及凸塊280 連接至基板、軟板(tape)、薄膜基板(film)或是玻璃基板之電源端。 當金屬線路層250比如是作為接地匯流排時，金屬線路層250可 以經由薄膜線路層236之連接線路237及凸塊280連接至基板、 軟板(tape)、薄膜基板(film)或是玻璃基板之接地端。 請參照圖108 ’金屬線路250係暴露在外且直接接觸地 47 1284385 15625twf.doc/006 形成在保護層240上，金屬線路250可以連接暴露在保護層 240之開口 242外的薄膜線路層236之接點。凸壤280係直 接接觸地形成在保護層240之開口 242所暴露出之薄膜線路 層236的接點上。值得注意的是，凸塊280的厚度b29係大 於金屬線路250的厚度c;以此類推，當前述之柱狀凸塊2如、 291取代凸塊280時，柱狀凸塊290、291的庠度亦可以是尊 於金屬線路250的厚度c。然而’本發明的應用並不限於此， 請參照圖110,凸塊280的厚度b30亦可以是等於金屬線路250 的厚度c ;以此類推，當前述之柱狀凸塊290、291取代凸塊 280時，柱狀凸塊290、291的厚度亦可以是等於金屬線路250 的厚度。。 在圖111及圖112中，金屬線路250係直接接觸地形成 在保護層240上，且可以連接暴露在保護層240之開口 242 外的薄膜線路層236之接點。聚合物層245係形成在金屬線 路250上及保護層240上，藉以保護金屬線路250。凸塊280 係直接接觸地形成在保護層240之開口 242所暴露出之薄膜 線路層236的接點上。值得注意的是，在圖hi中，凸塊280 的厚度b31係大於金屬線路250與聚合物層245所加總的厚 度(c+d)，以此類推，當前述之柱狀凸塊290、291取代凸塊280 時，柱狀凸塊290、291的厚度亦可以是大於金屬線路250與 聚合物層245所加總的厚度。在圖112中，凸塊280的厚度 b32係小於金屬線路250與聚合物層245所加總的厚度(c+d)， 以此類推，當前述之柱狀凸塊290、291取代凸塊280時，柱 狀凸塊290、291的厚度亦可以是小於金屬線路250與聚合物 層245所加總的厚度。 在圖113、圖114及圖115中，聚合物層247係位於保 護層240上，聚合物層247具有多個開口 248 ,大致上係對 48 1284385 15625twf.doc/006 準保護層240之開口 242，並暴露出頂層之薄膜線路層236 的接點。金屬線路250係形成在聚合物層247上，並且經由 聚合物廣247之開口 248及保護層240之開口 242連接至薄 膜線路層236的接點。凸塊280係直接接觸地形成在保護層 240之開口 242所暴露出之薄膜線路層236的接點上。值得 注意的是，在圖113中，凸塊280的厚度b33係大於金靥線 路250與聚合物層247所加總的厚度(c+e)，以此類推，當前 述之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、291 的厚度亦可以是大於金屬線路250與聚合物層247所加總的 厚度。在圖114中，凸塊280的厚度b34係大致上相同於金 屬線路250與聚合物層247所加總的厚度(c+e)，以此類推， 當前述之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、 291的厚度亦可以是等於金屬線路250與聚合物層247所加 總的厚度。在圖115中，凸塊280的厚度b35係大於金靥線 路250與聚合物層247所加總的厚度(c+e)，以此類推，當前 述之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、291 的厚度亦可以是大於金屬線路250與聚合物層247所加總的 厚度。 在圖116及圖117中，聚合物層247係位於保護層240 上，聚合物層247具有多個開口 248,大致上係對準保護層240 之開口 242，並暴露出頂層之薄膜線路層236的接點。金屬 線路250係形成在聚合物層247上，並且經由聚合物層247 之開口 248及保護層240之開口 242連接至薄膜線路層236 的接點。聚合物層245係位於金屬線路250上及聚合物層247 上，用以保護金屬線路250。凸塊280係直接接鳞地形成在 保護層240之開口 242所暴露出之薄膜線路層236的接點上。 值得注意的是，在圖116中，凸塊280的厚度b36係小於金 49 1284385 15625twf.doc/006 ' · . · ·-• . · · 屬線路250與聚合物層245、247所加總的厚度(c+d+e)，以 此類推，當前述之柱狀凸塊290、291取代凸塊280時，柱狀 凸塊290、291的厚度亦可以是小於金屬綵路250與聚合物層 245、247所加總的厚度；在圖117中，凸塊280的厚度b37 係大於金屬線路250與聚合物層245、247所加總的厚度 (c+d+e)，以此類推，當翁述之柱狀凸塊29〇、291取代凸塊280 時，柱狀凸塊290、291的厚度亦可以是小於金屬線路250與 聚合物層245、247所加總的厚度。 在圖118及圖119中，聚合物層247係位於保護層240 上，聚合物層247具有多個開口 248，大致上對準保護層240鲁, 之開口 242，並暴露出頂層之薄膜線路層236的接點。金屬 線路250係形成在聚合物層247上，並且經由聚合物層247 之開口 248及保護層240之開口 242連接至薄膜線路層236 的接點。凸塊280係直接接觸地形成在保護層240之開口 242 及聚合物層247之開口 248所暴露出之薄膜線路層236的接 點上。值得注意的是，在圖118中，凸塊280凸出於外的厚 度b38係相同於金屬線路250的厚度c，以此類推，當前述 之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、291 凸出於外的厚度亦可以是相同於金屬線路250與聚合物層鲁 245、247所加總的厚度；在圖119中，凸塊280凸出於外的 厚度b39係大於金屬線路250的厚度c，以此類推，當前述 之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、291 凸出於外的厚度亦可以是大於金屬線路250與聚合物層245、 247所加總的厚度。 在圖120及圖121中，聚合物層247係位於保護層240 上，聚合物層247具有多個開口 248,大致上係對準保護層240 之開口 242，並暴露出頂層之薄膜線路層236的接點。金屬 50 1284385 15625twf.doc/006 線路250係形成在聚合物層247上，且可以經由聚合物層247 之開口 248及保護層240之間口 242連接至薄膜線路廣236 的接點。聚合物層245係位於金羼線路250上及聚合物層247 上，用以保護金屬線路250。凸塊280係直接接觸地形成在 保護層240之開口 242及聚合物屠247之開口 248所暴露出 之薄膜線路層236的接點上。值得注意的是，在周U0中, 凸塊280凸出於外的厚度b40係小於金屬線路250與聚合物 層245所加總的厚度(c+d)，以此類推，當前述之柱狀凸塊290、 291取代凸塊280時，柱狀凸塊290、291凸出於外的厚度亦 可以是相同於金屬線路250與聚合物層245所加總的厚度； 在圖121中’凸塊280凸出於外的厚度b41係大於金屬線路 250與聚合物層245所加總的厚度(c+d)，以此類推，當前述 之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、291 凸出於外的厚度亦可以是大於金屬線路250與聚合物層245 所加總的厚度。 在上述圖108至圖121的實施例中，聚合物脣245、247 的材質比如是聚醯亞胺(polyimide，PI)、苯基環丁嫦 (benzocyclobutene ’ BCB)、聚亞芳香基謎(parylene)、多孔性 介電材質或彈性體等，且聚合物層245、247的厚度d、e比 如係大於1微米。 D·金屬線路係作為外界電路構件之訊號傳輸、電源匯流 排或接地匯流排之用 圖122至圖134繪示依照本發明第二實施例之晶片結構的 剖面示意圖，其中金屬線路250係作為外界電路構件(未繪示） 之訊號傳輸、電源匯流排或接地匯流排之用，金屬線路250並 未連接頂層的薄膜線路層236。在電性連接上，比如可以利用打 線(wire_bonding)的方式使外界電路構件與金屬線路25〇電性連 51 1284385 15625twf.doc/006 接；或者，亦可以在外界電路構件上形成凸塊或焊球，用以連接 金屬線路250。當金羼線路250係作為外界電路構件之訊號 傳輸之用時’外界電路構件可以輸出一電子訊號至金屬線路 250,經由金屬線路250的傳輸之後，再僳輸至外界電路構件。 此外，金展線路250亦可以作為外界電路構件之電源風流辦 或接地匯流排，此時金屬線路250可以與外界電路構件之電 源匯流排或接地匯流排連接。 請參照圖122，金屬線路250係暴露在外且直接接觸地 形成在保護層240上，金屬線路250並未連接頂層的薄膜線路 層236。凸塊280係直接接觸地形成在保護層240之開口 242 所暴露出之薄膜線路層236的接點上。值得注意的是，凸塊 280的厚度b42係大於金屬線路250的厚度c ;以此類推，當 前述之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、 291的厚度亦可以是等於金屬線路250的厚度c。然而，本發 明的應用並不限於此，請參照圖123，凸塊280的厚度b43 亦可以是等於金屬線路250的厚度c ;以此類推，當前述之 柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、291的 厚度亦可以是等於金屬線路250的厚度c。 在圖124及圖125中，金屬線路250係直接接觸地形成 在保護層240上，且並未連接頂層的薄膜線路層236。聚合物 層245係形成在金屬線路250上及保護層240上，藉以保護 金屬線路250，聚合物層245具有開口 246，暴露出金屬線路 250，使得透過聚合物層245之開口 246，凸塊、焊球或打線 方式所形成的導線可以電性連接金屬線路250與外界電路構 件。值得注意的是，在圖124中，凸塊280的厚度b44係大 於金屬線路250與聚合物層245所加總的厚度(c+d)，以此類 推，當前述之柱狀凸塊290、291取代凸塊280時，柱狀凸塊 52 1284385 15625twf.doc/006 290、291的厚度亦可以是大於金屬線路250與聚合物層245 所加總的厚度。在圖125中，凸塊280的厚度b45徐小於金 屬線路250與聚合物層245所加總的厚度(c+d)，以此類推， 當前述之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、 291的厚度亦可以是小於金屬線路250與聚合物層245所加 總的厚度。 在圖126、圖127及圖128中，聚合物層247係位於保 護層240上，金屬線路250係形成在聚合物層247上，且並 未連接頂層的薄膜線路層236。凸塊280係直接接觸地形成在 保護層240之開口 242所暴露出之薄膜線路層236的接點上。 值得注意的是，在圖126中，凸塊280的厚度b46係大於金^ 屬線路250與聚合物層247所加總的厚度(c+e)，以此類推， 當前述之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、 291的厚度亦可以是大於金屬線路250與聚合物層247所加 總的厚度。在圖127中，凸塊280的厚度b47係大致上相同 於金屬線路250與聚合物層247所加總的厚度(c+e)，以此類 推，當前述之柱狀凸塊290、291取代凸塊280時，柱狀凸塊 290、291的厚度亦可以是等於金屬線路250與聚合物層247 所加總的厚度。在圖128中，凸塊280的厚度b48係大於金 屬線路250與聚合物層247所加總的厚度(c+e)，以此類推， 當前述之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、 291的厚度亦可以是大於金屬線路250與聚合物層247所加 總的厚度。 在圖129及圖130中，聚合物層247係位於保護層240 上’金屬線路250係形成在聚合物層247上，且並未連接頂層 的薄膜線路層236。聚合物層245係位於金屬線路250上及聚 合物層247上，用以保護金屬線路250，聚合物層245具有 53 1284385 15625twf.doc/006 • . · . ·.* 開口 246 ’暴露出金屬線路250，使得透過聚合物層245之開 口 246，凸塊、焊球或打線方式所形成的導線可以電性連接 金屬線路250與外界電路構件。凸塊28〇係直接接觸地形成 在保護層240之開口 242所暴露出之薄膜線路層236的接點 上。值得注意的是，在圖129中，凸塊280的厚度b49係小 於金屬線路250與聚合物層245、247所加總的厚度(c+d+e), 以此類推，當前述之柱狀凸塊290、291取代凸塊280時，柱 狀凸塊290、291的厚度亦可以是小於金屬線路250與聚合物 層245、247所加總的厚度；在圖13〇中，凸塊28〇的厚度七5〇 係大於金屬線路250與聚合物層245、247所加總的厚度 (c+d+e)’以此類推，當前述之柱狀凸塊290、291取代凸塊280 時’柱狀凸塊290、291的厚度亦可以是小於金屬線路250與 聚合物層245、247所加總的厚度。 在圖131及圖132中，聚合物層247係位於呆護層240 上’金屬線路250係形成在聚合物層247上，且並未蓮接頂層 的薄膜線路層236。凸塊280係直接接觸地形成在保護層240 之開口 242及聚合物層247之開口 248所暴露出之薄膜線路 層236的接點上。值得注意的是，在圖131中，凸塊280凸 出於外的厚度b51係相同於金屬線路250的厚度c，以此類 推，當前述之柱狀凸塊290、291取代凸塊280時，柱狀凸塊 290、291凸出於外的厚度亦可以是相同於金屬線路250與聚 合物層245、247所加總的厚度；在圖132中，凸塊280凸出 於外的厚度b52係大於金屬線路250的厚度c，以此類推， 當前述之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、 291凸出於外的厚度亦可以是大於金屬線路250與聚合物層 245、247所加總的厚度。 在圖133及圖134中，聚合物層247係位於保護層240 54 1284385 15625twf.doc/006 上，金屬線路250係形成在聚合物層247上，且並未連接頂層 的薄膜線路層236。聚合物層245係位於金屬線路250上及聚 合物層247上，用以保镬金屬線路250，聚合物層245具有 開口 246，暴露出金屬線路25〇 ,使得透過乘合物層245之開 口 246 ’凸塊、焊球或打線方式所形成的導線可以電性薄接 金屬線路250與外界電路構件。凸塊280係直接接觸地形成 在保護層240之開口 242及聚合物層247之開口 248所暴露 出之薄膜線路層236的接點上。值得注意的是，在圖133中， 凸塊280凸出於外的厚度b53係小於金屬線路250與聚合物 層245所加總的厚度(c+d)，以此類推，當前述之柱狀凸塊290、 291取代凸塊280時，柱狀凸塊290、291凸出於外的厚度亦 可以是相同於金屬線路250與聚合物層245所加總的厚度； 在圖134中，凸塊280凸出於外的厚度b54係大於金屬線路 250與聚合物層245所加總的厚度(c+d)，以此類推，當前述 之柱狀凸塊290、291取代凸塊280時，柱狀凸塊290、291 凸出於外的厚度亦可以是大於金屬線路250與聚合物層245 所加總的厚度。 在上述圖122至圖134的實施例中，聚合物層245、247 的材質比如是聚醯亞胺（polyimide，pi)、苯基環丁烯 (benzocydobutene，BCB)、聚亞芳香基醚(parylene)、多孔性 介電材質或彈性體等，且聚合物層245、247的厚度d、e比 如係大於1微米。 三、晶片結構製作方法的第三實施你丨 •圖135至圖138繪示依照本發明第三實施例中在半導體晶圓 上製作金屬線路及凸塊的剖面示意圖。請參照圖135，首先提供 一半，體晶圓200，半導體晶圓2〇〇包括一半導禮基底21〇、多 數層薄膜介電層222、224、226、多數層薄膜線路層232、以4、 55 1284385 15625twf.doc/006 236及一保s蔓層240 ,其詳細結構在第一實施例的第1點中有 詳盡的敘述，在此便不再贅述。 . 請參照圖135 ’在提供半導體晶圓200之後，可以利用濺錄 的方式形成底部金屬層250在半導體晶圓200之保護層240上及 暴露於保護層240之開口 242外的薄膜線路層236之接點 236a、236b上，在此過程中，比如包括先滅鍍黏著/阻障層在 半導體晶圓200之保護層240上及暴露於保護層240之開p 242 外的薄膜線路層236上，接著再減鍍種子層在黏著/阻障層上， 黏者/阻障層及種子層的材質係敘述如後，在此便不再贅述。 接者’可以形成光阻層260在底部金屬層252上，光阻層260 具有開口 262，暴露出底部金屬層252，如圖135所示。接著， 可以利用電鍵的方式，形成具有線路圓案254a及凸塊调案254c 之金屬層254在光阻層260之開口 262所暴露出的底部金屬層252 上，如圖136所示，其中金屬層254之線路圖案254a係電性連 接薄膜線路層236之接點236a，且在保護層240上延伸，金 屬層254之凸塊圖案254c係位在薄膜線路層236之接點236a 上。定義一平面1000 ,平面1000係大致上平行於半導體基 底210之主動表面214，其中金屬層254之線路圖案254a投影 至平面1000上的延伸距離比如係大於50〇微米，或者比如係 大於800微米，或者比如係大於12〇〇微米；金屬層254之線 路圖案254a投影至平面1〇〇〇上的面積比如係大於3〇,〇〇〇平 方微米，或者比如係大於80,000平方微米，或者比如係大於 150,000平方微米。金屬層254之每一凸塊圖案254c投影至平 面1000上的面積比如係小於30,00〇平方微米，或者比如係 小於20,000平方微米，或者比如係小於15,000平方微米。 接著’可以將光阻層260去除，暴露出底部金屬層252 ,如 圖137所示。接著，再以金屬層254作為蝕刻罩壁，透過蝕刻 56 1284385 15625twf.doc/006 的方式依序去除未被金屬層254覆蓋之底部金屬層252的種 子層及黏著/阻障層，僅留下位在金屬層254下的底部金屬層 252，如圖138所示。 之後，可以進行單切的步驟，此時切割刀會沿著半導體 晶圓200之切割道(scribe-line)來切割半導體晶圓200，藉以 形成多個獨立的晶片結構205。 在上述的製程中，金屬線路250及凸塊280可以同時完 成，由於金屬線路250及凸塊280之底部金屬層252係由同 一道濺鍍步驟所形成，且金屬線路250及凸塊280之金屬層 254係由同一道電鍍步驟所形成，故可以簡化形成金屠線路 250及凸塊280的步驟。 2·金屬線路及凸塊之金屬層結構 請參照圖139,其繪示依照本發明第三實施例之金屬線 路及凸塊之金屬層結構的剖面示意圖，其中在形成底部金屬 層252時，比如係先利用濺鍍製程形成黏著/阻障屠2521a, 接著再利用濺鍍的方式形成作為種子層之金層2521b於黏著/ 阻障層2521a上，其中黏著/阻障層2521a之材質比如係為鈦、 欽鶴合金、鈦氮化合物、钽或组敗化合物萼。在形成金展層 254時，比如係利用電鍍的方式形成厚度X大於3微米的金 層在底部金屬層252之種子層2521b上。 3.凸塊、金屬線路舆聚合物層之間的厚度關係 在第三實施例中，如圖138所示，金屬線路250係暴露 在外且直接接觸地形成在保護層240上，金屬線路250可以 連接暴露在保護層240之開口 242外的薄膜線路層236之接 點。凸塊280係直接接觸地形成在保護層240之開口 242所 暴露出之薄膜線路層236的接點上。值得注意的是，凸塊280 的厚度b55係等於金屬線路250的厚度c。 57 1284385 15625twf.doc/006 在圖140中，金屬線路250係直接接觸地形成在保護層 240上，且可以連接暴露在保護層240之開口 242外的薄艇 線路層236之接點，一聚合物層245係形成在金屬線路250 上及保護層240上，藉以保護金屬線路250。凸塊280係真 接接觸地形成在保護層240之開口 242所暴露出之薄艇線路 層236的接點上。值得注意的是，在圓140中，凸塊280的 厚度b56係等於金屬線路250的厚度c，且小於金屬線路250 與聚合物層245所加總的厚度(c+d)。 在圖141中，聚合物層247係位於保護層240上，聚合 物層247具有多個開口 248，大致上係對準保護層240之開 口 242,並暴露出頂層之薄膜線路層236的接點。金屬線路250 係形成在聚合物層247上，並且經由聚合物層247之開口 248 及保護層240之開口 242連接至薄膜線路層236的接點。凸 塊280係直接接觸地形成在保護層240之開口 242所暴露出 之薄膜線路層236的接點上。值得注意的是，在圖141中， 凸塊280的厚度b57係等於金屬線路250的厚度c，且小於 金屬線路250與聚合物層247所加總的厚度(c+e)。 在圖142中，聚合物層247係位於保護層240上，聚合 物層247具有多個開口 248，大致上係對準保護層240之開 口 242，並暴露出頂層之薄膜線路層236的接點。金屬線路250 係形成在聚合物層247上，並且經由聚合物層247之開口 248 及保護層240之開口 242連接至薄膜線路層236的接點。聚 合物層245係位於金屬線路250上及聚合物層247上，用以 保護金屬線路250。凸塊280係直接接觸地形成在保護層240 之開口 242所暴露出之薄膜線路層236的接點上。值得注意 的是，在圖142中，凸塊280的厚度b58係等於金屬線路250 的厚度c，且小於金屬線路250與聚合物層245、247所加總 58 1284385 15625twf.doc/006 的厚度(c+d+e) 〇 在圖143中，聚合物層247係位於保護層24〇上，聚合 物層247具有多個開口 248，大致上對準保護層240之開口 242，並暴露出頂層之薄膜線路層236的接點。金屡線路250 係形成在聚合物層247上，並且經由聚合物層247之開口 248 及保護層240之開口 242連接至薄膜線路層236的無點。凸 塊280係直接接觸地形成在保護層240之開口 242及聚合物 層247之開口 248所暴露出之薄膜線路層236的接點上。僮 得注意的是，在圖143中，凸塊280凸出於外的庠度上59係 相同於金屬線路250的厚度c。 在圖144中，聚合物層247係位於保護層240上，聚合 物層247具有多個開口 248，大致上係對準保護層240之開 口 242,並暴露出頂層之薄膜線路層236的接點。金屬線路250 係形成在聚合物層247上，且可以經由聚合物層247之開口 248及保護層240之開口 242連接至薄膜線路層236的接點〇 聚合物層245係位於金屬線路250上及聚合物層247上，用 以保護金屬線路250。凸塊280係直接接觸地形成在保護層240 之開口 242及聚合物層247之開口 248所暴露出之薄膜線路 層236的接點上。值得注意的是，在圖144中，凸塊280凸 出於外的厚度b60係等於金屬線路250的厚度c，且小於金 屬線路250與聚合物層245所加總的厚度(c+d)。 在上述圖140至圖144的實施例中，聚合物層245、247 的材質比如是聚醯亞胺（polyimide，PI)、苯基瓖丁烯 (benzocyclobutene，BCB)、聚亞芳香基醚(parylene)、多孔性 介電材質或彈性鱧等，且聚合物層245、247的厚度d、e比 如係大於1微米〇 4·金屬線路的功能 59 1284385 15625twf.doc/006 Α·金屬線路係作為晶片結構之内部訊號傳輸之用 請參照圖138及圖140至圖144，金展線路250係作為 晶片結構205之内部訊號傳輸之用，亦即電子元妹212之其 中一個（比如是電子元件212a)係適在輪出一電子訊號，此電 子訊號經由薄膜線路層232、234、236並穿過保護層240後， 傳輸至金屬線路250，接著再穿過保護層24〇，並經由薄膜線 路層236、234、232傳輸至其他的電子元件212之至少其中 一個（比如是電子元件212b)。 B·金屬線路係作為晶片結構之電源匯流排或揍地匯流排 之用 圖145至圖150繪示依照本發明第三實施例之晶片結構的 剖面示意圖，其中金屬線路250可以與薄膜線路層之薄膜電源 匯流排235電性連接，作為晶片結構205之電源匯流排。或 者，金屬線路250亦可以與薄膜線路層之薄膜接地匯流排235 電性連接，作為晶片結構205之接地匯流排。 請參照圖145，金屬線路250係暴露在外且直接接觸地 形成在保護層240上，且可以連接暴露在保護層240之開口 242外的薄膜線路層236之接點。凸塊280係直接接觸地形 成在保護層240之開口 242所暴露出之薄膜線路層236的接 點上。值得注意的是，凸塊280的厚度b61係等於金屬線路 250的厚度c。 在圖146中，金屬線路250係直接接觸地形成在保護層 240上，一聚合物層245係形成在金屬線路250上及保護層240 上，藉以保護金屬線路250。凸塊280係直接接觸地形成在 保護層240之開口 242所暴露出之薄膜線路層236的接點上。 值得注意的是，在圖146中，凸塊280的厚度b62係等於金 屬線路250的厚度c，且小於金屬線路250與聚合物層245 1284385 1靜砷 15625twf.doc/006 所加總的厚度(c+d)〇 在圖147中，聚合物層247係位於保護層240上，聚合 物層247具有多個開口 248，大致上係對準保護層240之開 口 242,並暴露出頂層之薄膜線路層236的接點。金屬線路250 係形成在聚合物層247上，並且經由聚合物層247之開口 248 及保護層240之開口 242連接至薄膜線路層236的接點。凸 塊280係直接接觸地形成在保護層240之蘭口 242所暴露出二 之薄膜線路層236的接點上。值得注意的是，在圖147中， 凸塊280的厚度b63係等於金屬線路250的厚度c，且小於 · 金屬線路250與聚合物層247所加總的厚度(c+e)。 籲 在圖148中，聚合物層247係位於保護層240上，聚合 物層247具有多個開口 248，大致上係對準保護層240之開 口 242,並暴露出頂層之薄膜線路層236的接點。金孱線路250 係形成在聚合物層247上，並且經由聚合物層247之開口 248 及保護層240之開口 242連接至薄膜線路層236的接點。聚 合物層245係位於金屬線路250上及聚合物層247上，用以 保護金屬線路250。凸塊280係直接接觸地形成在保護層240 ,, 之開口 242所暴露出之薄膜線路層236的接點上。值得注意泰 的是，在圖148中，凸塊280的厚度b64係等於金屬線路250 * 的厚度c，且小於金屬線路250與聚合物層245、247所加總 的厚度(c+d+e)。 在圖149中，聚合物層247係位於保護層240上，聚合 物層247具有多個開口 248，大致上對準保護層240之開口 242 ’並暴露出頂層之薄膜線路層236的接點。金屬線路250 係形成在聚合物層247上，並且經由聚合物層247之開口 248 及保護層240之開口 242連接至薄膜線路層236的接點。凸 塊280係直接接觸地形成在保護層240之開口 242及聚合物 1284385 15625tw£docA)06 層247之開口 248所暴露出之薄膜線路層236的接點上。值 得注意的是，在圖149中，凸塊280凸出於外的厚度b65係 相同於金屬線路250的厚度e。 在圖150中，聚合物層247係位於保護層240 土，聚合 物層247具有多個開口 248，大致上係對準保護層240之開 口 242,並暴露出頂層之薄膜線路層236的接點。金屬線路250 係形成在聚合物層247上，且可以經由聚合物層247之開口 248及保護層240之開口 242連揍至薄膜線路層236的接點、 聚合物層245係位於金屬線路250上及聚合物層247上，用 以保護金屬線路250。凸塊280係直接接觸地形成在保護層240 · 之開口 242及聚合物層247之開口 248所暴露出之薄膜線路 層236的接點上。值得注意的是，在圖150中，四塊280凸 出於外的厚度b66係等於金屬線路250的厚度c，且小於金 屬線路250與聚合物層245所加總的厚度(c+d)。 在上述圖145至圖150的實施例中，聚合物層245、247 的材質比如是聚醯亞胺（polyimide，PI)、苯基環丁烯 (benzocyclobutene，BCB)、聚亞芳香基it(parylene)、多孔性 介電材質或彈性體等，且聚合物層245、247的厚度d、e比 如係大於1微米。 籲 C·金屬線路係作為訊號傳輸線路、電源儀流排或接地匯流 排之用，其中金屬線路係利用頂層之薄膜線路層電性連接凸塊 請參照圖151至圖157，其繪示依照本發明第三實施例之晶 片結構的剖面示意圖，其中金屬線路250係利用頂層之薄膜線路 層236連接凸塊280,金屬線路層250比如係作為訊號傳輸線路、 電源匯流排或接地匯流排之用。金屬線路250係位於保護層 240上，且經由保護層240之開口 242電性連接於薄臈線路 層236之接點237a。凸塊280係位在保護層240之開口 242 62 1284385 15625twf.doc/006 所暴露出的薄膜線路層236之接點237b上。薄膜線路層236 具有一連接線路237，連接接點237&、23713，使得金屬線路 250可以透過連接線路237及接點237a、237b電性連接凸塊 280。請參照圖152，其繪示連接線路237及接痴237汪、2371> 的上視示意圖，在較佳的情说下，連接線路237的延伸距離s 比如是小於500微米。 請參照圖151至圖157，當金屬線路250比如是作為訊號傳 輸線路時，電子元件212之其中一個（比如是電子元件212a) 所輸出的電子訊號可以經由薄膜線路層232、234、236並穿 過保護層240後，傳輸至金屬線路250，接著再穿過保護層 240,並經由薄膜線路層236之連接線路237傳輸至凸塊260。 或者，由凸塊260所接收的電子訊號，可以穿過保護層240 傳輸至薄膜線路236之連接線路237，接著再穿過保護層240 傳輸至金屬線路250，然後再穿過保護層240，並經由薄膜線路 層236、234、232傳輸至電子元件212之至少其中一個(比如 是電子元件212a)。當金屬線路250比如是作為電源匯流排時， 金屬線路250可以經由薄膜線路層236之連接線路237及凸塊280 連接至基板、軟板(tape)、薄膜基板(film)或是玻璃基板之電源端。 當金屬線路層250比如是作為接地匯流排時，金屬線路層250可 以經由薄膜線路層236之連接線路237及凸塊280連接至基板、 軟板(tape)、薄膜基板(film)或是玻璃基板之接地端。 請參照圖151 ’金屬線路250係暴露在外且直接接觸地 形成在保護層240上，金屬線路250可以連接暴露在保镬層 240之開口 242外的薄膜線路層236之接點。凸塊280係直 接接觸地形成在保護層240之開口 242所暴露出之薄膜線路 層236的接點上。值得注意的是，凸塊280的厚度b67係等 於金屬線路250的厚度c。 63 1284385 15625twf.doc/006 在圖153中，金屬線路250係直接接觸地形成在保護層 240上，且可以連接暴露在保護層240之開口 242外的薄膜 線路層236之接點。聚合物層245係形成在金屬線路250上 • · . - .· ·· . 及保護層240上，藉以保護金屬線路250。凸塊280係直接 接觸地形成在保護層240之開口 242所暴霹出之薄膜線路層 236的接點上。值得注意的是，在圓153中，凸塊280的厚 度b68係等於金屬線路250的厚度c，且小於金屬線路250 與聚合物層245所加總的厚度(c+d)。 在圖154中，聚合物層247係位於保護層240上，聚合 物層247具有多個開口 248，大致上係對準保護層240之開 口 242,並暴露出頂層之薄膜線路層236的接點。金羼線路250 係形成在聚合物層247上，並且經由聚合物層247之開口 248 及保護層240之開口 242連接至薄膜線路層236的接點。凸 塊280係直接接觸地形成在保護層240之開口 242所暴露出 之薄膜線路層236的接點上。值得注意的是，在圖154中， 凸塊280的厚度b69係等於金屬線路250的厚度c，且小於 金屬線路250與聚合物層247所加總的厚度(c+e)。 在圖155中，聚合物層247係位於保護層240上，聚合 物層247具有多個開口 248，大致上係對準保護層240之開 口 242,並暴露出頂層之薄膜線路層236的接點。金屬線路250 係形成在聚合物層247上，並且經由聚合物層247之開口 248 及保遵層240之開口 242連接至薄膜線路層236的接點。聚 合物層245係位於金屬線路250上及聚合物層247上，用以 保護金屬線路250。凸塊280係直接接觸地形成在保護層24〇 之開口 242所暴露出之薄膜線路層236的接點上。值得注意 的是，在圖155中，凸塊280的厚度b70係等於金屬線路25〇 的厚度c，且小於金屬線路250與聚合物層245、247所加總 1284385 15625twf.doc/006 的厚度(c+d+e)。 在圖156中，聚合物層247係位於保護層240上，聚合 物層247具有多個開口 248，大致上對準保護屠240之開口 242，並暴露出頂層之薄膜線路層236的揍點。金屬線路250 係形成在聚合物層247上，並且經由聚合物層247之開口 248 及保護層240之開口 242連接至薄膜線路層236的接點。凸 塊280係直接接觸地形成在保護屑240之開口 242及聚合物 層247之開口 248所暴露出之薄膜線路層236的接點上。值 得注意的是，在圖156中，凸塊280凸出於外的厚度b71係 相同於金屬線路250的厚度c。 在圖157中，聚合物層247係位於保護層240上，聚合 物層247具有多個開口 248，大致上係對準保護層240之開 口 242，並暴露出頂層之薄膜線路層236的接點。金屬線路250 係形成在聚合物層247上，且可以經由聚合物層247之開口 248及保護層240之開口 242連接至薄膜線路層236的接點。 聚合物層245係位於金屬線路250上及聚合物層247上，用 以保護金屬線路250。凸塊280係直接接觸地形成在保護屠240 之開口 242及聚合物層247之開口 248所暴露出之薄膜線路 層236的接點上。值得注意的是，在圖157中，凸塊280凸 出於外的厚度b72係小於金屬線路250與聚合物層245所加 總的厚度(c+d)。 在上述圖151至圖157的實施例中，聚合物層245、247 的材質比如是聚醯亞胺（polyimide，PI)、苯基環丁烯 (benzocyclobutene，BCB)、聚亞芳香基醚(parylene)、多孔性 介電材質或彈性體等，且聚合物層245、247的厚度d、e比 如係大於1微米。 D·金屬線路係作為外界電路構件之訊號傳輸、電源匯流 65 1284385 15625twf.doc/006 排或接地匯流排之用 圖158至圖163繪示依照本發明第三實施例之晶片結構的 剖面示意圖，其中金屬線路250係作為外界電路構件(未緣示) 之訊说傳輸、電源匯流排或接地匯流排之用，金屬線路250並 未連接頂層的薄膜線路層236。在電性連接上，比如可以利用打 線(wire-bonding)的方式使外界電路構件與金屬線路25〇電植連 接；或者，亦可以在外界電路構件上形成凸塊或焊球,用以連接 金屬線路250。當金屬線路250係作為外界電路構件之訊號 傳輸之用時’外界電路構件可以輪出一電子訊號至金屬線路 250’經由金屬線路250的傳輸之後，再傳輸至外界電路構件。 此外，金屬線路250亦可以作為外界電路構件之電源匯流排 或接地匯流排，此時金屬線路250可以與外界電路構件之電 源匯流排或接地匯流排連接。 請參照圖158 ,金屬線路250係暴露在外且直接接觸地 形成在保護層240上，金屬線路250並未連接頂層的薄膜線路 層236。凸塊280係直接接觸地形成在保護層240之開口 242 所暴露出之薄膜線路層236的接點上。值得注意的是，凸塊 280的厚度b73係等於金屬線路250的厚度c。 在圖159中，金屬線路250係直接接觸地形成在保護層 240上，且並未連接頂層的薄膜線路層236。聚合物層245係形 成在金屬線路250上及保護層240上，藉以保護金屬線路250， 聚合物層245具有開口 246，暴露出金屬線路250，使得透過 聚合物層245之開口 246，凸塊、焊球或打線方式所形成的 導線可以電性連接金屬線路250與外界電路構件。值得注意 的是，在圖159中，凸塊280的厚度b74係等於金屬線路250 的厚度c，且小於金屬線路250與聚合物層245所加總的厚 度(c+d)。 66 1284385 15625twf.doc/006 在圖160中，聚合物層247係位於保護層240上，金羼 線路250係形成在聚合物層247上，且並未連接頂層的薄膜線 路層236。凸塊280係直接接觸地形成在保護廣240之開口 242 所暴露出之薄膜線路層236的接點上。值得注意的是，在圖 160中，凸塊280的厚度b75係等於金屬線路250的厚度c， 且小於金屬線路250與聚合物層247所加總的厚度(c+e) 〇 在圖161中，聚合物層247係位於保護層240上，金屬 線路250係形成在聚合物層247上，且並未連接頂層的薄膜線 路層236。聚合物層245係位於金屬線路250上及聚合物層247 上，用以保護金屬線路250，聚合物層245具有開口 246，暴 露出金屬線路250,使得透過聚合物層245之開口 246,凸塊、 焊球或打線方式所形成的導線可以電性連接金屬線路250與 外界電路構件。凸塊280係直接接觸地形成在保護層240之 開口 242所暴露出之薄膜線路層236的接點上。值得注意的 是，在圖161中，凸塊280的厚度b76係等於金屬線路250 的厚度，且小於金屬線路250與聚合物層245、247所加總的 厚度(c+d+e)。 在圖162中，聚合物層247係位於保護層240上，金屬 線路250係形成在聚合物層247上，且並未連接頂層的薄膜線 路層236。凸塊280係直接接觸地形成在保護展240之開口 242 及聚合物層247之開口 248所暴露出之薄膜線路層236的接 點上。值得注意的是，在圖162中，凸塊280凸出於外的厚 度b77係相同於金屬線路250的厚度c。 在圖163中，聚合物層247係位於保護層240上，金屬 線路250係形成在聚合物層247上，且並未連接頂層的薄膜線 路層236。聚合物層245係位於金屬線路250上及聚合物層247 上，用以保護金屬線路250，聚合物層245具有開口 246，暴 67 1284385 15625twf.doc/006 露出金屬線路250,使得透過聚合物層245之開口 246,凸塊、 焊球或打線方式所形成的導線可以電性連接金屬線路250與 外界電路構件。凸塊280係直接接觸地形成在保護層240之 開口 242及聚合物層247之開口 248所暴露出之薄膜線路層 236的接點上。值得注意的是，在圖163中，凸塊28Q凸出 於外的厚度b78係等於金屬線路250的厚度（：，且小於金展 線路250與聚合物層245所加總的厚度(c+d)。 在上述圖158至圓163的實施例中，聚合物層245、247 的材質比如是聚醯亞胺（polyimide，Π)、笨基環丁烯 (benzocyclobutene ’ BCB)、聚亞芳香基醚(parylene)、多孔性 介電材質或彈性體等，且聚合物層245、247的厚度d、e比 如係大於1微米。 四、結論 綜上所述，本發明之晶片結構及其製作方法，可以將製作凸 塊的步驟與製作金屬線路的步驟整合，藉以簡化形成金屬線路及 凸塊的製程步驟。 本發明之晶片結構及其製作方法，可以形成厚度大於丨微米 的銅層或金層在半導體晶圓的保護層上，以作為金屬線路，並且 可以形成厚度大於3微米的金層或焊料層在半導體晶圓的保護層 上，以作為凸塊。 雖然本發明已以一較佳實施例揭露如上，然其並非用以限定 十發明’任何熟習此技藝者，在不脫離本發明之精神和範圍内， 备可作些許之更動與潤飾，因此本發明之保護範圍當視後附之 請專利範圍所界定者為準。 68 1284385 15625twf.doc/006 【圖式簡單說明】 圖1至圖12繪示習知在半導體晶圓上製作金屬線路及凸塊 之製程的剖面示意圖〇 圖13至圖21繪示依照本發明第一實施例中在丰導體晶圓上 製作金屬線路及凸塊之第一種製作方法的刮面示意圖。 圖22至圖25繪示依照本發明第一實施例之金屬線路及 接墊之金屬層結構的剖面示意圖。 圖26至圖29繪示依照本發明第一實施例之凸塊結搛的 剖面示意圖。 圖30至圖33繚示依照本發明第一實施例中在半導體晶圓上 製作金屬線路及凸塊之第二種製作方法的剖面示意圖。 圖34至圖39繪示依照本發明第一實施例中在半導艘晶圓 上製作金屬線路及第一種形式之柱狀凸塊的第一種製作方法之剖 面示意圖。 圖40及圖41繪示依照本發明第一實施例中在半導體晶圓 上製作金屬線路及第一種形式之柱狀凸塊的第二種製作方法之剖 面示意圖。 圖42至圖47緣示依照本發明第一實施例中在半導體晶圓 上製作金屬線路及第二種形式之柱狀凸塊的第一種製作方法之剖 面示意圖。 圖48至圖52緣示依照本發明第一實施例中在丰導體晶圓 上製作金屬線路及第二種形式之柱狀凸塊的第二種製作方法之剖 面示意圖。 圖53繪示依照本發明第一實施例中保護層上具有金屬線 路、凸塊及聚合物層之晶片結構的剖面示意圖。 圖54及圖55缘示依照本發明第一實施例之晶片結構的剖 面示意圖，其中金屬線路係作為晶片結構之内部訊號傳輸之 用。 69 1284385 15625twf.doc/006 圖56及圖57繪示依照本發明第一實施例之晶片結構的剖 面示意圖，其中金屬線路係作為晶片結構之電源匯流排或接地 匯流排之用。 圖58及圖59繪示依照本發明第一實施例之晶片結構的剖 面示意圖，其中金屬線路係作為外界電路構件之訊號傳輸、電 源匯流排或接地匯流排之用。 圖60至圖66繪示依照本發明第二實施例中在半導體晶圓上 製作金屬線路及凸塊的咅彳面示意圖。 圖67至圓70繪示依照本發明第二實施例之金屬線路之 金屬層結構的剖面示意圖。 圖71及圓72繪示依照本發明第二實施例之凸塊緯構的 剖面示意圖。 圖73至圖77繪示依照本發明第二實施例中在半筹體晶圓 上製作金屬線路及第一種形式之柱狀凸塊的剖面示意圖。 圖78至圖82繪示依照本發明第二實施例中在半導髏晶圓 上製作金屬線路及第二種形式之柱狀凸塊的剖面示意圖。 圖83至圖94繪示依照本發明第二實施例之晶片結構的剖 面示意圖’其中金屬線路係作為晶片結構之内部訊號傳輸之 用。 圖95至圖107繪示依照本發明第二實施例之晶片結；j：籌的剖 面示意圖，其中金屬線路係作為晶片結構之電源匯流排或接 匯流排之用。 圖108至@ 121緣示依照本發明第二實施例之晶片結構的 面示意圖，其中金屬線路係作為訊號傳輪線路、電源匯流 接地匯流排之用，且金屬線路係利用頂層之薄膜線路層電性連 接凸塊。 圖122至圖134繪示依照本發明第二實施例之晶片結 剖面示意圖，其中金屬線路係作為外界電路構件之訊號^ ' 電源匯流排或接地匯流排之用。 ' J " 1284385 15625twf.doc/006 圖135至圖138繪示依照本發明第三實施例中在半導體晶圓 上製作金屬線路及凸塊的剖面示意圖。 圖139緣示依照本發明第三實施例之金屬線路及凸塊之 金屬層結構的剖面示意圖。 圖140至圖144繪示依照本發明第三實施例之晶月結構的 剖面示意圖，其中金屬線路係作為晶片結構之内部訊號傳輸之 用。 圖145至圖150緣不依照本發明第三實施例之晶片結構的 剖面示意圖，其中金屬線路係作為晶片結構之電源匯流排或接 地匯流排之用。 if1 ί示依照本發明第三實施例之晶片結構的剖 面示忍圖’其中金屬線路係作為訊號傳輪線路、電源匯流排或 接地匯流排之用，結屬線路係利用頂層之薄路層電性連 接凸塊。 幻二至甘圖二1示依照本發明第三實施例之晶片結構的 j面不〜圖’其中金屬線路係作為外界電路構件之訊號傳輸、 電源匯流排或接地匯流排之用。 【主要元件符號說明】 10 :路徑 100:半導體晶片 110 :半導體基底 112:電子元件 114 :主動表面 121、 123、125 :導通孔 122、 124、126:薄膜介電層 132、134、136 :薄膜線路層 140 :保護層 150 :金屬線路 152 :底部金屬層 71 1284385 15625twf.doc/006 154 線路圖案之金屬層 160 光阻層 162 光阻層之開口 170 聚合物層 172 聚合物層之開口 180 凸塊 182 底部金展層 184 凸塊圖案之金屬層 190 光阻層 192 光阻層之開口 200 半導體晶片 205 晶片結構 210 半導體基底 212 電子元件 214 主動表面 221、 223、225 :導通孔 222、 224、226 :薄膜介電層 232、234、236 :薄膜線路層 235 :薄膜電源匯流排、薄膜接地匯流排 236a、236b、237a、237b ··薄膜線路層之接點 237 :連接線路 240 :保護層 245 :聚合物層 246 :聚合物層之開口 247 ··聚合物層 248 :聚合物層之開口 250 :金屬線路 251 ··接墊 252 :底部金屬層 72 1284385 15625twf.doc/006 2521a、2522a、2523a、2524a :黏著/阻障層 2521b、2522b、2523b、2524b :種子層 254:金屬層 254a :金屬層之線路圖案 254b :金屬屠之接墊圖案 254c :金屬層之凸塊圖案 2543a :銅層 2543b :鎳層 2544a ··銅層 2544b :鎳層 2544c ··金層 260 ··光阻層 262 :光阻層之開口 270 :光阻層 272:光阻層之開口 275 :光阻層 276:光阻層之開口 280 ··凸塊 2801 :金層 2802a:黏著/阻障層 2802b :金層 2803 :焊料層 2804a :黏著/阻障層 2804b :銅層 2804c :鎳層 2804d :焊料層 282 :凸塊圖案之金屬層 2822a :銅層 2822b :鎳層 73 1284385 15625twf.doc/006 2822c :焊料層 290、291 :柱狀凸塊 292 :金屬柱 293 :底部金屬層 294 :柱狀金屬層 295 :防崩落層 296 :焊料層 1000 ··平面Electronic component 212b). At the same time, the electronic signal outputted by the electronic component 212a can also be transmitted to the external circuit component through the bump 28C located on the metal line 25A (not shown). It is noted that the metal line 250 can be formed in direct contact with The protective layer 240 is shown as shown in FIG. 54; alternatively, the polymer layer 245 may be formed on the protective layer 240, and then the metal line 25 is formed on the polymer layer 245, as shown in FIG. In addition, in the form of the bump, it may be a pattern similar to the stud bumps described above, and will not be described again here. The C. metal circuit is used as a power bus or ground bus of the wafer structure. The circuit line of the wafer structure according to the first embodiment of the present invention can be combined with the thin film circuit layer. Huidian 'connection' as the power busbar of the wafer structure 2〇5; at the same time, through the bump 28G can also be transferred to the external power_piece (not (four)) power supply convergence 1284385 15625twf.doc/006 electric connection 'the outside world The circuit components are, for example, substrates or a different conductor wafer. Alternatively, the metal line 250 can also be electrically connected to the film ground bus bar 235 of the thin film circuit layer as the wafer structure 2〇5. <The grounding busbar; at the same time, the through bump 280 can also be electrically connected to the grounding busbar of an external circuit component (not shown), such as a substrate or another semiconductor wafer. It should be noted that the metal line 250 may be formed on the protective layer 240 in direct contact, as shown in FIG. 56; or, the polymer layer 245 may be formed on the protective layer 240 first, and then the metal line 250 is formed in the polymerization. On the object layer 245, as shown in FIG. Further, in the form of the bump, it may be a pattern similar to the stud bump described herein, and will not be described again. D. Metal circuit as signal transmission, power bus or ground bus of external circuit components. FIG. 58 and FIG. 59 are schematic cross-sectional views showing the structure of the wafer according to the first embodiment of the present invention, wherein the metal lines 250 are not connected. The top film layer 236. When the metal line 250 is used for signal transmission of an external circuit component (not shown), the external circuit component can output an electronic signal, transmit to the metal line 250 via the bump 280a, and then transmit to the external circuit via the bump 280b. member. In addition, the metal line 250 can also serve as a power bus or ground bus for the external circuit components. It should be noted that the metal line 250 may be formed on the protective layer 240 in direct contact, as shown in FIG. 58; or, the polymer layer 245 may be formed on the protective layer 240 first, and then the metal line 250 is formed in the polymerization. On the object layer 245, as shown in FIG. Further, in the form of the bump, it may be a pattern similar to the above-described columnar bump, and will not be described again. Second Embodiment of Wafer Structure Manufacturing Method FIGS. 60 to 66 illustrate a semiconductor wafer on a semiconductor wafer in accordance with a second embodiment of the present invention 29 1284385 15625 twf. Doc/006 A schematic diagram of the cross section of metal lines and bumps. Referring to FIG. 60, a semiconductor wafer 200 is first provided. The semiconductor wafer 200 includes a semiconductor substrate 210, a plurality of thin film dielectric layers 222, 224, and 226, a plurality of thin film circuit layers 232 V234 and 236, and a protective layer 240. The detailed structure thereof is described in detail in the first point of the first embodiment, and will not be described again. Referring to FIG. 60, after the semiconductor wafer 200 is provided, the bottom metal layer 250 may be formed by sputtering on the protective layer 240 of the semiconductor wafer and the thin film wiring layer 236 exposed outside the opening 242 of the protective layer 240. At points 236a, 236b, in the process, for example, including first sputtering an adhesion/barrier layer on the protective layer 240 of the semiconductor wafer 200 and on the thin film wiring layer 236 exposed outside the opening 242 of the protective layer 240, and then The splattered seed layer is on the adhesion/barrier layer, and the material of the adhesion/barrier layer and the seed layer is described later, and will not be described here. Next, a photoresist layer 260 can be formed over the bottom metal layer 252, and the photoresist layer 260 has openings 262 that expose the bottom metal layer 252, as shown in FIG. Then, the metal layer 254 can be formed on the bottom metal layer 252 exposed by the opening 262 of the photoresist layer 26 by electroplating, as shown in FIG. 61, wherein the metal layer 254 is in the form of a line pattern, metal. Layer 254 is electrically connected to contact 236a of thin film wiring layer 236 and extends over protective layer 240. Defining a plane, the plane 1 is substantially parallel to the active surface 214 of the semiconductor substrate 210, wherein the metal layer 254 of the line pattern is projected onto the plane 1000 such that the extent is greater than 5 GG microns, or such as greater than _micron, or such as greater than 1200 microns; the area of the line pattern 254a of the metal layer 254 projected onto the plane 1〇00 is, for example, greater than 30, _ square microns, or such as greater than 8 〇, _ square microns, or such as greater than 15 〇, 〇〇〇 square micron. Next, the photoresist layer 260 can be removed to expose the bottom metal layer 252, as shown in FIG. Thereafter, a photoresist layer 27 may be formed on the bottom metal layer and on the metal layer 254. The photoresist layer 270 has an opening 272 exposed to the film line 30 1284385 15625 twf. Doc/006 The bottom metal layer 252 on the contact 236b of the road layer 236, as shown in FIG. Next, a metal pattern 282 of bump patterns can be formed by electroplating on the bottom metal layer 252 exposed by the opening 272 of the photoresist layer 270, as shown in FIG. It is noted that the area of the metal layer 282 of each bump pattern projected onto the plane 1000 is, for example, less than 30,000 square microns, or such as less than 20,000 square microns, or such as less than 15,000 square meters. Next, the photoresist layer 270 can be removed to expose the bottom metal layer 252 as indicated by circle 65. Then, the seed layer of the bottom metal layer 252 not covered by the full layer 254, 282 is sequentially removed by using the metal layer 254 of the circuit pattern and the metal layer 282 of the bump pattern as the stencil cover' The adhesion/barrier layer leaves only the bottom metal layer 252 under the metal layers 254, 282, as shown in FIG. When the metal layer 282 of the bump pattern includes a solder layer, a subsequent step of reflowing may be performed such that the top surface of the metal layer 282 may form a smooth surface (not shown). Thereafter, a single-cut step can be performed in which the dicing blade cuts the semiconductor wafer 200 along the scribe-line of the semiconductor wafer 200, thereby forming a plurality of individual wafer structures 205. In the above process, the metal line 250 is formed by a bottom metal layer 252 formed by a sputtering process and a metal layer 254 formed by an electroplating process, and the bump 280 is a bottom metal layer 252 formed by a sputtering process and plating. The metal layer 282 formed by the process is formed. Since the metal lines 250 and the bottom metal layer 252 of the bumps 280 are formed by the same sputtering step, the steps of forming the metal lines 250 and the bumps 280 can be simplified. 2. Structure of Metal Circuit Referring to Fig. 66, the metal line 250 is composed of a bottom metal layer 252 formed by a sputtering process and a metal layer 254 formed by a plating process, and the detailed structure is as follows. 31 1284385 15625twf. Doc/006 The first metal layer structure of the Α·金羼 line is referred to 圏67, and the section of the first metal layer structure of the metal line of _Jianben_second solid compensation is shown in (4), in which the metal in the shape of the wire At 252, for example, the adhesion/barrier layer 252a is formed by a sputtering process, and then a seed layer 252b of gold or copper is formed on the adhesion/barrier layer 252a by sputtering, wherein the adhesion/barrier is formed. The material of the layer 252a is, for example, a complex, a titanium, a titanium tungsten alloy, a titanium nitride compound, a button or a group nitrogen compound, or the adhesion/barrier layer 252a may be formed by sequentially depositing a chromium layer and a copper alloy layer. The chrome-copper alloy layer is located on the chrome layer. In forming the metal layer 254, for example, a gold layer having an axial thickness X greater than 丨 micron is used on the seed layer 252b of the bottom metal layer 252. B. Metal Structure of Second Metal Layer Referring to FIG. 68, a cross-sectional view of a second metal layer structure of a metal line in accordance with a second embodiment of the present invention is illustrated, in which, for example, when forming the bottom metal layer 252, The adhesion/barrier layer 252a is formed by a sputtering process, and then a copper or gold seed layer 252b is formed on the adhesion/barrier layer 252a by using a minus bond, wherein the material of the adhesion/barrier layer 252a is formed. For example, it is a chromium, titanium, titanium tungsten alloy, a titanium nitride compound, a ruthenium or a nitrogen compound, or the adhesion/barrier layer 252a may be formed by sequentially depositing a chromium layer and a chromium-copper alloy layer, wherein the chromium-copper alloy The layer is on the chrome layer. In forming the metal layer 254, a copper layer having a thickness greater than 丨 micron is formed on the seed layer 252b of the bottom metal layer 252, for example, by electroplating. A third metal layer structure of the C. metal line, reference numeral 69, which illustrates a cross-sectional view of a third metal layer structure of the metal line in accordance with the second embodiment of the present invention, wherein when the bottom metal layer 252 is formed, such as The adhesion/barrier layer 252a is formed by a sputtering process, and then a seed layer 252b made of copper or gold is formed by adhesion to the bonding layer / 32 1284385 15625 twf. Doc/006 on the barrier layer 252a, wherein the material of the adhesion/barrier layer 252a is, for example, chromium, titanium, tantalum tungsten alloy, titanium nitride compound, group or nitrogen compound, or the adhesion/barrier layer 252a may also be The chromium layer and the chromium-copper alloy layer are sequentially deposited, wherein the chromium-copper alloy layer is on the chromium layer. When the metal layer 254 is formed, for example, a copper layer 254 having a thickness of more than 1 micrometer is formed by electroplating to be known on the seed layer 2522b of the bottom metal layer 252, and then the recording layer 2543b is formed on the copper layer 2543a by electroplating. . Referring to FIG. 70, a cross-sectional view showing a fourth metal layer structure of a metal line according to a second embodiment of the present invention, wherein, when forming the bottom metal layer 252, for example, The adhesion/barrier layer 252a is formed by a sputtering process, and then a seed layer 252b made of copper or gold is formed on the adhesion/barrier layer 252a by sputtering, wherein the material of the adhesion/barrier layer 252a is The system is a chromium, titanium, titanium alloy, a titanium nitride compound, a group or a niobium nitrogen compound, or the adhesion/barrier layer 252a may be formed by sequentially depositing a chromium layer and a chromium-copper alloy layer, wherein the chromium-copper alloy layer The base is on the chrome layer. When the gold-plated layer 254 is formed, for example, a copper layer 2544a having a thickness greater than 1 micrometer is first formed on the seed layer 2522b of the bottom metal layer 252 by electroplating, and then a recording layer 2544b is formed on the copper layer 2544a by electroplating. Then, a gold layer 2544c is formed on the nickel layer 2544b by electroplating. 3. Structure of the bumps Referring to Fig. 66, the bumps 280 are composed of a bottom metal layer 252 formed by a sputtering process and a metal layer 282 formed by a plating process, and the detailed structure is as follows.第·First bump structure v. Referring to FIG. 71', a cross-sectional view of a first bump structure not according to the second embodiment of the present invention is shown, wherein when the bottom metal layer 252 is formed, for example, 33 1284385 l5625twf. Doc/006 firstly forms an adhesion/barrier layer 252a by a sputtering process, and then forms a seed layer 252b of a gold or copper material on the adhesion/barrier layer 252a by means of a metallurgical method. The material of the layer 252a is, for example, a complex, a chain, a zihe alloy, a titanium nitride compound, a group or a ruthenium nitride compound, or the adhesion/resistance layer 252a may also be formed by sequentially depositing a chrome layer and a chrome-copper alloy layer. The chromium steel alloy layer is located on the chromium layer. When the metal layer 282 of the bump pattern is formed, for example, a gold layer having a thickness y of more than 3 μm is formed on the seed layer 252b of the bottom metal layer 252 by means of an electric bond. In practical applications, bumps 280 as shown in Figure η can be formed on semiconductor wafer 200 in conjunction with routing lines 250 having metal layers as shown in Figures 67-70. B. Second bump structure Referring to FIG. 72, a cross-sectional view of a second bump structure according to a second embodiment of the present invention is shown. Forming an adhesion/barrier layer 252a, and then forming a seed layer 252b made of copper or gold on the adhesion/barrier layer 252a by means of sputtering. The material of the adhesion/barrier layer 252a is, for example, chromium, titanium, The titanium tungsten alloy, the titanium nitride compound, the niobium or the nitrogen compound, or the adhesion/barrier layer 252a may also be formed by sequentially depositing a chromium layer and a chromium-copper alloy layer, wherein the chromium steel alloy layer is on the chromium layer. . When the metal layer 282 of the bump pattern is formed, for example, the copper layer 2822a is first formed on the seed layer 252b of the bottom metal layer 252 by electroplating, and then the nickel layer 282 is formed on the steel layer 2822a by electroplating. Then, a solder layer 2822c having a thickness y greater than 3 μm is formed on the nickel layer 2822b by electroplating, and the material of the solder layer 2822c is, for example, tin-lead alloy, tin, tin-silver alloy or tin-silver-copper alloy. In practical applications, the bump 280 as shown in Fig. 72 can be formed on the semiconductor wafer 2 with a metal wiring 250 having a metal layer structure as shown in Figs. 67 to 7B. 4. Method of making metal lines and columnar bumps of the first form 34 1284385 15625twf. Doc/006 In addition, the process of the present invention can also be combined with the process of fabricating stud bumps, as shown in FIGS. 73-77, which illustrate the fabrication of metal lines on semi-guide wafers in accordance with a second embodiment of the present invention. And a cross-sectional view of the first form of the columnar tenon, wherein the figure to Fig. 73 are the steps following the Fig. 62. After the metal pattern 254 of the line pattern is completed, as shown in FIG. 62, a photoresist layer 270 may be formed on the bottom metal layer 252 and the metal layer 254. The photoresist layer 270 has an opening 272 to expose the film line. The bottom metal layer 252 on the contact 236b of the layer 236, as shown in FIG. 73, wherein the bottom metal layer 252 has a structure such as the bottom of the adhesion/barrier layer 252a and the seed layer 252b as shown in FIGS. 67-72. The structure of the metal layer 252 will not be described here. Referring to FIG. 73, the metal pillars 292 and the solder layer 296 may be sequentially formed by electroplating on the bottom metal layer 252 exposed by the opening 272 of the photoresist layer 270, wherein when the metal pillars 292 are formed, for example, The columnar metal layer 294 and the anti-disintegration layer 295 are sequentially formed by the Lithium plating process. When the columnar metal layer 294 is formed, for example, a copper layer having a thickness of 8 μm to 100 μm is formed on the bottom metal layer 252 by electroplating, or is formed to have a thickness of 8 μm to 1 by, for example, electroplating. The tin-micron high-capacity tin boat alloy layer is on the bottom metal layer 252; when the anti-crack layer 295 is formed, for example, a nickel layer having a thickness of 1 μm to 1 μm is formed by electroplating. On the metal layer 294. In this embodiment, the material of the solder layer 296 is, for example, tin-lead alloy, tin, tin-silver alloy or tin-silver-copper alloy. The solder layer 296 can be directly contacted on the recording layer 295 of the metal pillar 292, and the bit In the opening 272 of the photoresist layer 270. Next, the photoresist layer 270 can be removed to expose the bottom metal layer 252 as shown in FIG. Next, the pillar metal layer 294 may be etched from the sidewall of the pillar metal layer 294 such that the area projected onto the plane 1000 by the pillar metal layer 294 may be smaller than the collapse prevention layer 295 or the solder layer 296 projected onto the plane i〇〇Q Face 35 1284385 15625twf. Doc/006 is accumulated, and the edge of the lower surface of the anti-disintegration layer 295 can be exposed as shown in Fig. 75. Then, the metal layer 254 and the columnar metal layer 294 are used as etching walls, and the seed layer and the adhesion/barrier of the bottom metal layer 252 not covered by the metal layer 254 and the metal layer 294 are sequentially removed by etching. The layer leaves only the bottom metal layer 252 under the metal layer 254 and under the columnar metal layer 294, as shown in FIG. Next, a step of reflowing can be performed so that the top surface of the solder layer 296 can form a smooth surface, as shown in Fig. 77, and the process of fabricating the bumps 290 is completed. As described above, the bump 290 may include a metal post 292 and a solder layer 296. In the present embodiment, the metal post 292 is composed of, for example, a bottom metal layer 252, a columnar metal layer 294, and an anti-crash layer 295. Referring to FIG. 77, in the present embodiment, since the lateral dimension of the columnar metal layer 294 of the metal post 292 is smaller than the lateral dimension of the anti-disintegration layer 295, it is melted by the solder layer 296 when the reflow process is performed. The solder does not flow down along the sidewall of the columnar metal layer 294, so that the occurrence of the solder layer 296 falling apart can be avoided. Thereafter, a single-cut step can be performed in which the dicing blade cuts the semiconductor wafer 2 沿着 along the scribe-iine of the semiconductor wafer 200, thereby forming a plurality of individual wafer structures 205. In the above process, the metal line 250 is formed by a bottom metal layer 252 formed by a sputtering process and a metal layer 254 formed by an electroplating process. The columnar bump 290 is a bottom metal layer 252 formed by a sputtering process. And a columnar metal layer 282, a collapse prevention layer 294, and a solder layer 296 formed by an electroplating process. Since the metal lines 250 and the bottom metal layer 252 of the columnar bumps 290 are formed by the same plating step, the steps of forming the metal lines 25A and the columnar bumps 290 can be simplified. 5. Method of Fabricating Metal Lines and Second Form of Columnar Bumps FIGS. 78-82 illustrate a semiconductor wafer 36 1284385 15625 twf in accordance with a second embodiment of the present invention. A cross-sectional view of the metal line and the second form of the columnar bumps is made on doc/006, wherein Figs. 78 to 82 are the steps following Fig. 62. After the metal pattern 254 of the line pattern is completed, as shown by 阖62, a photoresist layer 270 may be formed on the bottom metal layer 252 and the metal layer 254. The photoresist layer 270 has an opening 272 to expose the film line. The bottom metal layer 252' on the contact 236V of the layer 236 is as shown in FIG. 78. The structure of the bottom metal layer 252 is as shown in FIG. 67 to FIG. 72 including the bottom of the adhesion/barrier 252a and the seed layer 252b. The structure of the metal layer 252 will not be described here. Continuing to refer to FIG. 78, a metal pillar 292 may be formed by electroplating on the bottom gold layer 252 exposed by the opening 272 of the photoresist layer 270, such as by electroplating. The method sequentially forms the columnar metal layer 294 and the anti-disruption layer 295 on the bottom metal layer 252 exposed by the opening 272 of the photoresist layer 270; when forming the columnar metal layer 294, for example, the thickness is formed by electroplating. A copper layer of between 8 micrometers and 1 micrometers is on the bottom metal layer 252 or, for example, a tin-lead alloy layer having a high lead content of 8 micrometers to 100 micrometers in thickness is formed by electroplating in the bottom metal layer 252. Above, when the anti-cracking layer 295 is formed, for example, a nickel layer having a thickness of 1 μm to 10 μm is formed on the columnar metal layer 294 by electroplating. Next, a photoresist layer 275 is formed on the photoresist layer 270 and the anti-crack layer 295: as shown in FIG. 79, wherein the photoresist layer 2 has an opening 276 exposing the anti-crash layer 295, it is noted that The lateral dimension of the opening 276 of the photoresist layer 275 is less than the lateral dimension of the columnar metal layer 294 and the anti-aggression layer 295. Then, a solder layer 296 can be formed on the anti-crash layer 295 exposed by the opening 276 of the photoresist layer 275, as shown in FIG. 8A, wherein 2% of the solder layer is made of tin alloy, kick, tin silver. Alloy Mithril copper alloy, etc. Next, the photoresist layers 275, 270 can be sequentially removed to expose the bottom metal layer 252' as shown in FIG. Next, the metal layer 254 and the columnar metal layer 37 1284385 15625twf. Doc/006 294 is used as an etching mask wall to sequentially remove the seed layer and the adhesion/barrier layer of the bottom metal layer 252 not covered by the metal layer 254 and the columnar metal layer 294 by etching, leaving only the metal layer 254. The bottom metal layer 252 under the lower and columnar metal layer 294 is as shown in FIG. 82, and the process of fabricating the bump 291 is completed. As described above, the stud bump 291 may include a metal post 292 and a solder layer 296. In the present embodiment, the metal post 292 is composed of, for example, a bottom metal layer 252, a columnar metal layer 294, and an anti-crash layer 295. Thereafter, a single-cut step can be performed in which the dicing blade cuts the semiconductor wafer 200 along the scribe-line of the semiconductor wafer 200, thereby forming a plurality of individual wafer structures 205. Referring to FIG. 82, when the bonding of the wafer structure 205 and a substrate (not shown) is performed, since the lateral dimension of the solder layer 296 of the stud bumps 291 is smaller than the lateral dimension of the metal pillars 292, even in the soldering of the substrate. In the case where the opening of the cap layer is small, the solder layer 296 of the stud bump 291 can be easily inserted into the opening of the solder mask layer of the substrate and exposed to the opening of the solder mask layer of the substrate. Point connection. In the above process, the metal line 250 is formed by a bottom metal layer 252 formed by a sputtering process and a metal layer 254 formed by an electroplating process, and the stud bump 291 is a bottom metal layer 252 formed by a sputtering process. And a columnar metal layer 282, a collapse prevention layer 294, and a solder layer 296 formed by an electroplating process. Since the metal lines 250 and the bottom metal layer 252 of the stud bumps 291 are formed by the same sputtering step, the steps of forming the metal lines 250 and the stud bumps 291 can be simplified. 6. Thickness Relationship Between Bump, Metal Line, and Polymer Layer In the second embodiment, as shown in FIGS. 66, 77, and 82, the metal line 250 is exposed and directly formed in the protective layer 240. The metal line 250 can be connected to the film line 38 1284385 15625twf exposed outside the opening 242 of the protective layer 240. Doc/006 Contact at layer 236. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It is to be noted that the thicknesses bl, b2, b3 of the bumps 280, 290, 291 are greater than the thickness c of the metal line 250. However, the application of the present invention is not limited to that. Referring to FIG. 83, the thickness b4 of the bump 280 may also be equal to the thickness c of the metal line 250; and so on, when the aforementioned columnar bumps 290, 291 replace the bumps. At 280, the thickness of the stud bumps 290, 291 may also be equal to the thickness c of the metal trace 250. In FIGS. 84 and 85, the metal trace 250 is formed in direct contact with the protective layer 240, a polymer layer 245. The metal line 250 is formed on the metal line 250 and the protective layer 240. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It should be noted that in FIG. 84, the thickness b5 of the bump 280 is greater than the total thickness (c+d) of the metal line 250 and the polymer layer 245, and so on, when the aforementioned stud bump 290, When the bump 280 is replaced by the 291, the thickness of the stud bumps 290, 291 may be greater than the total thickness of the metal line 250 and the polymer layer 245. In FIG. 85, the thickness b6 of the bump 280 is smaller than the total thickness (c+d) of the metal line 250 and the polymer layer 245, and so on, when the aforementioned stud bumps 290, 291 replace the bump 280. The thickness of the stud bumps 290, 291 may also be less than the total thickness of the metal line 250 and the polymer layer 245. In FIGS. 86, 87, and 88, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242 of the protective layer 240 and expose the film of the top layer. The junction of the circuit layer 236. A metal line 250 is formed on the polymer layer 247 and is connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. The bump 280 is formed in direct contact with the opening of the protective layer 240 242 39 1284385 15625twf. Doc/006 is exposed on the contact of the film circuit layer 236. It is to be noted that, in FIG. 86, the thickness b7 of the bump 280 is greater than the total thickness (c+e) of the metal line 250 and the polymer layer 247, and so on, when the aforementioned stud bump 290, 291 When the bumps 280 are replaced, the thickness of the columnar bumps 290, 291 may also be greater than the total thickness of the metal lines 250 and the polymer layer 247. In FIG. 87, the thickness b8 of the bump 280 is substantially the same as the total thickness (c+e) of the metal line 250 and the polymer layer 247, and so on, when the aforementioned pillar-shaped bumps 290, 291 are replaced. In the case of the bump 280, the thickness of the stud bumps 290, 291 may also be equal to the total thickness of the metal line 250 and the polymer layer 247. In FIG. 88, the thickness b9 of the bump 280 is greater than the total thickness (c+e) of the metal line 250 and the polymer layer 247, and so on, when the aforementioned stud bumps 290, 291 replace the bump 280. The thickness of the stud bumps 290, 291 may also be greater than the total thickness of the metal tantalum line 250 and the polymer layer 247. In FIGS. 89 and 90, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242 of the protective layer 240 and expose the top film layer 236. The junction. A metal line 250 is formed on the polymer layer 247 and is connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. Polymer layer 245 is located on metal line 250 and on polymer 247 to protect metal line 250. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It is to be noted that, in FIG. 89, the thickness M0 of the bump 280 is smaller than the total thickness (c+d+e) of the metal line 250 and the polymer layers 245, 247, and so on, when the foregoing columnar shape When the bumps 290, 291 are substituted for the bumps 280, the thickness of the stud bumps 290, 291 may also be less than the total thickness of the metal lines 250 and the polymer layers 245, 247; in Fig. 90, the thickness of the bumps 280 The bll is greater than the total thickness of the metal line 250 and the polymer layers 245, 247 plus 1284385 15625 twf. Doc/006 (c+d+e) ', and so on, when the above-mentioned columnar bumps 290, 291 replace the bumps 280, the thickness of the columnar bumps 290, 291 may also be smaller than the metal line 25 and the polymerization The total thickness of the layers 245, 247 is added. In FIG. 91 and FIG. 92, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 substantially aligned with the openings 242 of the protective layer 24 and exposes the thin film circuit layer of the top layer. 236 contacts. A metal line 250 is formed on the polymer layer 247 and is connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. The bumps 280 are formed in direct contact with the openings of the protective layer 240 and the contacts of the thin film wiring layer 236 exposed by the openings 248 of the polymer layer 247. It should be noted that, in FIG. 91, the thickness M2 of the protrusion 280 is the same as the thickness c of the metal line 250, and so on. When the above-mentioned columnar bumps 290, 291 replace the bump 280, The thickness of the protruding protrusions 290, 291 may also be the same as the total thickness of the metal line 250 and the polymer layers 245, 247; in Fig. 92, the protrusion 280 protrudes from the outer thickness bl3 Greater than the thickness c of the metal line 250, and so on, when the aforementioned stud bumps 290, 291 replace the bumps 280, the thickness of the stud bumps 290, 291 protruding outward may also be greater than the metal line 250 and the polymerization. The total thickness of the layers 245, 247 is added. In FIGS. 93 and 94, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242 of the protective layer 240 and expose the top film layer 236. The junction. A metal line 250 is formed over the polymer layer 247 and may be connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. Polymer layer 245 is located on metal line 250 and on polymer layer 247 to protect metal line 250. The bump 280 is formed in direct contact with the opening 242 of the protective layer 240 and the opening 248 of the polymer layer 247 to expose 1284385 15625 twf. The contact of the film circuit layer 236 of doc/006. It is to be noted that, in FIG. 93, the thickness M4 of the protrusion 280 is smaller than the total thickness (c+d) of the metal line 250 and the polymer layer 245, and so on, when the foregoing columnar shape When the protrusions 290 and 291 are substituted for the bumps 280, the thickness of the columnar bumps 290 and 291 protruding from the outside may be the same as the total thickness of the metal lines 25 and the polymer layer 245; in FIG. The thickness M5 of the block 280 is greater than the total thickness (c+d) of the metal line 250 and the polymer layer 245, and so on, when the aforementioned columnar bumps 290, 291 replace the bump 280, The thickness of the stud bumps 290, 201 protruding outward may also be greater than the total thickness of the metal line 250 and the polymer layer 245. In the above embodiments of FIG. 84 to FIG. 94, the materials of the polymer layers 245 and 247 are, for example, polyimide, pi, benzocydobutene (BCB), and polyarylene ether (parylene). ), a porous dielectric material or an elastomer, etc., and the thicknesses d, e of the polymer layers 245, 247 are, for example, greater than 1 micron. 7. The function of the metal circuit A. The metal circuit is used for internal signal transmission of the wafer structure. Referring to FIG. 66, FIG. 77, FIG. 82 and FIG. 83 to FIG. 94, the metal line 250 is used as the internal signal transmission of the wafer structure 205. One of the electronic components 212 (such as the electronic component 212a) is adapted to output an electronic signal that is transmitted to the metal line 250 via the thin film circuit layers 232, 234, 236 and through the protective layer 240. Then, it passes through the protective layer 24A and is transferred to at least one of the other electronic components 212 (such as the electronic component 212b) via the thin film wiring layers 236, 234, 232. B. Metal circuit as a power bus or ground bus of a wafer structure. FIG. 95 to FIG. 107 are schematic cross-sectional views of a wafer structure according to a second embodiment of the present invention, in which a metal line 250 is used. It can be electrically connected to the thin film power supply bus bar 235 of the thin film circuit layer, and can be electrically connected to the power supply voltage source as the power supply of the wafer structure 2〇5. Alternatively, the metal circuit 25 can also be connected to the thin film circuit layer. The film ground bus bar 235 is electrically connected, and is used as a ground bus bar of the wafer structure 2〇5, and can be electrically connected to a ground voltage source. Referring to FIG. 95, the metal line 250 is exposed and directly contacted on the layer 240, and the metal line 250 can be connected to the contact of the film line layer 236 exposed outside the opening 242 of the protective layer. The bumps 28 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It is noted that the thickness bl6 of the bumps 280 is greater than the thickness c of the gold wire 250. And so on, when the above-mentioned columnar bumps 29〇, 291 replace the bumps 280, the thickness of the columnar bumps 290, 291 may also be equal to the thickness c of the metal line 250. However, the application of the present invention is not For this reason, referring to FIG. 96, the thickness b1 of the bump 280 may also be equal to the thickness c of the metal line 250; and so on, when the above-mentioned columnar bumps 29〇, 291 replace the bumps 280, the columnar bumps The thickness of 290, 291 may also be equal to the thickness e of the metal line 250. In FIGS. 97 and 98, the metal line 250 is formed in direct contact with the protective layer 240, and a polymer layer 245 is formed on the metal line 250. And repairing the protective layer 240 to protect the metal line 250. The bump 280 is formed in direct contact with the contact of the thin film wiring layer 236 exposed by the opening 242 of the protective layer 240. It is noted that in Fig. 97, the thickness bl8 of the bump 280 is larger than the metal wiring. 250 and the total thickness (c+d) of the polymer layer 245, and so on, when the above-mentioned columnar bumps 290, 291 replace the bumps 280, the thickness of the columnar bumps 290, 291 may also be greater than The total thickness of metal line 250 and polymer layer 245 is added. In Figure 98, the thickness M9 of bump 280 is less than the total thickness (c+d) of metal line 250 and polymer layer 245, and so on, 43 1284385 15625twf. Doc/006 When the aforementioned stud bumps 290, 291 replace the bumps 280, the thickness of the stud bumps 290, 291 may also be less than the total thickness of the metal lines 25" and the polymer layer 245. In FIG. 99, FIG. 100 and FIG. 101, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 substantially aligned with the openings 242 of the protective layer 240 and exposing the film of the top layer. The junction of the line Zhan 236. A metal line 250 is formed on the polymer layer 247 and is connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It is to be noted that, in FIG. 99, the thickness b20 of the bump 280 is greater than the total thickness (c+e) of the metal line 250 and the polymer layer 247, and so on, when the aforementioned stud bump 290, When the bump 280 is replaced by the 291, the thickness of the stud bumps 290, 291 may be greater than the total thickness of the metal line 250 and the polymer layer 247. In FIG. 100, the thickness b21 of the bump 280 is substantially the same as the total thickness (c+e) of the metal line 250 and the polymer layer 247, and so on, when the aforementioned stud bumps 290, 291 are replaced. In the case of the bump 280, the thickness of the stud bumps 290, 291 may also be equal to the total thickness of the metal line 250 and the polymer layer 247. In FIG. 101, the thickness b22 of the bump 280 is greater than the total thickness (c+e) of the metal line 25A and the polymer layer 247, and so on, when the aforementioned columnar bumps 290, 291 replace the bumps. At 280, the thickness of the stud bumps 290, 291 may also be greater than the total thickness of the metal line 250 and the polymer layer 247. In FIGS. 102 and 103, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 substantially aligned with the openings 242 of the protective layer 24 and exposes the thin film circuit layer of the top layer. 236 contacts. Metal line 250 is formed on polymer layer 247 and is connected to film line layer 236 1284385 15625 twf via opening 248 of polymer layer 247 and opening 242 of protective layer 240. The junction of doc/006. Polymer layer 245 is located on metal line 250 and on polymer layer 247 to protect metal line 250. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. . It is worth noting that in FIG. 102, the thickness b23 of the bump 280 is smaller than the total thickness (c+d+e) of the metal line 250 and the polymer layers 245, 247, and so on, when the foregoing When the stud bumps 290, 291 are substituted for the bumps 280, the thickness of the stud bumps 290, 291 may also be less than the total thickness of the metal lines 250 and the polymer layers 245, 247; in FIG. The thickness b24 of the block 280 is greater than the total thickness (c+d+e) of the metal line 250 and the polymer layers 245, 247, and so on. When the aforementioned stud bumps 290, 291 replace the bumps 280, The thickness of the stud bumps 290, 291 may also be less than the total thickness of the metal lines 250 and the polymer layers 245, 247. In FIGS. 104 and 105, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242 of the protective layer 240 and expose the top film layer 236. contact. A metal line 250 is formed on the polymer layer 247 and is connected to the defect of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. The bumps 280 are formed in direct contact with the openings of the protective layer 240 and the contacts of the thin film wiring layer 236 exposed by the openings 248 of the polymer layer 247. It should be noted that, in FIG. 104, the thickness b25 of the protrusion 280 is the same as the thickness c of the metal line 250, and so on. When the aforementioned columnar bumps 290, 291 replace the bump 280, The thickness of the protruding protrusions 290, 291 may also be the same as the total thickness of the metal line 250 and the polymer layers 245, 247; in Fig. 105, the protrusion 280 protrudes from the outer thickness b26 Greater than the thickness c of the metal line 250, and so on, when the aforementioned stud bumps 290, 291 replace the bumps 280, the thickness of the stud bumps 290, 291 protruding outward may also be greater than the metal line 250 and the polymerization. Object layer 245, 45 1284385 15625twf. The total thickness added by doc/006 247. In FIGS. 106 and 107, the polymer layer 247 is located on the protective cover 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242' of the protective layer 240 and expose the top layer of the thin circuit layer. 236 contacts. A metal line 250 is formed over the polymer layer 247 and may be connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. Polymer layer 245 is located on metal line 250 and on polymer layer 247 to protect metal line 250. Bumps 280 are formed in direct contact with the contacts of opening 242 of protective layer 240 and film wiring layer 236 exposed by openings 248 of polymer layer 247. It should be noted that in FIG. 1〇6, the thickness b27 of the protrusion 280 is smaller than the total thickness (c+d) of the metal line 250 and the polymer layer 245, and so on, when the foregoing When the stud bumps 29〇, 291 are substituted for the bumps 280, the thickness of the stud bumps 290, 291 protruding outward may also be the same as the total thickness of the metal line 250 and the polymer layer 245; The thickness b28 of the protrusion 280 is greater than the total thickness (c+d) of the metal line 250 and the polymer layer 245, and so on, when the aforementioned columnar bumps 290, 291 replace the bump 280. The thickness of the stud bumps 29A, 291 may also be greater than the total thickness of the metal line 250 and the polymer layer 245. In the above embodiments of FIGS. 95 to 107, the materials of the polymer layers 245, 247 are, for example, polyimide, PI, benzocyclobutene (BCB), polyarylene ether (parylene). ), a porous dielectric material or an elastic invitation, and the thicknesses d, e of the polymer layers 245, 247 are, for example, greater than 1 micron. The C. metal circuit is used as a signal transmission line, a power bus or a ground bus, wherein the metal circuit is electrically connected to the bump by using a thin film circuit layer of the top layer. Referring to FIG. 108 to FIG. 121, it is shown in accordance with the present invention. The crystal of the second embodiment 46 1284385 15625twf. Doc/006 is a schematic cross-sectional view of a sheet structure in which a metal line 250 is connected to a bump 280 by a thin film wiring layer 236 of a top layer, such as a signal transmission line, a power bus, or a bus bar. The metal line 250 is located on the saw layer 240 and is electrically connected to the contact 237a of the thin film wiring layer 236 via the opening 242 of the protective layer 240. The bump 280 is tied to the contact 237b of the thin film wiring layer 236 exposed by the opening 242 of the protective layer 240. The thin film circuit layer 236 has a connection line 237 connecting the contacts 237a, 237b so that the metal line 250 can be electrically connected to the bump 280 through the connection line 237 and the contacts 237a, 237b. Referring to FIG. 109, a top view of the connection line 237 and the contacts 237a, 237b is shown. In the latter case, the extension distance s of the connection line 237 is, for example, less than 500 microns. Referring to FIG. 108 to FIG. 121, when the metal line 250 is used as a signal transmission line, the electronic signal outputted by one of the electronic components 212 (for example, the electronic component 212a) can be worn through the thin film circuit layers 232, 234, and 236. After passing through the protective layer 240, it is transferred to the metal line 250, then passes through the protective layer 240, and is transferred to the bump 260 via the connecting line 237 of the thin film wiring layer 236. Alternatively, the electronic signal received by the bump 260 may be transmitted through the protective layer 240 to the connection line 237 of the thin film line 236, then through the protective layer 240 to the metal line 250, and then through the protective layer 240, and At least one of the electronic components 212 (such as the electronic component 212a) is transferred via the thin film wiring layers 236, 234, 232. When the metal line 250 is used as a power bus, for example, the metal line 250 can be connected to the substrate, the tape, the film, or the glass substrate via the connecting line 237 of the thin film wiring layer 236 and the bump 280. end. When the metal circuit layer 250 is used as a ground bus bar, for example, the metal circuit layer 250 can be connected to the substrate, the tape, the film, or the glass substrate via the connecting line 237 of the thin film wiring layer 236 and the bump 280. Ground terminal. Referring to Figure 108, the metal line 250 is exposed and directly in contact with 47 1284385 15625 twf. The doc/006 is formed on the protective layer 240, and the metal wiring 250 may be connected to the contact of the thin film wiring layer 236 exposed outside the opening 242 of the protective layer 240. The ridge 280 is formed in direct contact with the contact of the film wiring layer 236 exposed by the opening 242 of the protective layer 240. It should be noted that the thickness b29 of the bump 280 is greater than the thickness c of the metal line 250; and so on, when the above-mentioned columnar bumps 2 such as 291 replace the bumps 280, the ridges of the columnar bumps 290, 291 The degree may also be respected by the thickness c of the metal line 250. However, the application of the present invention is not limited thereto. Referring to FIG. 110, the thickness b30 of the bump 280 may also be equal to the thickness c of the metal line 250; and so on, when the aforementioned columnar bumps 290, 291 replace the bumps. At 280, the thickness of the stud bumps 290, 291 may also be equal to the thickness of the metal line 250. . In Figs. 111 and 112, metal lines 250 are formed in contact with each other on the protective layer 240, and may be connected to the contacts of the thin film wiring layer 236 exposed outside the opening 242 of the protective layer 240. Polymer layer 245 is formed over metal line 250 and protective layer 240 to protect metal line 250. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It should be noted that in the figure hi, the thickness b31 of the bump 280 is greater than the total thickness (c+d) of the metal line 250 and the polymer layer 245, and so on, when the aforementioned columnar bump 290, When the 291 is substituted for the bump 280, the thickness of the stud bumps 290, 291 may be greater than the total thickness of the metal line 250 and the polymer layer 245. In FIG. 112, the thickness b32 of the bump 280 is smaller than the total thickness (c+d) of the metal line 250 and the polymer layer 245, and so on, when the aforementioned stud bumps 290, 291 replace the bump 280. The thickness of the stud bumps 290, 291 may also be less than the total thickness of the metal line 250 and the polymer layer 245. In Fig. 113, Fig. 114 and Fig. 115, the polymer layer 247 is located on the protective layer 240, and the polymer layer 247 has a plurality of openings 248 which are substantially paired with 48 1284385 15625 twf. Doc/006 opens 242 of the protective layer 240 and exposes the contacts of the top film layer 236. A metal line 250 is formed on the polymer layer 247 and is connected to the junction of the film wiring layer 236 via the opening 248 of the polymer 247 and the opening 242 of the protective layer 240. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It is to be noted that, in FIG. 113, the thickness b33 of the bump 280 is greater than the total thickness (c+e) of the gold-line line 250 and the polymer layer 247, and so on, when the aforementioned columnar bump 290 When the 291 is substituted for the bump 280, the thickness of the columnar bumps 290, 291 may be greater than the total thickness of the metal line 250 and the polymer layer 247. In FIG. 114, the thickness b34 of the bump 280 is substantially the same as the total thickness (c+e) of the metal line 250 and the polymer layer 247, and so on, when the aforementioned stud bumps 290, 291 are replaced. In the case of the bump 280, the thickness of the stud bumps 290, 291 may also be equal to the total thickness of the metal line 250 and the polymer layer 247. In FIG. 115, the thickness b35 of the bump 280 is greater than the total thickness (c+e) of the gold-line line 250 and the polymer layer 247, and so on, when the aforementioned columnar bumps 290, 291 replace the bumps. At 280, the thickness of the stud bumps 290, 291 may also be greater than the total thickness of the metal line 250 and the polymer layer 247. In FIGS. 116 and 117, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242 of the protective layer 240 and expose the top film layer 236. The junction. A metal line 250 is formed on the polymer layer 247 and is connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. Polymer layer 245 is located on metal line 250 and on polymer layer 247 to protect metal line 250. The bumps 280 are formed directly on the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It should be noted that in FIG. 116, the thickness b36 of the bump 280 is smaller than that of the gold 49 1284385 15625 twf. Doc/006 ' . · ·-• . · The total thickness (c+d+e) of the line 250 and the polymer layers 245, 247, and so on, when the aforementioned columnar bumps 290, 291 replace the bump 280, the columnar bump 290 The thickness of 291 may also be less than the total thickness of the metal color circuit 250 and the polymer layers 245, 247; in FIG. 117, the thickness b37 of the bump 280 is greater than that of the metal line 250 and the polymer layers 245, 247. The total thickness (c+d+e), and so on, when the columnar bumps 29〇, 291 of the Wenzhou replace the bumps 280, the thickness of the columnar bumps 290, 291 may also be smaller than the metal line 250 and The total thickness of the polymer layers 245, 247 is added. In FIGS. 118 and 119, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 substantially aligned with the protective layer 240, the opening 242, and exposing the top film layer. 236 contacts. A metal line 250 is formed on the polymer layer 247 and is connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. The bumps 280 are formed in direct contact with the openings of the protective layer 240 and the contacts of the thin film wiring layer 236 exposed by the openings 248 of the polymer layer 247. It should be noted that, in FIG. 118, the thickness b38 of the protrusion 280 is the same as the thickness c of the metal line 250, and so on, when the above-mentioned columnar bumps 290, 291 replace the bump 280, The thickness of the protruding protrusions 290, 291 may also be the same as the total thickness of the metal line 250 and the polymer layers 245, 247; in Figure 119, the thickness of the protrusion 280 is convex outside the thickness b39 The thickness is greater than the thickness c of the metal line 250, and so on. When the aforementioned stud bumps 290, 291 replace the bumps 280, the thickness of the stud bumps 290, 291 may also be greater than the metal line 250 and The total thickness of the polymer layers 245, 247 is added. In FIGS. 120 and 121, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242 of the protective layer 240 and expose the top film layer 236. The junction. Metal 50 1284385 15625twf. The doc/006 line 250 is formed on the polymer layer 247 and may be connected to the junction of the film line 236 via the opening 248 between the opening 248 of the polymer layer 247 and the protective layer 240. Polymer layer 245 is located on gold ruthenium line 250 and polymer layer 247 to protect metal line 250. The bumps 280 are formed in direct contact with the contacts of the opening 242 of the protective layer 240 and the thin film wiring layer 236 exposed by the opening 248 of the polymer 247. It is worth noting that in the circumference U0, the thickness b40 of the protrusion 280 is smaller than the total thickness (c+d) of the metal line 250 and the polymer layer 245, and so on, when the foregoing columnar shape When the bumps 290, 291 are substituted for the bumps 280, the thickness of the stud bumps 290, 291 protruding outward may also be the same as the total thickness of the metal lines 250 and the polymer layer 245; in Figure 121, the bumps The outer thickness b41 is greater than the total thickness (c+d) of the metal line 250 and the polymer layer 245, and so on, when the aforementioned columnar bumps 290, 291 replace the bump 280, the column The thickness of the protrusions 290, 291 protruding outward may also be greater than the total thickness of the metal line 250 and the polymer layer 245. In the above embodiments of FIGS. 108 to 121, the materials of the polymer lips 245, 247 are, for example, polyimide (PI), benzocyclobutene 'BCB, and polystyrene. ), a porous dielectric material or an elastomer, etc., and the thicknesses d, e of the polymer layers 245, 247 are, for example, greater than 1 micron. D. Metal circuit as signal transmission, power bus or ground bus of external circuit components. FIG. 122 to FIG. 134 are schematic cross-sectional views showing a structure of a wafer according to a second embodiment of the present invention, wherein the metal circuit 250 is used as the outside. For signal transmission (not shown), power supply bus or ground bus, the metal line 250 is not connected to the top film circuit layer 236. In the electrical connection, for example, the external circuit component can be electrically connected to the metal circuit 25 by means of wire_bonding. 51 1284385 15625twf. Doc/006 is connected; alternatively, bumps or solder balls may be formed on the external circuit components for connecting the metal lines 250. When the metal line 250 is used for signal transmission of the external circuit components, the external circuit component can output an electronic signal to the metal line 250, after being transmitted through the metal line 250, and then transferred to the external circuit components. In addition, the gold exhibition line 250 can also serve as a power flow or ground bus of the external circuit components, and the metal line 250 can be connected to the power bus or the ground bus of the external circuit components. Referring to FIG. 122, the metal line 250 is exposed and directly contacted on the protective layer 240. The metal line 250 is not connected to the top film line layer 236. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It should be noted that the thickness b42 of the bump 280 is greater than the thickness c of the metal line 250; and so on, when the above-mentioned columnar bumps 290, 291 replace the bump 280, the thickness of the columnar bumps 290, 291 is also It may be equal to the thickness c of the metal line 250. However, the application of the present invention is not limited thereto. Referring to FIG. 123, the thickness b43 of the bump 280 may also be equal to the thickness c of the metal line 250; and so on, when the aforementioned columnar bumps 290, 291 replace the bumps. At 280, the thickness of the stud bumps 290, 291 may also be equal to the thickness c of the metal line 250. In Figs. 124 and 125, the metal wiring 250 is formed in direct contact with the protective layer 240, and the thin film wiring layer 236 of the top layer is not connected. A polymer layer 245 is formed over the metal line 250 and the protective layer 240 to protect the metal line 250. The polymer layer 245 has openings 246 that expose the metal lines 250 such that the openings 246 through the polymer layer 245, bumps, The wires formed by the solder balls or the wire bonding method can electrically connect the metal wires 250 and the external circuit components. It should be noted that in FIG. 124, the thickness b44 of the bump 280 is greater than the total thickness (c+d) of the metal line 250 and the polymer layer 245, and so on, when the aforementioned stud bump 290, When the 291 is substituted for the bump 280, the columnar bump 52 1284385 15625twf. The thickness of doc/006 290, 291 may also be greater than the total thickness of metal line 250 and polymer layer 245. In FIG. 125, the thickness b45 of the bump 280 is less than the total thickness (c+d) of the metal line 250 and the polymer layer 245, and so on, when the aforementioned stud bumps 290, 291 replace the bumps 280. The thickness of the stud bumps 290, 291 may also be less than the total thickness of the metal line 250 and the polymer layer 245. In Figures 126, 127, and 128, polymer layer 247 is disposed on protective layer 240, and metal line 250 is formed over polymer layer 247 without the top film layer 236 being attached. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It should be noted that in FIG. 126, the thickness b46 of the bump 280 is greater than the total thickness (c+e) of the metal line 250 and the polymer layer 247, and so on, when the above-mentioned columnar bump When the 290, 291 is substituted for the bump 280, the thickness of the columnar bumps 290, 291 may also be greater than the total thickness of the metal line 250 and the polymer layer 247. In FIG. 127, the thickness b47 of the bump 280 is substantially the same as the total thickness (c+e) of the metal line 250 and the polymer layer 247, and so on, when the aforementioned columnar bumps 290, 291 are replaced. In the case of the bump 280, the thickness of the stud bumps 290, 291 may also be equal to the total thickness of the metal line 250 and the polymer layer 247. In FIG. 128, the thickness b48 of the bump 280 is greater than the total thickness (c+e) of the metal line 250 and the polymer layer 247, and so on, when the aforementioned stud bumps 290, 291 replace the bump 280. The thickness of the stud bumps 290, 291 may also be greater than the total thickness of the metal line 250 and the polymer layer 247. In Figures 129 and 130, polymer layer 247 is on protective layer 240. Metal line 250 is formed on polymer layer 247 and is not connected to the top film layer 236. The polymer layer 245 is located on the metal line 250 and the polymer layer 247 for protecting the metal line 250. The polymer layer 245 has 53 1284385 15625 twf. Doc/006 • . · . ·. * The opening 246' exposes the metal line 250 such that the opening formed by the opening 246 of the polymer layer 245, the bump, solder ball or wire is electrically connected to the metal line 250 and the external circuit components. The bumps 28 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It should be noted that in FIG. 129, the thickness b49 of the bump 280 is smaller than the total thickness (c+d+e) of the metal line 250 and the polymer layers 245, 247, and so on, when the foregoing columnar shape When the bumps 290, 291 are substituted for the bumps 280, the thickness of the stud bumps 290, 291 may also be less than the total thickness of the metal lines 250 and the polymer layers 245, 247; in Fig. 13A, the bumps 28 The thickness of the seven 〇 system is greater than the total thickness (c+d+e) of the metal line 250 and the polymer layers 245, 247, and so on, when the aforementioned columnar bumps 290, 291 replace the bump 280' The thickness of the stud bumps 290, 291 may also be less than the total thickness of the metal lines 250 and the polymer layers 245, 247. In Figs. 131 and 132, the polymer layer 247 is located on the protective layer 240. The metal line 250 is formed on the polymer layer 247, and the thin film wiring layer 236 is not attached to the top layer. The bumps 280 are formed in direct contact with the contacts 242 of the protective layer 240 and the contacts of the thin film wiring layer 236 exposed by the openings 248 of the polymer layer 247. It is to be noted that, in FIG. 131, the thickness b51 from which the bump 280 protrudes is the same as the thickness c of the metal line 250, and so on, when the above-mentioned columnar bumps 290, 291 replace the bump 280, The thickness of the protruding protrusions 290, 291 may also be the same as the total thickness of the metal line 250 and the polymer layers 245, 247; in Figure 132, the protrusion 280 protrudes from the outer thickness b52 Greater than the thickness c of the metal line 250, and so on, when the aforementioned stud bumps 290, 291 replace the bumps 280, the thickness of the stud bumps 290, 291 protruding outward may also be greater than the metal line 250 and the polymerization. The total thickness of the layers 245, 247 is added. In FIGS. 133 and 134, the polymer layer 247 is located on the protective layer 240 54 1284385 15625 twf. On doc/006, metal line 250 is formed on polymer layer 247 and is not connected to the top film layer 236. The polymer layer 245 is disposed on the metal line 250 and the polymer layer 247 for protecting the metal line 250. The polymer layer 245 has an opening 246 exposing the metal line 25A such that the opening 246 of the multiplex layer 245 is transmitted. The wires formed by the bumps, solder balls or wire bonding methods can be electrically thinned to the metal wires 250 and the external circuit components. Bumps 280 are formed in direct contact with the contacts of opening 242 of protective layer 240 and film wiring layer 236 exposed by opening 248 of polymer layer 247. It is to be noted that, in FIG. 133, the thickness b53 of the protrusion 280 is smaller than the total thickness (c+d) of the metal line 250 and the polymer layer 245, and so on, when the foregoing columnar shape When the bumps 290, 291 are substituted for the bumps 280, the thickness of the stud bumps 290, 291 may be the same as the total thickness of the metal lines 250 and the polymer layer 245; in FIG. 134, the bumps are The outer thickness b54 is greater than the total thickness (c+d) of the metal line 250 and the polymer layer 245, and so on, when the aforementioned columnar bumps 290, 291 replace the bump 280, the column The thickness of the protrusions 290, 291 protruding outward may also be greater than the total thickness of the metal line 250 and the polymer layer 245. In the above embodiments of FIG. 122 to FIG. 134, the materials of the polymer layers 245 and 247 are, for example, polyimide (pi), benzocydobutene (BCB), and polyarylene ether (parylene). ), a porous dielectric material or an elastomer, etc., and the thicknesses d, e of the polymer layers 245, 247 are, for example, greater than 1 micron. III. Third Embodiment of Wafer Structure Fabrication Method FIG. 135 to FIG. 138 are schematic cross-sectional views showing the fabrication of metal lines and bumps on a semiconductor wafer in accordance with a third embodiment of the present invention. Referring to FIG. 135, firstly, half of the body wafer 200 is provided. The semiconductor wafer 2 includes a half of the substrate substrate 21, a plurality of thin film dielectric layers 222, 224, and 226, and a plurality of thin film circuit layers 232, 4, 55 1284385 15625twf. The detailed structure of the doc/006 236 and the sac layer 240 is described in detail in the first point of the first embodiment, and will not be described again. . Referring to FIG. 135, after the semiconductor wafer 200 is provided, the bottom metal layer 250 may be formed on the protective layer 240 of the semiconductor wafer 200 and exposed to the thin film wiring layer 236 outside the opening 242 of the protective layer 240 by means of smear. On the contacts 236a, 236b, in the process, for example, comprising first extruding the adhesion/barrier layer on the protective layer 240 of the semiconductor wafer 200 and exposing the thin film wiring layer 236 outside the opening p 242 of the protective layer 240, Then, the seed layer is further deposited on the adhesion/barrier layer, and the materials of the adhesion/barrier layer and the seed layer are described later, and will not be described herein. The connector ' can form a photoresist layer 260 on the bottom metal layer 252, and the photoresist layer 260 has an opening 262 exposing the bottom metal layer 252, as shown in FIG. Then, a metal layer 254 having a line circle 254a and a bump pattern 254c can be formed on the bottom metal layer 252 exposed by the opening 262 of the photoresist layer 260 by using an electric key, as shown in FIG. The wiring pattern 254a of the layer 254 is electrically connected to the contact 236a of the thin film wiring layer 236, and extends over the protective layer 240, and the bump pattern 254c of the metal layer 254 is located on the contact 236a of the thin film wiring layer 236. A plane 1000 is defined that is substantially parallel to the active surface 214 of the semiconductor substrate 210, wherein the line pattern 254a of the metal layer 254 is projected onto the plane 1000 such that the extent is greater than 50 〇 microns, or such as greater than 800 microns. Or, for example, greater than 12 〇〇 microns; the area of the line pattern 254a of the metal layer 254 projected onto the plane 1 比如 is, for example, greater than 3 〇, 〇〇〇 square microns, or such as greater than 80,000 square microns, or such as greater than 150,000 square microns. The area of each of the bump patterns 254c of the metal layer 254 projected onto the plane 1000 is, for example, less than 30,00 square microns, or such as less than 20,000 square microns, or such as less than 15,000 square microns. The photoresist layer 260 can then be removed to expose the bottom metal layer 252, as shown in FIG. Then, the metal layer 254 is used as an etching cover wall, and is etched by etching 56 1284385 15625 twf. The doc/006 method sequentially removes the seed layer and the adhesion/barrier layer of the bottom metal layer 252 that is not covered by the metal layer 254, leaving only the bottom metal layer 252 under the metal layer 254, as shown in FIG. Thereafter, a single-cut step can be performed in which the dicing blade cuts the semiconductor wafer 200 along the scribe-line of the semiconductor wafer 200, thereby forming a plurality of individual wafer structures 205. In the above process, the metal line 250 and the bump 280 can be completed simultaneously, since the metal line 250 and the bottom metal layer 252 of the bump 280 are formed by the same sputtering step, and the metal line 250 and the metal of the bump 280 are formed. The layer 254 is formed by the same plating step, so that the steps of forming the gold bullion line 250 and the bumps 280 can be simplified. 2. Metal Structure of Metal Circuit and Bump Referring to FIG. 139, a cross-sectional view of a metal layer structure of a metal line and a bump according to a third embodiment of the present invention is shown, wherein when the bottom metal layer 252 is formed, for example The adhesion/barrier 2521a is formed by a sputtering process, and then a gold layer 2521b as a seed layer is formed on the adhesion/barrier layer 2521a by sputtering, wherein the material of the adhesion/barrier layer 2521a is Titanium, Chinhe alloy, titanium nitrogen compound, ruthenium or group ruthenium compound. When the gold-plated layer 254 is formed, for example, a gold layer having a thickness X of more than 3 μm is formed on the seed layer 2521b of the bottom metal layer 252 by electroplating. 3. Thickness relationship between bumps, metal wiring and polymer layers In the third embodiment, as shown in FIG. 138, the metal lines 250 are exposed and directly contacted on the protective layer 240, and the metal lines 250 can be connected and exposed. The junction of the thin film wiring layer 236 outside the opening 242 of the protective layer 240. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It is to be noted that the thickness b55 of the bump 280 is equal to the thickness c of the metal line 250. 57 1284385 15625twf. Doc/006 In FIG. 140, a metal line 250 is formed in direct contact with the protective layer 240, and may be connected to a joint of the thin boat circuit layer 236 exposed outside the opening 242 of the protective layer 240, a polymer layer 245 The metal line 250 is formed on the metal line 250 and on the protective layer 240. The bumps 280 are formed in true contact with the contacts of the thin boat circuit layer 236 exposed by the openings 242 of the protective layer 240. It is noted that in the circle 140, the thickness b56 of the bump 280 is equal to the thickness c of the metal line 250 and less than the total thickness (c+d) of the metal line 250 and the polymer layer 245. In FIG. 141, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242 of the protective layer 240 and expose the contacts of the top film layer 236. . A metal line 250 is formed on the polymer layer 247 and is connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It is to be noted that in FIG. 141, the thickness b57 of the bump 280 is equal to the thickness c of the metal line 250 and less than the total thickness (c+e) of the metal line 250 and the polymer layer 247. In FIG. 142, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242 of the protective layer 240 and expose the contacts of the top film layer 236. . A metal line 250 is formed on the polymer layer 247 and is connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. Polymer layer 245 is located on metal line 250 and on polymer layer 247 to protect metal line 250. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It should be noted that, in FIG. 142, the thickness b58 of the bump 280 is equal to the thickness c of the metal line 250, and is less than the total length of the metal line 250 and the polymer layer 245, 247 58 1284385 15625 twf. The thickness of doc/006 (c+d+e) 〇 In FIG. 143, the polymer layer 247 is on the protective layer 24, and the polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242 of the protective layer 240. And exposing the contacts of the top film layer 236. The gold repeat line 250 is formed on the polymer layer 247 and is connected to the film line layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. The bumps 280 are formed in direct contact with the contacts of the opening 242 of the protective layer 240 and the thin film wiring layer 236 exposed by the opening 248 of the polymer layer 247. It is to be noted that in Fig. 143, the protrusions 280 protrude from the outside and the 59 is the same as the thickness c of the metal line 250. In FIG. 144, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242 of the protective layer 240 and expose the contacts of the top film layer 236. . The metal line 250 is formed on the polymer layer 247, and the contact 〇 polymer layer 245 which is connectable to the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240 is located on the metal line 250 and The polymer layer 247 is used to protect the metal line 250. The bumps 280 are formed in direct contact with the contacts 242 of the protective layer 240 and the contacts of the thin film wiring layer 236 exposed by the openings 248 of the polymer layer 247. It is noted that in FIG. 144, the thickness b60 of the bump 280 is equal to the thickness c of the metal line 250 and less than the total thickness (c+d) of the metal line 250 and the polymer layer 245. In the above embodiments of FIG. 140 to FIG. 144, the materials of the polymer layers 245 and 247 are, for example, polyimide (PI), benzocyclobutene (BCB), and polyarylene ether (parylene). ), a porous dielectric material or an elastic crucible, etc., and the thickness d, e of the polymer layers 245, 247 is, for example, greater than 1 micron 〇 4 · the function of the metal line 59 1284385 15625twf. Doc/006 金属·Metal circuit system for internal signal transmission of the wafer structure. Referring to FIG. 138 and FIG. 140 to FIG. 144, the gold exhibition line 250 is used for internal signal transmission of the wafer structure 205, that is, the electronic element sister 212. One of the components (such as the electronic component 212a) is adapted to rotate an electronic signal, which is transmitted through the thin film circuit layers 232, 234, 236 and through the protective layer 240, and then transmitted to the metal line 250, and then through the protection. The layer 24 is transferred to at least one of the other electronic components 212 (such as the electronic component 212b) via the thin film wiring layers 236, 234, 232. B. Metal circuit as a power bus or a bus bar of a wafer structure. FIG. 145 to FIG. 150 are schematic cross-sectional views showing a structure of a wafer according to a third embodiment of the present invention, wherein the metal line 250 and the film circuit layer are The thin film power bus 235 is electrically connected as a power bus of the wafer structure 205. Alternatively, the metal line 250 may be electrically connected to the thin film ground bus bar 235 of the thin film circuit layer as the ground bus bar of the wafer structure 205. Referring to FIG. 145, the metal line 250 is exposed and directly contacted on the protective layer 240, and may be connected to the contact of the thin film wiring layer 236 exposed outside the opening 242 of the protective layer 240. The bumps 280 are in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It is to be noted that the thickness b61 of the bump 280 is equal to the thickness c of the metal line 250. In FIG. 146, metal lines 250 are formed in direct contact with protective layer 240, and a polymer layer 245 is formed over metal lines 250 and protective layer 240 to protect metal lines 250. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It should be noted that in FIG. 146, the thickness b62 of the bump 280 is equal to the thickness c of the metal line 250, and is less than the metal line 250 and the polymer layer 245 1284385 1 static arsenic 15625 twf. Doc/006 The total thickness (c+d) added is shown in FIG. 147. The polymer layer 247 is on the protective layer 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings of the protective layer 240. 242 and exposing the contacts of the top film line layer 236. A metal line 250 is formed on the polymer layer 247 and is connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layers 236 exposed by the blue openings 242 of the protective layer 240. It is noted that in FIG. 147, the thickness b63 of the bump 280 is equal to the thickness c of the metal line 250 and less than the total thickness (c+e) of the metal line 250 and the polymer layer 247. In FIG. 148, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242 of the protective layer 240 and expose the connection of the top film layer 236. point. A metal tantalum line 250 is formed on the polymer layer 247 and is connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. Polymer layer 245 is located on metal line 250 and on polymer layer 247 to protect metal line 250. A bump 280 is formed in direct contact with the contact of the thin film wiring layer 236 exposed by the opening 242 of the protective layer 240. It is worth noting that in Figure 148, the thickness b64 of the bump 280 is equal to the thickness c of the metal line 250* and less than the total thickness of the metal line 250 and the polymer layers 245, 247 (c+d+e ). In FIG. 149, polymer layer 247 is disposed on protective layer 240 having a plurality of openings 248 that are substantially aligned with openings 242' of protective layer 240 and exposing the contacts of thin film wiring layer 236 of the top layer. A metal line 250 is formed on the polymer layer 247 and is connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. The bump 280 is formed in direct contact with the opening of the protective layer 240 and the contact of the thin film wiring layer 236 exposed by the opening 248 of the layer 247 of the polymer 1284385 15625 tw. It is to be noted that in Fig. 149, the thickness b65 from which the bump 280 protrudes is the same as the thickness e of the metal wiring 250. In FIG. 150, the polymer layer 247 is located in the protective layer 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242 of the protective layer 240 and expose the contacts of the top film layer 236. . The metal line 250 is formed on the polymer layer 247, and can be connected to the contact of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240, and the polymer layer 245 is located on the metal line 250. And the polymer layer 247 is used to protect the metal line 250. The bumps 280 are formed in direct contact with the contacts of the opening 242 of the protective layer 240 and the thin film wiring layer 236 exposed by the opening 248 of the polymer layer 247. It is noted that in Figure 150, the thickness 266 of the four 280 protrusions is equal to the thickness c of the metal line 250 and less than the total thickness (c+d) of the metal line 250 and the polymer layer 245. In the above embodiments of FIGS. 145 to 150, the materials of the polymer layers 245 and 247 are, for example, polyimide (PI), benzocyclobutene (BCB), and polyarylene (parylene). ), a porous dielectric material or an elastomer, etc., and the thicknesses d, e of the polymer layers 245, 247 are, for example, greater than 1 micron. The C. metal circuit is used as a signal transmission line, a power supply flow line or a ground bus, wherein the metal circuit uses the top film layer to electrically connect the bumps. Please refer to FIG. 151 to FIG. A cross-sectional view of the wafer structure of the third embodiment of the present invention, wherein the metal line 250 is connected to the bump 280 by a thin film circuit layer 236 of the top layer, and the metal wiring layer 250 is used, for example, as a signal transmission line, a power bus or a ground bus. The metal line 250 is disposed on the protective layer 240 and electrically connected to the contact 237a of the thin circuit layer 236 via the opening 242 of the protective layer 240. The bump 280 is fastened to the opening of the protective layer 240 242 62 1284385 15625twf. Doc/006 is exposed on the contact 237b of the thin film wiring layer 236. The thin film circuit layer 236 has a connection line 237 connecting the contacts 237 & 23713 so that the metal line 250 can be electrically connected to the bump 280 through the connection line 237 and the contacts 237a, 237b. Referring to FIG. 152, a top view of the connection line 237 and the connection line 237, 2371 is shown. In the preferred case, the extension distance s of the connection line 237 is, for example, less than 500 microns. Referring to FIG. 151 to FIG. 157, when the metal line 250 is used as a signal transmission line, the electronic signal outputted by one of the electronic components 212 (for example, the electronic component 212a) can be worn through the thin film circuit layers 232, 234, and 236. After passing through the protective layer 240, it is transferred to the metal line 250, then passes through the protective layer 240, and is transferred to the bump 260 via the connecting line 237 of the thin film wiring layer 236. Alternatively, the electronic signal received by the bump 260 may be transmitted through the protective layer 240 to the connection line 237 of the thin film line 236, then through the protective layer 240 to the metal line 250, and then through the protective layer 240, and At least one of the electronic components 212 (such as the electronic component 212a) is transferred via the thin film wiring layers 236, 234, 232. When the metal line 250 is used as a power bus, for example, the metal line 250 can be connected to the substrate, the tape, the film, or the glass substrate via the connecting line 237 of the thin film wiring layer 236 and the bump 280. end. When the metal circuit layer 250 is used as a ground bus bar, for example, the metal circuit layer 250 can be connected to the substrate, the tape, the film, or the glass substrate via the connecting line 237 of the thin film wiring layer 236 and the bump 280. Ground terminal. Referring to FIG. 151, the metal line 250 is exposed and directly contacted on the protective layer 240. The metal line 250 can be connected to the contact of the thin film wiring layer 236 exposed outside the opening 242 of the protective layer 240. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It is to be noted that the thickness b67 of the bump 280 is equal to the thickness c of the metal line 250. 63 1284385 15625twf. Doc/006 In Fig. 153, a metal line 250 is formed in direct contact with the protective layer 240, and may be connected to the contact of the thin film wiring layer 236 exposed outside the opening 242 of the protective layer 240. Polymer layer 245 is formed on metal line 250. - . · ·· . And the protective layer 240, thereby protecting the metal line 250. The bump 280 is formed in direct contact with the contact of the thin film wiring layer 236 which is smashed by the opening 242 of the protective layer 240. It is noted that in circle 153, the thickness b68 of bump 280 is equal to the thickness c of metal line 250 and less than the total thickness (c+d) of metal line 250 and polymer layer 245. In FIG. 154, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242 of the protective layer 240 and expose the contacts of the top film layer 236. . A metal tantalum line 250 is formed on the polymer layer 247 and is connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It is noted that in FIG. 154, the thickness b69 of the bump 280 is equal to the thickness c of the metal line 250 and less than the total thickness (c+e) of the metal line 250 and the polymer layer 247. In FIG. 155, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242 of the protective layer 240 and expose the contacts of the top film layer 236. . The metal line 250 is formed on the polymer layer 247 and is connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the bonding layer 240. Polymer layer 245 is located on metal line 250 and on polymer layer 247 to protect metal line 250. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 24''. It should be noted that in FIG. 155, the thickness b70 of the bump 280 is equal to the thickness c of the metal line 25A, and is less than the total of 1284385 15625 twf of the metal line 250 and the polymer layer 245, 247. The thickness of doc/006 (c+d+e). In FIG. 156, polymer layer 247 is disposed on protective layer 240, and polymer layer 247 has a plurality of openings 248 that are substantially aligned with openings 242 of protective tubing 240 and expose the defect of the top film layer 236. A metal line 250 is formed on the polymer layer 247 and is connected to the junction of the thin film wiring layer 236 via the opening 248 of the polymer layer 247 and the opening 242 of the protective layer 240. The bumps 280 are formed in direct contact with the contacts of the opening 242 of the protective chip 240 and the film wiring layer 236 exposed by the opening 248 of the polymer layer 247. It is to be noted that in Fig. 156, the thickness b71 from which the bump 280 protrudes is the same as the thickness c of the metal line 250. In FIG. 157, the polymer layer 247 is disposed on the protective layer 240. The polymer layer 247 has a plurality of openings 248 that are substantially aligned with the openings 242 of the protective layer 240 and expose the contacts of the top film layer 236. . Metal lines 250 are formed on polymer layer 247 and may be connected to the contacts of thin film wiring layer 236 via openings 248 of polymer layer 247 and openings 242 of protective layer 240. Polymer layer 245 is located on metal line 250 and on polymer layer 247 to protect metal line 250. Bumps 280 are formed in direct contact with the contacts of the opening 242 of the protective sleeve 240 and the film wiring layer 236 exposed by the opening 248 of the polymer layer 247. It is noted that in Figure 157, the thickness b72 of the bump 280 is less than the total thickness (c+d) of the metal line 250 and the polymer layer 245. In the above embodiments of FIGS. 151 to 157, the materials of the polymer layers 245, 247 are, for example, polyimide, PI, benzocyclobutene (BCB), polyarylene ether (parylene). ), a porous dielectric material or an elastomer, etc., and the thicknesses d, e of the polymer layers 245, 247 are, for example, greater than 1 micron. D. Metal circuit is used as signal transmission and power supply of external circuit components. 65 1284385 15625twf. Doc/006 row or ground bus bar 158 to 163 are schematic cross-sectional views of a wafer structure according to a third embodiment of the present invention, wherein the metal line 250 is used as a signal transmission of an external circuit component (not shown). For the power bus or ground bus, the metal line 250 is not connected to the top film circuit layer 236. In the electrical connection, for example, the external circuit component can be electrically connected to the metal circuit 25 by means of wire-bonding; or a bump or a solder ball can be formed on the external circuit component for connecting the metal. Line 250. When the metal line 250 is used for signal transmission of the external circuit member, the external circuit member can rotate an electronic signal to the metal line 250' via the metal line 250 and then transmit it to the external circuit member. In addition, the metal line 250 can also serve as a power bus or ground bus of the external circuit components, and the metal line 250 can be connected to the power bus or ground bus of the external circuit components. Referring to FIG. 158, the metal line 250 is exposed and directly contacted on the protective layer 240. The metal line 250 is not connected to the top film layer 236. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It is to be noted that the thickness b73 of the bump 280 is equal to the thickness c of the metal line 250. In Fig. 159, the metal wiring 250 is formed in direct contact with the protective layer 240, and the thin film wiring layer 236 of the top layer is not connected. A polymer layer 245 is formed over the metal line 250 and the protective layer 240 to protect the metal line 250. The polymer layer 245 has openings 246 that expose the metal lines 250 such that the openings 246 through the polymer layer 245, bumps, The wires formed by the solder balls or the wire bonding method can electrically connect the metal wires 250 and the external circuit components. It is noted that in Figure 159, the thickness b74 of the bump 280 is equal to the thickness c of the metal line 250 and less than the total thickness (c+d) of the metal line 250 and the polymer layer 245. 66 1284385 15625twf. Doc/006 In Fig. 160, polymer layer 247 is disposed on protective layer 240, and gold ruthenium line 250 is formed on polymer layer 247 without the top film line layer 236 being attached. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the opening 242 of the protective cover 240. It is to be noted that, in FIG. 160, the thickness b75 of the bump 280 is equal to the thickness c of the metal line 250 and less than the total thickness (c+e) of the metal line 250 and the polymer layer 247. The polymer layer 247 is on the protective layer 240, and the metal line 250 is formed on the polymer layer 247, and the thin film wiring layer 236 of the top layer is not connected. The polymer layer 245 is disposed on the metal line 250 and on the polymer layer 247 to protect the metal line 250. The polymer layer 245 has an opening 246 exposing the metal line 250 such that the opening 246 of the polymer layer 245 passes through the bump. The wires formed by the solder balls or the wire bonding method can electrically connect the metal wires 250 and the external circuit components. The bumps 280 are formed in direct contact with the contacts of the thin film wiring layer 236 exposed by the openings 242 of the protective layer 240. It is noted that in Figure 161, the thickness b76 of the bump 280 is equal to the thickness of the metal line 250 and less than the total thickness (c + d + e) of the metal line 250 and the polymer layers 245, 247. In Figure 162, polymer layer 247 is disposed on protective layer 240, and metal line 250 is formed over polymer layer 247 without the top film line layer 236 being attached. Bumps 280 are formed in direct contact with the openings 242 of the protective shield 240 and the contacts of the thin film wiring layer 236 exposed by the openings 248 of the polymer layer 247. It is to be noted that, in FIG. 162, the thickness b77 of the bump 280 protruding from the outside is the same as the thickness c of the metal line 250. In Fig. 163, the polymer layer 247 is disposed on the protective layer 240, and the metal wiring 250 is formed on the polymer layer 247, and the thin film wiring layer 236 of the top layer is not connected. Polymer layer 245 is located on metal line 250 and polymer layer 247 to protect metal line 250. Polymer layer 245 has opening 246, storm 67 1284385 15625 twf. The doc/006 exposes the metal line 250 such that the wires formed by the openings 246 of the polymer layer 245, bumps, solder balls or wire bonding can electrically connect the metal lines 250 to the external circuit components. The bumps 280 are formed in direct contact with the contacts 242 of the protective layer 240 and the contacts of the thin film wiring layer 236 exposed by the openings 248 of the polymer layer 247. It is to be noted that, in FIG. 163, the thickness b78 of the bump 28Q is equal to the thickness of the metal line 250 (:, and is less than the total thickness of the gold trace 250 and the polymer layer 245 (c+d). In the above embodiment of FIG. 158 to circle 163, the material of the polymer layers 245, 247 is, for example, polyimide, benzocyclobutene 'BCB, polyarylene ether. (parylene), a porous dielectric material or an elastomer, etc., and the thicknesses d, e of the polymer layers 245, 247 are, for example, greater than 1 micron. IV. Conclusion In summary, the wafer structure of the present invention and a method of fabricating the same, The steps of fabricating bumps can be integrated with the steps of fabricating metal lines to simplify the process steps for forming metal lines and bumps. The wafer structure of the present invention and the method of fabricating the same can form a copper layer or a gold layer having a thickness greater than 丨 micron. On the protective layer of the semiconductor wafer, as a metal line, and a gold layer or a solder layer having a thickness greater than 3 μm can be formed on the protective layer of the semiconductor wafer as a bump. Although the present invention has been a preferred embodiment Reveal However, it is not intended to limit the invention of the invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope is defined as 68.284385 15625twf. Doc/006 [Simplified Schematic] FIG. 1 to FIG. 12 are schematic cross-sectional views showing a process for fabricating metal lines and bumps on a semiconductor wafer. FIGS. 13 to 21 illustrate a first embodiment of the present invention. A schematic view of a scraped surface of a first method of making metal lines and bumps on a conductive conductor wafer. 22 to 25 are schematic cross-sectional views showing the metal layer structure of the metal wiring and the pad in accordance with the first embodiment of the present invention. 26 to 29 are schematic cross-sectional views showing a bump of a bump according to a first embodiment of the present invention. 30 to 33 are cross-sectional views showing a second method of fabricating metal lines and bumps on a semiconductor wafer in accordance with a first embodiment of the present invention. 34 to 39 are schematic cross-sectional views showing a first method of fabricating a metal wiring and a columnar bump of a first form on a semiconductor wafer in accordance with a first embodiment of the present invention. 40 and 41 are schematic cross-sectional views showing a second method of fabricating a metal line and a columnar bump of a first form on a semiconductor wafer in accordance with a first embodiment of the present invention. 42 to 47 are schematic cross-sectional views showing a first method of fabricating a metal wiring and a columnar bump of a second form on a semiconductor wafer in accordance with a first embodiment of the present invention. 48 to 52 are schematic cross-sectional views showing a second method of fabricating a metal wiring and a columnar bump of a second form on a conductive conductor wafer in accordance with a first embodiment of the present invention. Figure 53 is a cross-sectional view showing a wafer structure having metal lines, bumps, and polymer layers on a protective layer in accordance with a first embodiment of the present invention. Fig. 54 and Fig. 55 are schematic cross-sectional views showing the structure of a wafer in accordance with a first embodiment of the present invention, wherein the metal wiring is used for internal signal transmission of the wafer structure. 69 1284385 15625twf. Doc/006 Figures 56 and 57 are schematic cross-sectional views showing the structure of a wafer in accordance with a first embodiment of the present invention, wherein the metal wiring is used as a power bus or ground bus for the wafer structure. 58 and 59 are schematic cross-sectional views showing the structure of a wafer in accordance with a first embodiment of the present invention, wherein the metal wiring is used as a signal transmission, a power bus or a ground bus of an external circuit component. 60 to 66 are schematic views showing the fabrication of metal lines and bumps on a semiconductor wafer in accordance with a second embodiment of the present invention. 67 to 70 are cross-sectional views showing the structure of a metal layer of a metal wiring according to a second embodiment of the present invention. Figure 71 and circle 72 are schematic cross-sectional views showing the weft of the bump according to the second embodiment of the present invention. 73 to 77 are cross-sectional views showing the fabrication of a metal line and a columnar bump of a first form on a half-stack wafer in accordance with a second embodiment of the present invention. 78 to 82 are schematic cross-sectional views showing the fabrication of a metal line and a columnar bump of a second form on a semiconductor wafer in accordance with a second embodiment of the present invention. 83 to 94 are schematic cross-sectional views showing the structure of a wafer in accordance with a second embodiment of the present invention, wherein the metal wiring is used for internal signal transmission of the wafer structure. 95 to 107 are schematic cross-sectional views showing a wafer junction according to a second embodiment of the present invention, wherein the metal wiring is used as a power bus or a bus bar of the wafer structure. 108 to @121 show a schematic view of a wafer structure according to a second embodiment of the present invention, wherein the metal circuit is used as a signal transmission line, a power supply grounding bus, and the metal circuit uses a thin film circuit layer on the top layer. Sexual connection bumps. 122 to 134 are schematic cross-sectional views showing a wafer junction according to a second embodiment of the present invention, wherein the metal circuit is used as a signal for the external circuit component, or a power bus or a ground bus. ' J " 1284385 15625twf. Doc/006 Figures 135 through 138 are schematic cross-sectional views showing the fabrication of metal lines and bumps on a semiconductor wafer in accordance with a third embodiment of the present invention. Figure 139 is a cross-sectional view showing the metal layer structure of a metal wiring and a bump according to a third embodiment of the present invention. 140 to 144 are schematic cross-sectional views showing a crystal structure according to a third embodiment of the present invention, wherein the metal wiring is used for internal signal transmission of the wafer structure. 145 to 150 are schematic cross-sectional views of a wafer structure not according to a third embodiment of the present invention, wherein the metal wiring is used as a power bus or a ground bus of the wafer structure. If1 is a cross-sectional view of a wafer structure according to a third embodiment of the present invention, wherein the metal circuit is used as a signal transmission line, a power bus or a ground bus, and the line is made of a thin layer of the top layer. Sexual connection bumps. The phantom to the ganogram 2 shows the signal structure, the power busbar or the ground busbar of the wafer structure in which the metal circuit is used as the external circuit component in accordance with the third embodiment of the present invention. [Major component symbol description] 10: Path 100: Semiconductor wafer 110: Semiconductor substrate 112: Electronic component 114: Active surface 121, 123, 125: Via holes 122, 124, 126: Thin film dielectric layers 132, 134, 136: Thin film Circuit layer 140: protective layer 150: metal line 152: bottom metal layer 71 1284385 15625twf. Doc/006 154 Metal pattern of line pattern 160 Photoresist layer 162 Opening of photoresist layer 170 Polymer layer 172 Opening of polymer layer 180 Bump 182 Bottom gold layer 184 Bump pattern metal layer 190 Photoresist layer 192 light Resistor opening 200 semiconductor wafer 205 wafer structure 210 semiconductor substrate 212 electronic component 214 active surface 221, 223, 225: via 222, 224, 226: thin film dielectric layer 232, 234, 236: thin film wiring layer 235: thin film power supply Bus bar, film ground bus bar 236a, 236b, 237a, 237b · Film circuit layer contact 237: connection line 240: protective layer 245: polymer layer 246: polymer layer opening 247 · polymer layer 248: Opening 250 of polymer layer: metal line 251 ··pad 252: bottom metal layer 72 1284385 15625twf. Doc/006 2521a, 2522a, 2523a, 2524a: adhesion/barrier layer 2521b, 2522b, 2523b, 2524b: seed layer 254: metal layer 254a: metal layer wiring pattern 254b: metal butt pattern 254c: metal layer Bump pattern 2543a: copper layer 2543b: nickel layer 2544a · copper layer 2544b: nickel layer 2544c · gold layer 260 · photoresist layer 262: opening of photoresist layer 270: photoresist layer 272: opening of photoresist layer 275: photoresist layer 276: opening of photoresist layer 280 · bump 2801: gold layer 2802a: adhesion/barrier layer 2802b: gold layer 2803: solder layer 2804a: adhesion/barrier layer 2804b: copper layer 2804c: nickel Layer 2804d: solder layer 282: metal layer 2822a of bump pattern: copper layer 2822b: nickel layer 73 1284385 15625twf. Doc/006 2822c : Solder layer 290, 291 : Columnar bump 292 : Metal pillar 293 : Bottom metal layer 294 : Columnar metal layer 295 : Anti-aggression layer 296 : Solder layer 1000 · · Plane