TWI247362B - Varactor and differential varactor - Google Patents

Abstract

A varactor is provided. The varactor is consisted of a second type substrate, two gate structures, a first type doped region and a second type doped region. These two gate structures having a gate dielectric layer and a gate conductive layer are located on the substrate. The first type doped region is located in the substrate between these two gate structures. The second type doped region is located in the substrate on the other side of the gate structure without the first type doped region. Wherein the first type doped region is electrically connected to a first electrode, the second type doped region is electrically connected to a second electrode, and these two gate structure is electrically connected to the first electrode or the second electrode. Since the varactor includes structures of a MOS varactor and a junction varactor, it has character of these two varactors.

Description

1247362 Case No. 93108629 V. Description of the Invention (1) Technical Field of the Invention θ The present invention relates to a variable capacitor (Varactor), and in particular to a variable modulation range of both capacitance and voltage. Variable capacitance port and differential variable capacitor (Differentiai Varactor). [Prior Art] In a typical communication system, an information signal (such as a TV program) will be turned on (Tune) and placed on a high frequency carrier to facilitate signal transmission. f. Different frequencies have different characteristics of carrier signals, and many information messages are transmitted. Therefore, the receiver in the communication system needs to use the Voltage Controlled Oscillator (VC0) to separate the f and signal from the carrier. In the VC〇, there is an L C (inductor-capacitor) circuit composed of a variable-voltage transistor and an inductor. By changing the capacitance of the variable capacitor with the voltage modulation, the oscillation frequency of the VC 随之 can be changed. Common variable capacitors include MOS variable capacitors based on metal oxide semiconductor transistor Metal-Oxide Semiconductor Transist(R, M〇s), and staggered with p-doped and n-doped regions. It is a Junction variable capacitor. Among them, M〇s is variable, although the capacitance of the container has a large modulation range ((maximum capacitance - minimum capacitance minimum capacitance), but this modulation range only falls within a small voltage modulation range (about 1 V), that is, a small voltage modulation, which will cause the capacitance to change drastically. However, although the capacitance of the M〇s variable capacitor has a large modulation range, since the voltage modulation range is too small, it is The adjustment of the valley has the disadvantage of being difficult to control. On the other hand, although the junction variable capacitor has a large modulation range (greater than 2 V), this

12868twf1.ptc Page 6 1243732 _ Case No. 93108629_年月日日__ V. Description of invention (2) The range of capacitance modulation corresponding to the modulation range is not large enough, so that the junction variable capacitor is used. Limited. Moreover, for the differential variable capacitor obtained by applying the above variable capacitor, the above problem may cause the quality factor (Q-Factor) of the differential variable capacitor itself to be poor, thereby affecting its charge storage capacity. The problem. Thus, it has been desired to develop a variable capacitor having a wide range of modulation voltages and having a wide range of modulation capacitance characteristics. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a variable capacitor that solves the problem that the capacitance or voltage modulation range of a conventional variable capacitor is not large enough. It is still another object of the present invention to provide a differential variable capacitor for improving the quality factor of a differential variable capacitor. The present invention provides a variable capacitor comprising a first type of substrate, two gate structures, a first type doped region and a second type doped region. Wherein, the two gate structures are disposed on the first type substrate, and each of the gate structures is composed of a lower gate dielectric layer and an upper gate conductive layer. Additionally, a first type of doped region is disposed in the first type of substrate between the two gate structures. Further, the second type doping region is disposed in the first type substrate of the other side of the two gate structures not provided with the first type doping region. The first type doped region is electrically connected to the first electrode end, and the second type doped region is electrically connected to the second electrode end, and the two gate structures are connected to the first electrode end or The second electrode end is electrically connected. The present invention provides a differential variable capacitor that is comprised of at least one pair of variable capacitors disposed on a first type of substrate.

12868twf1.ptc Page 7 1247362 _ Case No. 93108629_年月日日__ V. Description of Invention (3) Composition, wherein each pair of variable capacitors includes a first variable capacitor and a second variable capacitor. The first variable capacitor includes two first gate structures, a first type first doped region and a second type first doped region, and the second variable capacitor is adjacent to the first variable capacitor And the second variable capacitor includes two second gate structures, a first type second doped region and a second type second doped region. The two first gate structures are disposed on the first type substrate, and each of the first gate structures is formed by a first gate dielectric layer of the lower layer and a first gate conductive layer of the upper layer. Additionally, a first type of first doped region is disposed in the first type of substrate between the two first gate structures. Further, the second type first doping region is disposed in the first type substrate of the other of the two first gate structures not disposed on the other side of the first type first doping region. In addition, the two second gate structures are disposed on the first type substrate, and each of the second gate structures is formed by a second gate dielectric layer of the lower layer and a second gate conductive layer of the upper layer. Further, a first type second doped region is disposed in the first type of substrate between the two second gate structures. In addition, the second type second doping region is disposed in the first type substrate of the other side of the two second gate structures not configured with the first type second doping region, and is the first type with the second type The doped regions are adjacent. The first gate structure and the first type first doped region are electrically connected to a modulation voltage terminal, and the second gate structure and the first type second doping region are electrically connected to a relative modulation. The voltage terminal, and the second type first doping region and the second type second doping region are grounded. Since the variable capacitor or the differential variable capacitor of the present invention includes a MOS variable capacitor mainly composed of a gate structure, and a junction mainly composed of the first type doping region and the second type doping region Variable capacitor, so this variable capacitor or differential variable capacitor system has both kinds of variable current

12868twf1.ptc Page 8 1247362 _ Case No. 93108629_年月日日__ V. Description of invention (4) The characteristics of the container, so its capacitance and voltage have a large range of modulation. Moreover, the quality factor of the differential variable capacitor can also be improved. The above and other objects, features, and advantages of the present invention will be apparent from [Embodiment] In the following embodiments, the present invention will be described with the first type being a p-type doping type and the second type being an n-type doping type. However, those skilled in the art can easily infer that the doping patterns of the first type and the second type can be exchanged with each other, and thus other embodiments which are opposite to the doping type of the following embodiment are omitted. Further, in the following embodiments, the present invention will be described with the first electrode end as the anode and the second electrode end as the cathode. Similarly, those skilled in the art can easily infer that the electrodes of the first electrode end and the second electrode end can also be exchanged with each other, and thus other embodiments opposite to those of the following embodiments are omitted. [First Embodiment] Fig. 1 is a cross-sectional view showing a variable capacitor in accordance with a preferred embodiment of the present invention. Referring to Fig. 1, the variable capacitor of the present invention comprises an n-type substrate 100, two gate structures 102, 104, a p-doped region 106 and an n-type doped region 110. In a preferred embodiment, the variable capacitor further includes a germanium-type lightly doped region 108, an n-type lightly doped region 1 1 2, a spacer 1 14 and a scotch metal layer 116. Wherein, the two gate structures 1 0 2 and 1 0 4 are disposed on the n-type substrate 1 0 0 , and each of the gate structures 1 0 2 and 1 0 4 is composed of a lower gate dielectric layer 1 1 8 It is composed of a gate conductive layer 120 of the upper layer. Moreover, these two gate structures

12868twf1.ptc Page 9 1243732 —-_ Case No. 93108629 ___Year of the month _g_ Amendment ___ V. Description of the invention (5) 102 and 104, in addition to being arranged on the n-type substrate, may also be configured to have an n-type On the well area (not shown) type substrate (not shown). In addition, the material of the gate dielectric layer 1 18 is, for example, tantalum oxide, tantalum nitride or other suitable dielectric material, and the material of the gate conductive layer 12 2 is, for example, polycrystalline germanium, doped polysilicon or other suitable conductive material. . In addition, a 'p-type doping region 106 is disposed in the n-type substrate 1〇〇 between the two gate structures 丨〇2 and 1 〇4, and the two gate structures 1〇2 and 1〇4 This doped type doping region 1 0 6 is shared. In a preferred embodiment, the Ρ-type lightly doped region 1 is further disposed between the 11-type substrate 1 〇〇 and the 1)-type doped region 1 〇 6 under the two gate structures 102 and 1 〇 4 〇 8. In addition, the n-type doping region 1 is disposed in the n-type substrate ι of the two gate structures 丨〇2 and 104 disposed on the other side of the p-type doping region 1〇6 In the preferred embodiment, the n-type light-doped region is disposed between the n-type substrate 1 〇〇 and the n-type doped region 11 下方 under the two gate structures 1 〇 2 and 1 〇 4 In the preferred embodiment, the gap walls 4 are disposed on the sidewalls of the two gate structures 与2 and the spacers 4, and the spacers 4 and the n-type lightly doped regions 112 are covered. In another preferred embodiment, a further θ 矽 矽 metal layer 1 1 6 is disposed on the gate conductive layer 12 这 of the two gate structures 1 0 2 , 104 and the die doping The area 1〇6 and the 11-type doping region are changed to reduce the resistance of the two gate structures 102, 104, the doped-type doping region 1〇6 and the ni-doping region 1 1 ,, thereby increasing Electrical conductivity. , in other words, the above-mentioned p-type doped region 1 〇 6 is electrically == is, pole), and the „type doped region " 〇 is electrically connected to the second electric electrode of the second electrode such as 疋 cathode) And these two gate structures 1 0 2, 1 〇 4 are

12868twfl.ptc Page 10 1247362

The first electrode 1 2 2 is electrically connected. Install #丨^, and in comparison with mussels/also, the two gate structures 1 〇2, 1 0 4 ί t are electrically connected to the f-electrode 124 (for example, haze, I, I brother疋, the above-mentioned P-type doped region i 〇 6 is electrically connected to electricity = 22 (for example, an anode), and is a type doped region 11 〇 is electrically connected to a lightning; pole 124, and two gate structures 102 The 104 series is electrically connected to the second drain 1 2 4 . * The mIc is a variable capacitor including a gate structure 102 or 104 as a variable capacitor 'and a P-type doped region 106 and η The type doping region lj is mainly a junction variable capacitor, so the variable capacitor has the characteristics of the variable capacitor. The detailed description is that the k-type grid of the present invention is not only p-doped. The region between the impurity region 1〇6 and the n-type doping region 11〇 can be used to store charge (capacitance), and the gate dielectric layer 8 can also be used for storing electricity. Therefore, the present invention can Compared with the conventional M〇s capacitors or junction-type variable capacitors, the variable capacitors have better charge storage and force, that is, the capacitance can be adjusted to a larger range.

Further, the variable capacitor of the present invention has a distance between the p-type doped region 1 〇 6 and the „-type mismatch region 1 10 0 by the line widths of the gate structures 丨〇 2 and 1 〇 4 . That is, the narrower the line width of the gate structures 102 and 104, the smaller the distance between the p-type doped region and the n-type doped region 1 1 〇, so that the resistance of the container can be reduced, thereby enabling To evaluate the quality of the variable capacitor due to the increase in the energy factor. Further, in order to prove that the present invention can indeed increase the modulation range of the capacitance, the voltage modulation and the corresponding $ are performed by using the variable capacitor described above. The measurement of the volume is shown in Figure 2. Figure 2 is a variable capacitor whose electrical and electrical / electrical

Case number 93108629

1247362 V. INSTRUCTIONS (7) Pressure diagram, in which the horizontal axis represents the modulation voltage (V) and the vertical axis represents the capacitance that has been normalized (Normal i zed). It can be seen from Fig. 2 that the capacitance modulation range can reach about 70% in the range of such a large drop of 0.5V~2.5V, which is compared with the modulation of the capacitance of the conventional junction variable capacitor. The range is only 40%, and the variable capacitor of the present invention does have a large modulation range 'and its voltage also has a large modulation range. [Second Embodiment] FIG. 3 is a cross-sectional view showing a differential variable capacitor according to a preferred embodiment of the present invention, which is a variation application of a variable capacitor of the first embodiment. . Referring to FIG. 3, the differential variable capacitor of the present invention is composed of at least one pair of capacitors 200 disposed on the n-type substrate 2〇2, and each pair of variable capacitors 2〇〇 includes a variable capacitor. 2 0 4a and variable capacitor 2 0 4b. Wherein the 'variable capacitor 2〇4a includes two gate structures 2〇8a, 210a, a p-type doping region 212a, and an n-type doping region 216a. In a preferred embodiment, the variable capacitor 2 0 4a further includes a p-type lightly doped region 214a, a light-doped region 218a, a spacer 220a, and a deuterated metal layer 222a. Wherein, the two gate structures 2 0 8 a and 21 〇a are disposed on the n-type substrate 220, and each of the gate structures 2〇8a, 21〇a is a lower gate dielectric layer 2 24a It is composed of a gate conductive layer 2 2 6 a of the upper layer. Moreover, the two gate structures 2 0 8 a and 2 10a may be disposed on the n-type substrate 2〇2, or may be disposed on an ip-type substrate having an n-type well region (not shown) (not shown) )on. In addition, the material of the gate dielectric layer 2 24a is, for example, tantalum oxide, tantalum nitride or other suitable dielectric material, and the material of the interlayer conductive layer 2 26a is, for example, polycrystalline germanium.

Page 12 12868twf1.ptc 1247362 --- Case 93108623⁄4__ Year Month_Day Revision V. Description of the invention (8) Doped polysilicon or other suitable conductive material. Further, a p-type doping region 2 1 2 a is disposed in the n-type substrate 2〇2 between the two gate structures 2 0 8 a and 210a, and the two gate structures 2〇8a and 210a are shared. This p-type doped region 212a. In a preferred embodiment, a p-type lightly doped region is further disposed between the n-type substrate 202 and the p-type doped region 2 1 2 a under the two gate structures 2〇8& and 21〇3. 2 1 4 a. Further, the n-type doping region 216a is disposed in the ?-type substrate 2? 2 of the other side of the two gate structures 208a and 210a where the p-type doping region 212a is not disposed. In a preferred embodiment, an n-type light doped region 2 18 a is disposed between the n-type substrate 202 and the n-type doped region 216a further under the two gate structures 2 〇 8a and 210a. In a preferred embodiment, the spacers 22a are disposed on the sidewalls of the two gate structures 2 〇 8a and 210a, and the spacers 22 〇 a cover the p-type lightly doped regions 2 1 4 a And the n-type lightly doped region is 2 18 a. In another preferred embodiment, a further comprising a deuterated metal layer 2 2 2 a is disposed on the gate conductive layer 226a of the two gate structures 208a and 210a and the p-doped region 212a and the n-type doping The impurity region 2 1 6 a is used to reduce the resistance values of the two gate structures 2 〇 8 a and 2 1 0 a, the p-type doping region 212a and the n-type doping region 216a, thereby increasing the conductivity. In addition, another variable capacitor 204b is adjacent to the variable capacitor 204a, and the variable capacitor 2 0 4b includes two gate structures 2 〇 8 b, 210b, a p-type doping region 212b, and an n-type doping. Zone 216b. In a preferred embodiment, the variable capacitor 204b further includes a p-type lightly doped region 214b, an n-type lightly doped region 2 18b, a spacer 2 2 0 b and a deuterated metal layer 2 2 2 b. Each of the gate structures 2 0 8b and 21 Ob is composed of a lower gate dielectric layer 2 2 4b and an upper gate.

12868twf1.ptc Page 13 1247362 __号号 93108629_年月日日_____ V. Description of invention (9) Electrical layer 226b. Further, the n-type doping region 2 16b of the variable capacitor 204b is adjacent to the n-type doping region 21 6a of the variable capacitor 2 0 4a, and thus can be regarded as the same doping region. Further, the arrangement relationship of the other related members of the variable capacitor 2 0 4b is the same as that of the variable capacitor 204a, and will not be described again. The variable capacitor described above is in particular divided by m, and the device is configured to be electrically connected to a modulation voltage terminal 22g, and the variable capacitor 2 0 4 The gate structure 2 〇8 b, 2 1 0 b and its p-type doping region 2 12b are electrically connected to a relatively modulated voltage terminal “ο. Therefore, the mutual voltage and the relative modulation voltage are mutually Under the action, the n-type doping regions 216a and 216b between the modulation voltage and the opposite modulation voltage terminal 230 are combined. The 13-differential 1 variable capacitor will have a lower value, and ... mouth mouth (Q Factor) can be improved by this. The variable capacitor in the dynamic example, this difference is 2 1〇a U ^2 0 83 ' 2〇8b ' _, (10) and n-type doped containers. Therefore, this difference The characteristics of the variable-type variable-capacitor based on the variable-type variable-crossing. In other words, the differential 糸=日守 has the two kinds of variable-electric MOS variable capacitors or the <-type variable capacitors The ability to know, and the capacitance and voltage of the capacitor have a better charge storage. Although the invention has been better implemented; J ^: modulation range. Limit the invention, any familiarity J exposing art, as described above, and they are not intended in a range, when the gray cover modifications may be made without t little from the spirit and scope of the present invention when the scope of the appended claims which are given by: J protection of the present invention

Brief Description of the Drawings Fig. 1 is a schematic cross-sectional view of a variable capacitor in accordance with a preferred embodiment of the present invention. 2 is a graph showing the relationship between capacitance and voltage of a variable capacitor in accordance with a preferred embodiment of the present invention. Figure 3 is a cross-sectional view of a differential variable capacitor in accordance with a preferred embodiment of the present invention. 4 is a cross-sectional view of a variable capacitor in accordance with another embodiment of the present invention. [Description of Patterns] 1 00, 2 0 2 : n-type substrates 102, 104, 2 0 8 a, 210a, 2 0 8b, 210b: gate structures 106, 212a, 212b: p-type doped regions 108, 214a 214b: p-type lightly doped regions 110, 216a, 216b: n-type doped regions 112, 218a, 218b: n-type lightly doped regions 1 1 4, 2 2 0 a, 2 2 0 b: spacers 116, 222a, 222b: deuterated metal layers 118, 224a, 224b: gate dielectric layer 1 2 0, 2 2 6 a, 2 2 6 b: gate conductive layer 122: anode 124: cathode 2 0 0 : one pair of Variable capacitor 2 04a , 2 0 4b : Variable capacitor: 2 28 : Modulated voltage terminal

12868twf1.ptc Page 15 1247362 Case No. 93108629 Year Month Correction Simple description of the diagram 2 3 0 : Relative modulation voltage terminal 232 : Grounding mi Page 16 12868twf1.ptc

Claims (1)

1247362 _ Case No. 93108629_年月日日__ VI. Patent Application Range 1· A variable capacitor (Varactor) comprising: a first type substrate; a second gate structure disposed on the first type substrate, and each The gate structure is composed of a gate dielectric layer of the lower layer and a gate conductive layer of the upper layer; a first type doped region disposed in the first type substrate between the two gate structures; a second type doping region is disposed in the first type substrate of the two gate structures not disposed on the other side of the first type doping region, wherein the first type doping region is electrically connected Up to a first electrode end, wherein the second type doping region is electrically connected to a second electrode end, and the two gate structures are electrically connected to the first electrode end and the second electrode end connection. 2. The variable capacitor of claim 1, wherein the first type doped region is a p-type doped region and the second type doped region is an n-type doped region. 3. The variable capacitor of claim 1, wherein the first doped region is an n-type doped region and the second doped region is a p-type doped region. 4. The variable capacitor of claim 1, further comprising a deuterated metal layer disposed on the gate conductive layer, the first doped region and the second doped region. 5. The variable capacitor of claim 1, further comprising: a first type of lightly doped region disposed under each of the gate structures 12868twf1.ptc Page 17 1243732 Case No. 93108629 Revised on the sixth day of the year. Patent application range: Type 1 substrate and a second type substrate and 6 · If the gap is a gap, the lightly doped area and the 7·Varactor) At least the container includes: a first pole, a first two-pole electric gate, and a first pole of the first gate, and a second pole; And the first type of doped regions; and the lightly doped regions are disposed between the second doped regions below the gate structures. The variable capacitor of claim 5, further comprising a sidewall disposed on each of the gate structures and covering the first type of the second type of lightly doped regions. a differential variable capacitor (differential) consisting of a variable capacitor disposed in a pair of first type bases, wherein each pair of variable electric variable capacitors, the first variable The capacitor includes: a first gate structure disposed on the first type substrate, and each structure is formed by a first gate dielectric layer of the lower layer and a first layer of the upper layer; the first type first doped region, Disposed in the first substrate of the first gate structure; and the first doped region of the second type is disposed on the other side of the first doped region of the first gate structure a type substrate variable capacitor adjacent to the first variable capacitor, and the container comprises: a second gate structure disposed on the first type substrate, and each structure is formed by a second gate dielectric layer of the lower layer And the first layer of the upper layer; 12868twf1.ptc Page 18 1247362 Case No. 93108629 Year of the month Correction of the construction of the pole gate II The second in the allocation area Miscellaneous Type II First Division One Fanli Special Application Shen 6 Construction Extreme Gate Second Second The arrangement and the area are miscellaneous, the second base of the second type, the second type, the first base of the first one, the first side, the other side, the adjacent area, the doped area, the doped first type, the first type The second type has the first set and the match, and the second type of the second type of the first type is mixed with the first and the first, and the type of the junction is connected to the second gate. The change and the first configuration of the pair of junctions and the phase poles, the gates to the crimping of the first electrical connection of the denaturation, in the power adjustment, the system is connected to the inter-connected mixed-connected regions. The second division of the 3⁄4 Fan Erlidi specializes in the application and the application of the district such as 隹. 砉8 掺 容 容 容 容 容 所 所 所 掺 掺 掺 掺 掺 掺 掺 掺 掺 掺 掺 掺 掺 掺 掺 掺 掺 掺 掺 掺The first type of the second type and the doping of the area and the doped region are mixed with the first type, the second type, the first one, and the middle portion of the miscellaneous device has a difference of 1^00.专 专 专 — — — — — — — — — — — — — I I I I I I I I I I I I I I I I I I I I I I I I — — — In the meantime, the miscellaneous type of the middle zone is the zone impurity. 10. Including the inclusion type, please apply for the Arc IL, the layer is the first, and the gate is the second. The first part of the electric conduction differential is described as the second impurity. The first type region is mixed with the second type, the second type is mixed with the first type, and the first type and the first type are mixed with the first layer and the second type of the second type of the second electrode. The electrical structure of the device can be changed to the pole of the gate. The difference between the two is the same as that of the first section. 12868twf1.ptc Page 19 1243732 _ Case No. 93108629_年月日日__ 6. Patent application area between the first type substrate and each of the first type first doped regions; and a second type light doped region And disposed between the first type substrate and the second type first doped region under the first gate structure. 1 . The differential variable capacitor of claim 1 , further comprising a spacer disposed on a sidewall of each of the first gate structures and covering the first type of lightly doped region and The second type of lightly doped region. The differential variable capacitor of claim 7, further comprising: a first type of lightly doped region, the first type of substrate disposed under each of the second gate structures and the Between the first type of second doped regions; and a second type of lightly doped regions disposed between the first type of substrate and the second type of second doped regions below each of the second gate structures. The differential variable capacitor of claim 13 further comprising a spacer disposed on a sidewall of each of the second gate structures and covering the first type of lightly doped region and The second type of lightly doped region. 12868twf1.ptc Page 20