TWI855639B - Semiconductor structure having heat dissipation structure - Google Patents

Abstract

A semiconductor structure is provided. The semiconductor structure includes a first substrate, a first dielectric layer disposed on the first substrate, a first passivation layer disposed on the first dielectric layer, a second substrate disposed on the first passivation layer, and a second substrate disposed on the first passivation layer. The semiconductor structure further includes a first seal ring embedded within the first dielectric layer and surrounds a circuit region of the first dielectric layer. The semiconductor structure further includes a thermal conductive structure embedded within the first passivation layer, wherein the thermal conductive structure is connected with the first seal ring through a first connecting structure.

Description

Semiconductor structure with heat dissipation structure

This application claims priority to U.S. Patent Application Nos. 17/857,223 and 17/857,752 (i.e., priority date is July 5, 2022), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure with a heat dissipation structure.

3D stacked chip packages present challenges in terms of heat dissipation. For example, 3D stacked integrated circuit (IC) packages, such as high-bandwidth memory (HBM), may include the application of thermal interface materials (TIM) between stacked chips and/or cavities between the die for lateral heat dissipation. Because each die within a 3D stacked chip package requires individual consideration, it is desirable to establish a heat dissipation path for each die to achieve robust heat dissipation and device reliability.

The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present case.

One aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first substrate, a first dielectric layer disposed on the first substrate, a first passivation layer disposed on the first dielectric layer, and a second substrate disposed on the first passivation layer. The semiconductor structure also includes a first sealing ring embedded in the first dielectric layer and surrounding a circuit region of the first dielectric layer. The semiconductor structure also includes a heat conductive structure embedded in the first passivation layer and connected to the first sealing ring through a first connection structure.

Another aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first chip having a first dielectric layer and a first substrate; and a second chip bonded to the first chip and having a first passivation layer and a second substrate, wherein the second chip includes a heat sink structure in contact with a first sealing ring, and the first sealing ring is embedded in the first dielectric layer of the first chip.

Another aspect of the present disclosure provides a method for preparing a semiconductor structure with a heat dissipation structure. The preparation method includes forming a heat-conducting structure embedded in a first passivation layer of a first chip, and forming a plurality of conductive vias to penetrate a first substrate of the first chip and contact the heat-conducting structure. The preparation method also includes forming a first connecting structure that contacts the heat-conducting structure and is exposed by a surface of the first passivation layer. The preparation method further includes bonding the first connecting structure of the first chip to a second connecting structure of the second chip, and bonding the first passivation layer of the first chip to the first dielectric layer of the second chip, wherein a first sealing ring embedded in the first dielectric layer of the second chip is thermally connected to the heat-conducting structure through the first connecting structure and the second connecting structure.

In the semiconductor structure proposed in the present disclosure, a heat dissipation structure for a three-dimensional stacked chip package or a wafer-on-wafer structure includes a sealing ring for each chip. The proposed heat dissipation structure provides an effective heat dissipation path for each chip in the three-dimensional stacked chip package or the wafer-on-wafer structure without introducing additional components or complex structures. At the same time, the proposed heat dissipation structure also increases the function of the existing sealing ring. That is, in addition to the inherent function of the sealing ring (i.e., preventing unexpected stress from propagating into the semiconductor element), the proposed heat dissipation structure also utilizes the sealing ring for heat conduction and heat dissipation. The proposed heat dissipation structure also enhances the structural stability of the three-dimensional stacked chip package or the wafer-on-wafer structure.

The above has been a fairly broad overview of the technical features and advantages of the present disclosure so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application scope of the present disclosure will be described below. Those with ordinary knowledge in the art to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the art to which the present disclosure belongs should also understand that such equivalent constructions cannot deviate from the spirit and scope of the present disclosure as defined by the attached patent application scope.

The embodiments, or examples, of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as would be routinely made by one of ordinary skill in the art to which the present disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment are applicable to another embodiment, even if they share the same reference numeral.

It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, or portions, these elements, components, regions, layers, or portions are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion without departing from the teachings of the present inventive concept.

The terms used herein are used only to describe specific embodiments and are not intended to limit the concepts of the present invention. As used herein, the singular forms "a", "an", and "the" also include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms "comprise" and "include", when used in this specification, indicate the presence of the features, integers, steps, operations, elements, or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

FIG. 1A is a top view illustrating a portion of a semiconductor structure according to some embodiments of the present disclosure.

1A is a top view 100a of a portion of a semiconductor structure, showing components/elements that may be included in two layers of a stacked IC package. The top view 100a includes a dielectric layer d1, sealing rings r1 and r2 embedded in the dielectric layer d1, and a thermally conductive structure 10a disposed above the dielectric layer d1.

The thermally conductive structure 10a includes ridges x1, x2, x3, x4, x5, and x6 extending in the x-direction. The ridges x1, x2, x3, x4, x5, and x6 are substantially parallel. The ridges x1, x2, x3, x4, x5, and x6 may also be referred to as strips or extensions. Although FIG. 1A shows six ridges, it is contemplated that the thermally conductive structure 10a may include more than six ridges, or any number between one and six ridges.

The thermally conductive structure 10a may include a material having a relatively high thermal conductivity. In some embodiments, the thermally conductive structure 10a may include, for example, but not limited to, silver (Ag), copper (Cu), gold (Au), aluminum nitride (AlN), silicon carbide (SiC), aluminum (Al), tungsten (W), zinc (Zn), or any combination thereof.

One or more conductive vias may be disposed in contact with the thermal conductive structure 10a. For example, conductive vias v1, v2, and v3 may be disposed in contact with the thermal conductive structure 10a.

The sealing ring r1 surrounds the periphery of the dielectric layer d1. The sealing ring r2 surrounds the periphery of the dielectric layer d1. The sealing ring r2 is surrounded by the sealing ring r1.

The sealing rings r1 and r2 may surround semiconductor elements (not shown) disposed in an active region of a wafer, for example, the sealing rings r1 and r2 may surround the circuit region A1. By surrounding the active region with the sealing rings, it is possible to prevent unexpected stress from being propagated into the semiconductor elements during a chemical mechanical polishing (CMP) or dicing process, and thus prevent cracking of a layer in which the semiconductor elements are embedded and/or delamination between adjacent layers of a stacked IC package. The sealing rings r1 and r2 may prevent stress from being propagated into the semiconductor elements in the circuit region A1.

The sealing rings r1 and r2 may include copper (Cu) or any other suitable material. In some embodiments, the sealing rings r1 and r2 may each include a multi-layer structure. In some embodiments, the sealing rings r1 and r2 may each include a barrier metal layer (not shown) that encapsulates the sealing rings r1 and r2 skeletons. In some embodiments, the barrier metal layer may include, for example, but not limited to, tungsten (Ta), tungsten nitride (TaN), tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), titanium (Ti), titanium nitride (TiN), and titanium silicon nitride (TiSiN).

The ridges x2, x3, x4 and x5 may intersect the sealing rings r1 and r2 respectively from a top view. The ridges x1 and x6 may partially overlap the sealing ring r2 from a top view.

Although not shown in FIG. 1A , ridge x1 may be connected to sealing rings r1 and r2 via interlayer connections. Similarly, ridges x2, x3, x4, x5, and x6 may be connected to sealing rings r1 and r2 via interlayer connections. In some embodiments, ridges x1, x2, x3, x4, x5, and x6 may be electrically connected to sealing rings r1 and r2. In some embodiments, ridges x1, x2, x3, x4, x5, and x6 may be thermally connected to sealing rings r1 and r2.

FIG. 1B is a top view illustrating a portion of a semiconductor structure according to some embodiments of the present disclosure.

FIG1B is a top view 100b of a portion of a semiconductor structure. The top view 100b shows components/elements that may be included in two layers of a stacked IC package. The top view 100b includes a dielectric layer d1, sealing rings r1 and r2 embedded in the dielectric layer d1, and a thermally conductive structure 10b disposed above the dielectric layer d1.

The thermally conductive structure 10b includes ridges x1, x2, x3, x4, x5 and x6 extending in the x direction. The ridges x1, x2, x3, x4, x5 and x6 are substantially parallel. The thermally conductive structure 10b also includes ridges y1, y2, y3, y4, y5, y6, y7 and y8 extending in the y direction. The ridges y1, y2, y3, y4, y5, y6, y7 and y8 are substantially parallel. The ridges x1, x2, x3, x4, x5 and x6 may be substantially perpendicular to the ridges y1, y2, y3, y4, y5, y6, y7 and y8. The ridges x1, x2, x3, x4, x5 and x6 may also be referred to as stripes or extensions. Ridges y1, y2, y3, y4, y5, y6, y7 and y8 may also be referred to as strips or extensions.

Although FIG. 1B shows six ridges extending along the x-direction and eight ridges extending along the y-direction, it is contemplated that the thermally conductive structure 10b may include any other number of ridges extending along the x-direction, and any other number of ridges extending along the y-direction.

The thermally conductive structure 10b may include a material having a relatively high thermal conductivity. The thermally conductive structure 10b may include a material similar to the thermally conductive structure 10a.

Ridges x2, x3, x4 and x5 may intersect sealing rings r1 and r2, respectively, from a top view. Ridges x1 and x6 may overlap partially with sealing ring r2, from a top view. Ridges y2, y3, y4, y5, y6 and y7 may intersect sealing rings r1 and r2, respectively, from a top view. Ridges y1 and y8 may overlap partially with sealing ring r2, from a top view.

Although not shown in Figure 1B, the ridge x1 can be connected to the sealing rings r1 and r2 through interlayer connections. Similarly, the ridges x2, x3, x4, x5 and x6 can be connected to the sealing rings r1 and r2 through interlayer connections.

Although not shown in Figure 1B, ridge y1 can be connected to sealing rings r1 and r2 through interlayer connections. Similarly, ridges y2, y3, y4, y5, y6, y7 and y8 can be connected to sealing rings r1 and r2 through interlayer connections.

In some embodiments, ridges x1, x2, x3, x4, x5, and x6 may be electrically connected to sealing rings r1 and r2. In some embodiments, ridges x1, x2, x3, x4, x5, and x6 may be thermally connected to sealing rings r1 and r2. In some embodiments, ridges y1, y2, y3, y4, y5, y6, y7, and y8 may be electrically connected to sealing rings r1 and r2. In some embodiments, ridges y1, y2, y3, y4, y5, y6, y7, and y8 may be thermally connected to sealing rings r1 and r2.

The ridges x1, x2, x3, x4, x5 and x6 and the ridges y1, y2, y3, y4, y5, y6, y7 and y8 may together form a mesh structure. The heat conductive structure 10b may include a mesh profile.

FIG2 is a cross-section of a semiconductor structure according to some embodiments of the present disclosure. FIG2 shows a semiconductor structure 200. The semiconductor structure 200 may correspond to a cross-section along the dashed line SS' shown in FIG1A.

Semiconductor structure 200 includes chips CW1, DW1, and DW2. Chips CW1, DW1, and DW2 can be vertically stacked. Chip CW1 can be bonded to chip DW1 using a hybrid bond. Chip DW1 can be bonded to chip DW2 using a hybrid bond. The hybrid bond can use an adhesive such as polyimide, heat pressing, diffusion bonding, pressure bonding, etc. to form metal-to-metal, insulator-to-insulator, and metal-to-insulator bonds to achieve a vertically stacked chip.

In the present disclosure, "chip" or "semiconductor chip" may refer to any type and shape of substrate on which semiconductor elements are formed. Chips DW1 and DW2 may be bonded in a "face-to-back" manner. Generally, one side of the substrate may be referred to as the back side of the chip, and the other side on which the semiconductor elements are formed may be referred to as the surface of the chip. That is, the surface of chip DW2 is bonded to the back side of chip DW1.

The chip CW1 can be referred to as a carrier chip. The chip CW1 includes a substrate s1 and a passivation layer p1. The chip CW1 includes a thermally conductive structure 10a embedded in the passivation layer p1. The passivation layer p1 can be one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics (such as carbon-doped oxides), ultra-low-k dielectrics (such as porous carbon-doped silicon dioxide), combinations thereof, or similar materials. The manufacturing technology of the passivation layer p1 can be, for example, a chemical vapor deposition (CVD) process, although any suitable process can be used, and its thickness can be between about 0.5μm and about 5μm, such as about 9.25kÅ.

Wafer CW1 includes conductive vias v1, v2 and v3 embedded in substrate s1. Conductive vias v1, v2 and v3 may each be referred to as through-silicon vias (TSVs). Conductive vias v1, v2 and v3 penetrate substrate s1, respectively. Referring to FIG. 2 , conductive via v1 includes an end v1a exposed by surface s1a of substrate s1. Conductive via v1 includes an end v1b embedded in passivation layer p1. End v1b of conductive via v1 contacts thermal conductive structure 10a. Conductive via v1 falls on thermal conductive structure 10a through end v1b. Referring to FIG. 2 , end v1b of conductive via v1 may protrude from surface s1b of substrate s1. End v1b of conductive via v1 may not be coplanar with surface s1b.

The end v1a exposed by the surface s1a of the substrate s1 can promote the dissipation of the accumulated heat of the semiconductor structure 200. The exposed surfaces of the plurality of TSVs embedded in the substrate s1 can promote the dissipation of the accumulated heat of the semiconductor structure 200.

Similarly, the conductive via v2 includes an end v2a exposed by the surface s1a of the substrate s1. The conductive via v2 includes an end v2b embedded in the passivation layer p1. The end v2b of the conductive via v2 contacts the thermal conductive structure 10a. The conductive via v2 lands on the thermal conductive structure 10a through the end v2b.

The heat conducting structure 10 a and all the conductive vias embedded in the substrate s1 may be collectively referred to as a heat dissipation structure 20 .

The chip DW1 can be called a component chip. The chip DW1 includes a substrate s2, a dielectric layer d1, and a passivation layer p2. The chip DW1 includes sealing rings r1, r2, r3, r4, r5, and r6 embedded in the dielectric layer d1. The sealing rings r1 and r2 can be set at the same height. The sealing rings r3 and r4 can be set at the same height. The sealing rings r5 and r6 can be set at the same height. The sealing ring r3 is farther from the heat-conducting structure 10a than the sealing ring r1. The sealing ring r5 is farther from the heat-conducting structure 10a than the sealing ring r3. The sealing ring r4 is farther from the heat-conducting structure 10a than the sealing ring r2. The sealing ring r6 is farther from the heat conducting structure 10a than the sealing ring r4.

The sealing ring r1 can be connected to the sealing ring r3. The sealing ring r2 can be connected to the sealing ring r4. The sealing ring r3 can be connected to the sealing ring r5. The sealing ring r4 can be connected to the sealing ring r6.

For example, the sealing ring R1 can be connected to the sealing ring R3 through the connecting structure C5. The sealing ring R2 can be connected to the sealing ring R4 through the connecting structure C6. The sealing ring R3 can be connected to the sealing ring R5 through the connecting structure therebetween. The sealing ring R4 can be connected to the sealing ring R6 through the connecting structure therebetween. In some embodiments, the connecting structure C5 and the connecting structure C3 can be coaxial. In some embodiments, the connecting structure C6 and the connecting structure C4 can be coaxial.

The sealing rings r1, r3 and r5 can be electrically connected through the connection structure between them. The sealing rings r1, r3 and r5 can be thermally connected through the connection structure between them. The sealing rings r2, r4 and r6 can be electrically connected through the connection structure between them. The sealing rings r2, r4 and r6 can be thermally connected through the connection structure between them.

The sealing rings r1, r3 and r5 can be electrically connected to the heat-conducting structure 10a through the connecting structures c1 and c3. The sealing rings r1, r3 and r5 can be thermally connected to the heat-conducting structure 10a through the connecting structures c1 and c3. The connecting structures c1 and c3 can be collectively referred to as a connecting structure.

The sealing rings r2, r4 and r6 can be electrically connected to the heat-conducting structure 10a through the connecting structures c2 and c4. The sealing rings r2, r4 and r6 can be thermally connected to the heat-conducting structure 10a through the connecting structures c2 and c4. The connecting structures c2 and c4 can be collectively referred to as a connecting structure.

In some embodiments, the connection structure c1 and the conductive via v1 may be coaxial. In some embodiments, the connection structure c3 and the conductive via v1 may be coaxial. In some embodiments, the connection structure c2 and the conductive via v2 may be coaxial. In some embodiments, the connection structure c4 and the conductive via v2 may be coaxial.

Wafer DW1 includes a circuit area A1 embedded in a dielectric layer d1. Circuit area A1 may include active components, passive components, wires and/or interconnects. Circuit area A1 may include a multi-layer structure. Circuit area A1 may be surrounded by sealing rings r1, r2, r3, r4, r5 and r6. Sealing rings r1, r2, r3, r4, r5 and r6 may prevent stress from propagating to semiconductor components in circuit area A1.

The wafer DW1 includes conductive vias v4 and v5 embedded in the substrate S2. The conductive vias v4 and v5 may penetrate the substrate s2. The conductive vias v4 and v5 may be respectively referred to as through-silicon vias (TSVs). The conductive vias v4 and v5 may each include one end embedded in the dielectric layer d1 and the other end embedded in the passivation layer p2.

The chip DW2 may be referred to as a device chip. The chip DW2 includes a substrate s3, a dielectric layer d2, and passivation layers p3, p4, and p5.

The chip DW2 includes sealing rings r7, r8, r9, r10, r11 and r12 embedded in the dielectric layer d2. The sealing rings r7 and r8 can be arranged at the same height. The sealing rings r9 and r10 can be arranged at the same height. The sealing rings r11 and r12 can be arranged at the same height.

The sealing rings R7, R9 and R11 can be electrically connected through the connection structure between them. The sealing rings R7, R9 and R11 can be thermally connected through the connection structure between them. The sealing rings R8, R10 and R12 can be electrically connected through the connection structure between them. The sealing rings R8, R10 and R12 can be thermally connected through the connection structure between them.

The sealing ring of the element wafer DW2 can be connected to the sealing ring of the element wafer DW1. The sealing ring of the element wafer DW2 can be thermally connected to the sealing ring of the element wafer DW1. For example, the sealing rings r7, r9 and r11 can be connected to the sealing rings r1, r3 and r5 through the conductive via v4 and the connection structure c7.

The sealing ring of the device wafer DW2 may be thermally connected to the thermally conductive structure 10a, for example, via conductive vias embedded in the substrate s2, the sealing ring of the device wafer DW1, and connection structures in the dielectric layer d1 and the passivation layer p1.

Wafer DW2 includes a circuit area A2 embedded in a dielectric layer d2. Circuit area A2 may include active components, passive components, wires and/or interconnects. Circuit area A2 may include a multi-layer structure. Circuit area A2 may be surrounded by sealing rings r7, r8, r9, r10, r11 and r12. Sealing rings r7, r8, r9, r10, r11 and r12 may prevent stress from propagating to semiconductor components in circuit area A2.

The semiconductor elements in the circuit area A2 can be electrically connected to the elements in the circuit area A1 through the conductive vias v5 embedded in the substrate S2.

Wafer DW2 includes conductive vias v6 and v7 embedded in substrate s3. Conductive vias v6 and v7 may penetrate substrate s3. Conductive vias v6 and v7 may be respectively referred to as through-silicon vias (TSV). Conductive vias v6 and v7 may each include one end embedded in dielectric layer d2 and the other end embedded in passivation layer p4.

The chip DW2 also includes a plurality of conductive bumps b1 partially embedded in the passivation layer p5. Some of the conductive bumps b1 can be configured to transmit/receive signals to/from the circuit areas A1 and/or A2. Some of the conductive bumps b1 can be part of a signal transmission path of the semiconductor structure 200. Some of the conductive bumps b1 can be part of a heat conduction path of the semiconductor structure 200.

FIG. 3A is a schematic diagram illustrating a semiconductor structure of some embodiments of the present disclosure. FIG. 3A shows a semiconductor structure 120a. The semiconductor structure 120a may be part of a three-dimensional stacked chip package or a wafer-on-wafer structure. The semiconductor structure 120a may be a heat dissipation structure of a three-dimensional stacked chip package or a wafer-on-wafer structure. The semiconductor structure 120a includes a thermally conductive structure 10a, conductive vias v1, v2, v12, and v13, sealing rings r1 and r2, and connection structures c1, c2, c3, and c4.

The heat-conducting structure 10a includes ridges x1, x2, x3, x4, x5 and x6 extending along the x-direction. The ridges x1, x2, x3, x4, x5 and x6 may be spaced apart from each other by a certain distance T1. In some embodiments, the distance between each ridge x1, x2, x3, x4, x5 and x6 may be adjusted according to design requirements. The ridges of the conductive structure 10a are conducive to relatively uniform heat conduction, thereby improving the efficiency of heat dissipation. The ridges may also enhance the structural stability of the heat-conducting structure 10a.

3A, conductive vias v1, v2, v12, and v13 fall on ridge x2. Although a specific number (i.e., 4) of conductive vias are shown falling on a single ridge in the present embodiment, it is contemplated that the number of conductive vias on a single ridge may be adjusted according to design needs. In some embodiments, a single ridge of the thermally conductive structure 10a may include more than four conductive vias mounted thereon. In some embodiments, a single ridge of the thermally conductive structure 10a may include less than four conductive vias mounted thereon.

The sealing rings r1 and r2 may be connected via the thermally conductive structure 10a. For example, the sealing rings r1 and r2 may be connected to the thermally conductive structure 10a via the ridges x2 and the connecting structures c1, c2, c3, and c4. In some embodiments, each ridge of the thermally conductive structure 10a may be connected to the sealing rings r1 and r2. In other embodiments, only some of the ridges of the thermally conductive structure 10a are connected to the sealing rings r1 and r2.

The heat conducting structure 10a, all the conductive vias, all the sealing rings and all the connecting structures shown in FIG. 3A can jointly play the role of a heat dissipation structure.

FIG. 3B is a schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure.

FIG3B shows a semiconductor structure 120b. The semiconductor structure 120b may be a part of a three-dimensional stacked chip package or a chip-on-chip structure. The semiconductor structure 120b may be a heat dissipation structure of a three-dimensional stacked chip package or a chip-on-chip structure. The semiconductor structure 120b includes a heat-conducting structure 10b, a plurality of conductive vias located on the heat-conducting structure 10b, sealing rings r1 and r2, and a plurality of connection structures disposed between the heat-conducting structure 10b and the sealing rings r1 or r2.

The thermally conductive structure 10b includes ridges x1, x2, x3, x4, x5, and x6 extending along the x-direction. The ridges x1, x2, x3, x4, x5, and x6 may be spaced a certain distance apart from one another. In some embodiments, the distance between each of the ridges x1, x2, x3, x4, x5, and x6 may be adjusted as required by the design. Although a specific number (i.e., 6) of ridges extending along the x-direction are shown in the present embodiment, it is contemplated that the number of ridges extending along the x-direction may be adjusted as required by the design.

The thermally conductive structure 10b includes ridges y1, y2, y3, y4, y5, y6, y7, and y8 extending in the y-direction. The ridges y1, y2, y3, y4, y5, y6, y7, and y8 may be spaced a certain distance apart from one another. In some embodiments, the distance between each of the ridges y1, y2, y3, y4, y5, y6, y7, and y8 may be adjusted as required by the design. Although a specific number (i.e., 8) of ridges are shown extending in the y-direction in the present embodiment, it is contemplated that the number of ridges extending in the y-direction may be adjusted as required by the design.

The ridges x1, x2, x3, x4, x5 and x6 and the ridges y1, y2, y3, y4, y5, y6, y7 and y8 together form a mesh profile. The thermal conductive structure 10b includes a mesh profile. The mesh profile of the thermal conductive structure 10b is conducive to relatively uniform heat conduction, thereby improving heat dissipation efficiency. The mesh profile can also improve the structural stability of the thermal conductive structure 10b.

The heat conducting structure 10b includes a plurality of intersections. For example, the ridge y2 intersects with the ridge x2 at the intersection i1, the ridge y2 intersects with the ridge x3 at the intersection i2, the ridge y3 intersects with the ridge x2 at the intersection i3, and the ridge y3 intersects with the ridge x3 at the intersection i4.

FIG. 3C is a schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure.

FIG3C shows a semiconductor structure 120c. The semiconductor structure 120c may be a part of a three-dimensional stacked chip package or a chip-on-chip structure. The semiconductor structure 120c may be a heat dissipation structure of a three-dimensional stacked chip package or a chip-on-chip structure. The semiconductor structure 120c includes a thermally conductive structure 10b, a plurality of conductive vias (e.g., v2 and v3) located on the thermally conductive structure 10b, sealing rings r1 and r2, and a plurality of connection structures disposed between the thermally conductive structure 10b and the sealing rings r1 or r2.

The semiconductor structure 120c includes a plurality of conductive vias disposed at the intersections of the thermally conductive structure 10b. For example, the semiconductor structure 120c may include a conductive via v2 disposed at the intersection i1, and a conductive via v3 disposed at the intersection i3. In the present embodiment, all of the conductive vias are disposed at the intersections of the thermally conductive structure 10b. Nevertheless, it is contemplated that the locations of the conductive vias on the thermally conductive structure 10b may be adjusted according to design requirements. That is, the thermally conductive structure 10b may include one or more conductive vias disposed at locations other than the intersections.

FIG4 is a cross-sectional view illustrating a semiconductor structure of some embodiments of the present disclosure. FIG4 shows a semiconductor structure 300. The semiconductor structure 300 may correspond to a cross-section of a three-dimensional stacked chip package or a chip-on-chip structure. The semiconductor structure 300 includes vertically stacked chips CW1, DW1, DW2, DW3, and DW4.

The chip CW1 may be referred to as a carrier chip. The chip CW1 includes a plurality of through silicon vias (TSVs) and a thermal conductive structure 10 a. The TSVs (eg, conductive vias v1 ) and the thermal conductive structure 10 a may be collectively referred to as a heat sink structure 20 .

Chip DW1 can be called a component chip. Chip DW1 includes a circuit area A1 surrounded by a sealing ring structure R1. Chip DW1 can be bonded to chip CW1 using a hybrid bonding method. Chip DW2 can be called a component chip. Chip DW2 includes a circuit area A2 surrounded by a sealing ring structure R2. Chip DW2 can be bonded to chip DW1 using a hybrid bonding method. Chip DW2 can be bonded to chip DW1 in a "face-to-back" manner. Chip DW3 can be called a component chip. Chip DW3 includes a circuit area A3 surrounded by a sealing ring structure R3. Chip DW3 can be bonded to chip DW2 using a hybrid bonding method. Chip DW3 can be bonded to chip DW2 in a "face-to-back" manner. Chip DW4 can be called a component chip. The chip DW4 includes a circuit area A4 surrounded by a sealing ring structure R4. The chip DW4 can be bonded to the chip DW3 using a hybrid bonding method. The chip DW4 can be bonded to the chip DW3 in a "back-to-back" manner.

The heat dissipation structure 20 and the sealing ring structures R1, R2, R3 and R4 can together form a three-dimensional heat dissipation structure 30. The three-dimensional heat dissipation structure 30 can promote the dissipation of heat generated by the chips DW1, DW2, DW3 and DW4. The three-dimensional heat dissipation structure 30 can promote the dissipation of heat generated from the circuit areas A1, A2, A3 and A4 of the chips DW1, DW2, DW3 and DW4.

5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J, 5K, 5L, 5M, 5N, 5O, 5P, 5Q, 5R, 5S and 5T illustrate various stages of a method for preparing a semiconductor structure 200 according to some embodiments of the present disclosure.

5A, a substrate s1' is provided. In some embodiments, the substrate s1' may include a single crystal substrate, a semiconductor on insulator (SOI) substrate, a doped silicon bulk substrate, and an epitaxial on semiconductor (EPI) substrate, etc. In addition, although various embodiments may be described primarily with respect to materials and processes compatible with silicon-based semiconductor materials (e.g., silicon and alloys of silicon with germanium and/or carbon), the present disclosure is not limited thereto. Instead, various embodiments may be implemented using any type of semiconductor material.

5B , a plurality of TSVs (e.g., conductive vias v1 and v2) are formed. A portion of each TSV extends to the substrate s1′ and remains embedded in the substrate s1′. One end of each TSV is exposed by the substrate s1′. In some embodiments, one end of each TSV protrudes from the surface s1b of the substrate s1′. In some embodiments, each TSVs includes an end that is not coplanar with the surface s1b of the substrate s1′. In some embodiments, both ends of each TSV are not coplanar with the surface s1b of the substrate s1′.

The preparation of multiple TSVs may involve forming trenches on the substrate s1' by a dry etch. In the present disclosure, dry etching refers to removing material by exposing the material to a bombardment of ions, causing a portion of the material to move away from the exposed surface. In some embodiments, the ions may include but are not limited to fluorocarbons, oxygen, chlorine, or boron trichloride. In some embodiments, the addition of nitrogen, argon, helium, and other gases may also participate in the dry etching process.

5C , a passivation layer p1 having a thermally conductive structure 10a or 10b embedded therein may be formed on a substrate s1′. The passivation layer p1 may be one or more suitable dielectric materials, such as silicon oxide, silicon nitride, a low-k dielectric (such as a carbon-doped oxide), an ultra-low-k dielectric (such as porous carbon-doped silicon dioxide), a combination thereof, or the like. The passivation layer p1 may be fabricated using, for example, a chemical vapor deposition (CVD) process, although any suitable process may be used, and its thickness may be between about 0.5 μm and about 5 μm, such as about 9.25 kÅ.

The thermally conductive structure 10a or 10b contacts a plurality of TSVs (e.g., conductive vias v1 and v2). The thermally conductive structure 10a or 10b is thermally connected to a plurality of TSVs of the substrate s1'. In some embodiments, the thermally conductive structure 10a or 10b may include a plurality of ridges or strips. In some embodiments, the thermally conductive structure 10a or 10b may include a mesh profile.

Referring to FIG. 5D , one or more connection structures (e.g., connection structures c1 and c2) are formed in contact with the heat conductive structure 10a or 10b. In some embodiments, the connection structure is embedded in the passivation layer p1. One end of the connection structures c1 and c2 may be exposed by the surface p1a of the passivation layer p1. In some embodiments, the connection structure c1 and the conductive via v1 may be coaxial. In some embodiments, the connection structure c2 and the conductive via v2 may be coaxial. The semiconductor structure formed in the operation of FIG. 5D may be referred to as a chip CW1 '.

Referring to FIG. 5E , a chip is provided, including a substrate s2 ′ and a dielectric layer d1 disposed thereon. The dielectric layer d1 includes a circuit area A1 embedded therein and a sealing ring structure R1 surrounding the circuit area A1. The dielectric layer d1 may include a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer, or a dielectric layer made of other suitable dielectric materials, and the manufacturing technology of the dielectric layer d1 may be deposition or similar technology. In some embodiments, the dielectric layer d1 may include a multi-layer structure.

Referring to FIG5F, connection structures c3 and c4 are formed in contact with the sealing ring structure R1. Connection structures c3 and c4 are thermally connected to the sealing ring structure R1. One end of each of connection structures c3 and c4 is exposed by dielectric layer d1. The semiconductor structure obtained in the operation of FIG5F can be referred to as chip DW1'.

Referring to FIG. 5G , a chip is provided, including a substrate s3 ′ and a dielectric layer d2 disposed thereon. The dielectric layer d2 includes a circuit area A2 embedded therein and a sealing ring structure R2 surrounding the circuit area A2. The dielectric layer d2 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials, and the manufacturing technology of the dielectric layer d2 may be deposition or similar technology. In some embodiments, the dielectric layer d2 may include a multi-layer structure.

Referring to FIG. 5H , connection structures c7 and c8 are formed in contact with the sealing ring structure R2. Connection structures c7 and c8 are thermally connected to the sealing ring structure R2. One end of connection structures c7 and c8 is exposed by dielectric layer d2. In addition, connection structure c9 is formed in contact with at least one layer of circuit area A2. The semiconductor structure obtained in the operation of FIG. 5H can be referred to as chip DW2 '.

Referring to FIG. 5I , chip DW1′ and chip CW1′ are bonded together. Connecting structures c1 and c3 are in contact, and connecting structures c2 and c4 are in contact. Chip DW1′ may be bonded to chip CW1′ using a hybrid bond. The hybrid bond may use an adhesive such as polyimide, heat pressing, diffusion bonding, pressure bonding, etc. to produce metal-to-metal, insulator-to-insulator, and metal-to-insulator bonds to achieve a vertically stacked chip. Chips DW1′ and CW1′ may be bonded in a “face-to-face” manner.

5J , the semiconductor structure shown in the figure is obtained after the chip DW1 ′ and the chip CW1 ′ are bonded. The dielectric layer d1 of the chip DW1 ′ and the passivation layer p1 of the chip CW1 ′ are sandwiched by the substrates s1 ′ and s2 ′.

5K, the substrate s2' is thinned to form a substrate s2, and a passivation layer p2 is formed thereon. The thinning technique of the substrate s2' may be mechanical polishing, chemical mechanical polishing (CMP), wet etching, or atmospheric downstream plasma (ADP) dry chemical etching (DCE).

The passivation layer p2 may be one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics (such as carbon-doped oxides), ultra-low-k dielectrics (such as porous carbon-doped silicon dioxide), combinations thereof, or the like. The passivation layer p2 may be formed by a chemical vapor deposition (CVD) process, although any suitable process may be used, and its thickness may be between about 0.5 μm and about 5 μm, such as about 9.25 kÅ.

Referring to FIG. 5L , a plurality of trenches 8 are formed that penetrate the passivation layer p2 and the substrate s2. The plurality of trenches 8 may be referred to as a hole, a cavity, or a pit. The manufacturing technique of the plurality of trenches 8 may be, for example, a dry etching. The trenches 8 may be prepared by the dry etching until at least a portion of the sealing ring R1 is exposed. The trenches 8 may be prepared by the dry etching until at least a portion of the circuit area A1 is exposed.

5M , a plurality of TSVs (e.g., conductive vias v4 and v5) are formed in trench 8. Some TSVs (e.g., conductive via v4) contact sealing ring R1. Some TSVs (e.g., conductive via v5) contact at least one layer of circuit area A1. The semiconductor structure obtained in the operation of FIG. 5M may be referred to as semiconductor structure 2W.

5N, the chip DW2' and the semiconductor structure 2W are bonded together. The connection structures c7 and c8 are in contact with the conductive via v4. The connection structure c9 is in contact with the conductive via v5.

The chip DW2' can be bonded to the semiconductor structure 2W using hybrid bonding. The hybrid bonding can use an adhesive such as polyimide, heat pressing, diffusion bonding, pressure bonding, etc. to form metal-to-metal, insulator-to-insulator and metal-to-insulator bonds to achieve a vertically stacked chip. The chip DW2' and the semiconductor structure 2W can be bonded in a "face-to-back" manner. That is, the "face" of the chip DW2' is bonded to the "back" of the semiconductor structure 2W.

In "face-to-back" bonding, the circuit areas A1 and A2 can be located on the same side, and the sealing ring structures R1 and R2 can be located on the same side, so the circuit areas A1 and A2 can be connected to each other with a short-distance line (for example, through the conductive via v5), and the sealing ring structures R1 and R2 can be connected to each other with a short-distance line (for example, through the conductive via v4). In "face-to-back" bonding, there is no need to prepare a wafer in which the circuit area and the sealing ring structure are arranged in a mirrored manner (or flipped manner). Therefore, the entire preparation process can be simplified and the cost can be reduced.

Referring to FIG. 5O , after the chip DW2′ is bonded to the semiconductor structure 2W, a semiconductor structure as shown in the figure is obtained. The circuit area A1 can be electrically connected to the circuit area A2 through the conductive via v5 and the connection structure c9. The sealing ring structure R1 can be thermally connected to the sealing ring structure R2 through the conductive via v4 and the connection structures c7 and c8.

Referring to FIG. 5P , the substrate s3′ is thinned to form a substrate s3, and then a passivation layer p4 is formed thereon. The thinning technique of the substrate s3′ may be a mechanical polishing, chemical mechanical polishing (CMP), wet etching, or atmospheric downstream plasma (ADP) dry chemical etching (DCE). The passivation layer p4 may be one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics (such as carbon-doped oxides), ultra-low-k dielectrics (such as porous carbon-doped silicon dioxide), combinations thereof, or similar materials.

Referring to FIG. 5Q , a plurality of trenches 18 are formed through the passivation layer p4 and the substrate s3. The plurality of trenches 18 may be referred to as a hole, a cavity or a pit. The manufacturing technique of the plurality of trenches 18 may be, for example, a dry etching. The trenches 18 may be prepared by the dry etching until at least a portion of the sealing ring R2 is exposed. The trenches 18 may be prepared by the dry etching until at least a portion of the circuit area A2 is exposed.

5R, a plurality of TSVs (e.g., conductive vias v6 and v7) are formed in trench 18. Some TSVs (e.g., conductive via v6) contact sealing ring R2. Some TSVs (e.g., conductive via v7) contact at least one layer of circuit area A2. The semiconductor structure obtained in the operation of FIG. 5R can be referred to as semiconductor structure 3W. Each of the plurality of TSVs has a surface exposed by passivation layer p4.

Referring to FIG. 5S , a plurality of conductive bumps b1 are formed in contact with the plurality of TSVs. The plurality of conductive bumps b1 can be in thermal contact with the plurality of TSVs. The plurality of conductive bumps b1 can be electrically connected to the plurality of TSVs. In addition, an additional passivation layer p5 is formed above the passivation layer p4. The passivation layer p5 is formed to cover at least a portion of each bump in the plurality of conductive bumps b1. The plurality of conductive bumps b1 are partially embedded in the passivation layer p5. The plurality of conductive bumps b1 are partially exposed by the passivation layer p5.

The passivation layer p5 may be one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics (such as carbon-doped oxides), ultra-low-k dielectrics (such as porous carbon-doped silicon dioxide), combinations thereof, or similar materials. In some embodiments, the passivation layer p5 may include a material different from the passivation layer p4. In some embodiments, the passivation layer p5 may include the same material as the passivation layer p4. The semiconductor structure obtained in the operation of FIG. 5S may be referred to as semiconductor structure 200'.

Referring to FIG. 5T , the semiconductor structure 200 ′ obtained in the operation of FIG. 5S is flipped over, and then the substrate s1 ′ is thinned to form a substrate s1 ′. The thinning technique of the substrate s1 ′ may be a mechanical polishing, chemical mechanical polishing (CMP), wet etching, or atmospheric downstream plasma (ADP) dry chemical etching (DCE). The substrate s1 ′ is thinned until the TSV (e.g., conductive via v1) is exposed. The semiconductor structure obtained in the operation of FIG. 5T corresponds to the semiconductor structure 200 shown in FIG. 2 .

6A and 6B are flow charts illustrating a method 600 for fabricating a semiconductor structure according to some embodiments of the present disclosure.

The fabrication method 600 begins with operation 602, where a thermally conductive structure is formed embedded in a first passivation layer of a first wafer. For example, operation 602 may form a thermally conductive structure 10a embedded in a passivation layer p1 of a wafer CW1, as shown in FIG. 2 or FIG. 5C.

The preparation method 600 continues with operation 604, in which a plurality of conductive vias are formed to penetrate a first substrate of the first wafer and contact the thermal conductive structure. For example, operation 604 may form a plurality of conductive vias v1, v2, and v3 that penetrate the substrate s1 of the wafer CW1 and contact the thermal conductive structure 10a, as shown in FIG. 2 .

The preparation method 600 continues with operation 606, where a first connection structure is formed, which contacts the thermal conductive structure and is exposed by a surface of the first passivation layer. For example, operation 606 can form a connection structure c1 that contacts the thermal conductive structure 10a and is exposed by a surface p1a of the passivation layer p1, as shown in FIG. 2 or FIG. 5D.

The preparation method 600 continues with operation 608, where the first connection structure of the first chip is bonded to a second connection structure of a second chip. For example, operation 608 can bond the connection structure c1 of the first chip CW1' to the connection structure c3 of the second chip DW1', as shown in FIG. 5I.

The preparation method 600 continues with operation 610, where the first passivation layer of the first wafer is bonded to a first dielectric layer of the second wafer. For example, operation 610 may bond the passivation layer p1 of the first wafer CW1' to the dielectric layer d1 of the second wafer DW1', as shown in FIG5J. Although operation 610 is described as being after operation 608, it is contemplated that operation 610 may be performed before operation 608, or that operations 608 and 610 may be performed simultaneously.

The preparation method 600 continues with operation 612, where a second passivation layer is formed on a second substrate of the second wafer. For example, operation 612 may form a passivation layer p2 on the substrate s2 of the wafer DW1', as shown in FIG. 5K.

The preparation method 600 continues with operation 614, in which a first conductive via is formed through the second passivation layer and the second substrate. For example, operation 614 may form a conductive via v4 that penetrates the passivation layer p2 and the substrate s2, as shown in FIG. 5M.

The preparation method 600 continues with operation 616, where the first conductive via of the second chip is bonded to a third connection structure of a third chip. For example, operation 616 can bond the conductive via v4 of the semiconductor structure 2W to the connection structure c7 of the third chip DW2', as shown in FIG. 5N.

The preparation method 600 continues with operation 618, wherein a third passivation layer ( FIG. 5N ; p3) of the third wafer is bonded to the second passivation layer ( FIG. 5N ; p2) of the second wafer. For example, operation 618 may bond the passivation layer p3 of wafer DW2′ to the passivation layer p2 of semiconductor structure 2W, as shown in FIG. 5N . Although operation 618 is described as being after operation 616, it is contemplated that operation 618 may be performed before operation 616, or that operations 616 and 618 may be performed simultaneously.

Preparation method 600 is merely an example and is not intended to limit the content of the present disclosure beyond the scope explicitly described in the scope of the application. Additional operations can be provided before, during, or after each operation of preparation method 600, and some of the operations described can be replaced, eliminated, or reordered for additional embodiments of the method. In some embodiments, preparation method 600 can also include operations not depicted in Figures 6A and 6B. In some embodiments, preparation method 600 can include one or more operations depicted in Figures 6A and 6B.

One aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first substrate, a first dielectric layer disposed on the first substrate, a first passivation layer disposed on the first dielectric layer, and a second substrate disposed on the first passivation layer. The semiconductor structure also includes a first sealing ring embedded in the first dielectric layer and surrounding a circuit region of the first dielectric layer. The semiconductor structure also includes a heat conductive structure embedded in the first passivation layer and connected to the first sealing ring through a first connection structure.

Another aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first chip having a first dielectric layer and a first substrate; and a second chip bonded to the first chip and having a first passivation layer and a second substrate, wherein the second chip includes a heat sink structure in contact with a first sealing ring, and the first sealing ring is embedded in the first dielectric layer of the first chip.

Another aspect of the present disclosure provides a method for preparing a semiconductor structure with a heat dissipation structure. The preparation method includes forming a heat-conducting structure embedded in a first passivation layer of a first chip, and forming a plurality of conductive vias to penetrate a first substrate of the first chip and contact the heat-conducting structure. The preparation method also includes forming a first connecting structure that contacts the heat-conducting structure and is exposed by a surface of the first passivation layer. The preparation method further includes bonding the first connecting structure of the first chip to a second connecting structure of the second chip, and bonding the first passivation layer of the first chip to the first dielectric layer of the second chip, wherein a first sealing ring embedded in the first dielectric layer of the second chip is thermally connected to the heat-conducting structure through the first connecting structure and the second connecting structure.

In the semiconductor structure proposed in the present disclosure, the heat dissipation structure used for a three-dimensional stacked chip package or a chip-on-chip structure includes a sealing ring for each chip. The proposed heat dissipation structure provides an effective heat dissipation path for each chip in the three-dimensional stacked chip package or the chip-on-chip structure without introducing additional components or complex structures. At the same time, the proposed heat dissipation structure also increases the function of the existing sealing ring. That is, in addition to the inherent function of the sealing ring (i.e., preventing unexpected stress from propagating into the semiconductor element), the proposed heat dissipation structure also utilizes the sealing ring for heat conduction and heat dissipation. The proposed heat dissipation structure also enhances the structural stability of the three-dimensional stacked chip package or the chip-on-chip structure.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure defined by the scope of the patent application. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of this disclosure that existing or future developed processes, machines, manufactures, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machines, manufactures, material compositions, means, methods, or steps are included in the scope of the patent application of this application.

2W: semiconductor structure 3W: semiconductor structure 8: trench 10a: heat conduction structure 10b: heat conduction structure 18: trench 20: heat dissipation structure 30: three-dimensional heat dissipation structure 100a: top view 100b: top view 120a: conductor structure 120b: conductor structure 120c: conductor structure 200: semiconductor structure 200': semiconductor structure 300: semiconductor structure 600: preparation method 602: operation 604: operation 606: operation 608: operation 610: operation A1: circuit area A2: circuit area A3: circuit area A4: circuit area b1: conductive bump c1: connection structure c2: connection structure c3: connection structure c4: connection structure c5: connection structure c6: connection structure c7: connection structure c8: connection structure c9: connection structure CW1: chip CW1': chip d1: dielectric layer d2: dielectric layer DW1: chip DW1': chip DW2: chip DW2': chip DW3: chip DW4: chip i1: intersection i2: intersection i3: intersection i4: intersection p1: passivation layer p1a: surface p2: passivation layer p3: passivation layer p4: passivation layer p5: passivation layer r1: sealing ring r2: sealing ring r3: sealing ring r4: sealing ring r5: sealing ring r6: sealing ring r7: sealing ring r8: sealing ring r9: sealing ring r10: sealing ring r11: sealing ring r12: sealing ring R1: sealing ring structure R2: sealing ring structure R3: sealing ring structure R4: sealing ring structure R5: sealing ring structure s1: substrate s1': substrate s1a: surface s1b: surface s2: substrate s2': substrate s3: substrate s3': substrate S-S': dotted line T1: distance v1: conductive via v1a: end v1b: end v2: conductive via v2a: end v2b: end v3: conductive via v4: conductive via v5: conductive via v6: conductive via v7: conductive via v12: conductive via v13: conductive via x1: ridge x2: ridge x3: ridge x4: ridge x5: ridge x6: ridge y1: ridge y2: ridge y3: ridge y4: ridge y5: ridge y6: ridge y7: ridge y8: ridge x: direction y: direction z: direction

When referring to the embodiments and the scope of the patent application together with the drawings, a more comprehensive understanding of the disclosure of the present application can be obtained. The same element symbols in the drawings refer to the same elements. FIG. 1A is a top view illustrating a portion of a semiconductor structure of some embodiments of the present disclosure. FIG. 1B is a top view illustrating a portion of a semiconductor structure of some embodiments of the present disclosure. FIG. 2 is a cross-sectional view illustrating a semiconductor structure of some embodiments of the present disclosure. FIG. 3A is a schematic diagram illustrating a semiconductor structure of some embodiments of the present disclosure. FIG. 3B is a schematic diagram illustrating a semiconductor structure of some embodiments of the present disclosure. FIG. 3C is a schematic diagram illustrating a semiconductor structure of some embodiments of the present disclosure. FIG. 4 is a cross-sectional view illustrating a semiconductor structure of some embodiments of the present disclosure. FIG. 5A illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5B illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5C illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5D illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5E illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5F illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5G illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5H illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5I illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5J illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5K illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5L illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5M illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5N illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5O illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5P illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5Q illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5R illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5S illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 5T illustrates a stage of a method for preparing a semiconductor structure according to some embodiments of the present disclosure. FIG. 6A and FIG. 6B are flow charts illustrating a method for preparing a semiconductor structure according to some embodiments of the present disclosure.

10a: Heat conduction structure

100a: Top view

A1: Circuit area

d1: dielectric layer

r1: Sealing ring

r2: Sealing ring

S-S': dotted line

v1: conductive via

v2: conductive vias

v3: conductive vias

x1: Ridges

x2: Ridges

x3: Ridges

x4: Ridges

x5: Ridges

x6: Ridges

x: direction

y: direction

Claims (17)

A semiconductor structure includes: a first substrate; a first dielectric layer disposed on the first substrate; a first passivation layer disposed on the first dielectric layer; a second substrate disposed on the first passivation layer; a first sealing ring embedded in the first dielectric layer and surrounding a circuit region of the first dielectric layer; a thermal conductive structure embedded in the first passivation layer; and a second sealing ring embedded in the first dielectric layer and surrounded by the first sealing ring, wherein the second sealing ring is connected to the first sealing ring through a second connecting structure, the thermal conductive structure and the first connecting structure; wherein the thermal conductive structure is connected to the first sealing ring through a first connecting structure. The semiconductor structure as described in claim 1 further includes a first conductive via embedded in the second substrate, wherein a first end of the first conductive via is exposed by a surface of the second substrate, and a second end of the first conductive via is in contact with the thermal conductive structure. A semiconductor structure as described in claim 1, wherein the heat-conducting structure comprises: a first ridge extending in a first direction; and a second ridge spaced apart from the first ridge and extending parallel to the first ridge. The semiconductor structure as described in claim 3, wherein the heat-conducting structure further comprises: a third ridge extending along a second direction perpendicular to the first direction; and a fourth ridge spaced apart from the third ridge and extending parallel to the third ridge; wherein the third ridge intersects with the first ridge and the second ridge, and the fourth ridge intersects with the first ridge and the second ridge. The semiconductor structure as described in claim 3 further includes: a first conductive via falling on the first ridge; and a second conductive via falling on the first ridge; wherein the first conductive via includes an end exposed by a surface of the second substrate, and the second conductive via includes an end exposed by the surface of the second substrate. The semiconductor structure as described in claim 4 further includes: a first conductive via located at an intersection of the third ridge and the first ridge; and a second conductive via located at an intersection of the fourth ridge and the first ridge. The semiconductor structure as described in claim 2 further includes a third sealing ring embedded in the first dielectric layer, wherein the third sealing ring is spaced apart from the first sealing ring and the third sealing ring is farther away from the heat conductive structure than the first sealing ring. A semiconductor structure as described in claim 7, wherein the third sealing ring is connected to the first sealing ring via a third connecting structure, and the heat conducting structure includes a mesh profile. The semiconductor structure as described in claim 7 further includes a fourth sealing ring embedded in the first dielectric layer and surrounded by the third sealing ring, wherein the fourth sealing ring is connected to the second sealing ring through a fourth connecting structure. A semiconductor structure includes: a first chip having a first dielectric layer and a first substrate; a second chip bonded to the first chip and having a first passivation layer and a second substrate; and a second sealing ring embedded in the first dielectric layer and surrounded by the first sealing ring, wherein the second sealing ring is connected to the heat dissipation structure through a connecting structure; wherein the second chip includes a heat dissipation structure in contact with a first sealing ring, and the first sealing ring is embedded in the first dielectric layer of the first chip. A semiconductor structure as described in claim 10, wherein the heat dissipation structure comprises: a heat conductive structure embedded in the first passivation layer; and a first conductive via penetrating the second substrate, wherein a first end of the first conductive via is exposed by a surface of the second substrate. The semiconductor structure as described in claim 10 further includes a third chip bonded to the first chip and having a second dielectric layer and a third substrate, wherein the heat dissipation structure of the second chip is thermally connected to a third sealing ring embedded in the second dielectric layer, and the first chip includes a first circuit area surrounded by the first sealing ring, and the third chip includes a second circuit area surrounded by the third sealing ring. A semiconductor structure as described in claim 11, wherein the first circuit region is electrically connected to the second circuit region through a second conductive via penetrating the first substrate, and the thermally conductive structure includes a mesh profile. A semiconductor structure as described in claim 11, wherein the heat-conducting structure comprises: a first ridge extending in a first direction; and a second ridge spaced apart from the first ridge and extending parallel to the first ridge; wherein the heat-conducting structure further comprises a third ridge extending in a second direction perpendicular to the first direction, and wherein the heat dissipation structure further comprises a third conductive via located at an intersection of the third ridge and the first ridge. A semiconductor structure as described in claim 12, wherein the first circuit region of the first chip and the second circuit region of the third chip are located on opposite sides of the first substrate. A semiconductor structure as described in claim 10, wherein the heat dissipation structure comprises: a heat conductive structure embedded in the first passivation layer; and a plurality of conductive vias directly contacting the heat conductive structure, wherein each of the plurality of conductive vias comprises a first end embedded in the first passivation layer and a second end exposed by a surface of the second substrate. A semiconductor structure as described in claim 11, wherein the heat dissipation structure includes a heat conductive structure embedded in the first passivation layer and having a first ridge extending along a first direction, and the first ridge is connected to the first sealing ring and the second sealing ring.