TW200406876A - Method of forming self aligned contact - Google Patents

Abstract

A self-aligned contact method includes, firstly, forming a plurality of stack structures on a semiconductor substrate. The stack structures separate each other and each has a first polysilicon, an insulating layer on the first polysilicon and a second polysilicon on the insulating layer. Secondly, a spacer forms on the sidewall of the stack structures, and then a dielectric layer forms on the stack structures, the spacers and the semiconductor substrate. Finally, the portion of the second poly is used as a buffer for forming contact window by removing a portion of the dielectric layer. The contact window is located between two stack structures.

Description

200406876 V. Description of the invention (l) " ^ " — 一 '— ^ ~ — 1. [Technical field to which the invention belongs]-The present invention relates to a method for automatically aligning a contact window and a method in a memory cell process The method of automatically aligning the contact window includes: [Previous technique] Make-up: = body f ίf 1Γ mem ° ry) is a method that uses electrons to inject or extract floating gates to fly ^ ^ (non-volatile) ^ ^% # #; Increasingly increasing the number of electronic products such as telecommunications, communications and consumer products, and various electronic products ...… d South capacity, low-consumption battery energy flash memory architecture: 歹 on, t the main research direction ... In the former technology, the stacking structure does not have: == structure; has a small accumulation surface, and can cooperate with = "Yan 6 5 8'813 mentioned to form a stacked gate structure In this way, the active area of the silicon substrate is prevented from being destroyed when the dielectric layer is etched.

; Self-aligned contac technology (Self-aligned contac), used in the manufacture of various integrated circuit components,

Mark X X 1 diameter, contact window (contact wind) and lower contact window H.凊 Refer to the first marriage for the application of general Most I body HAC process. First, in the "Shi Xi wafer substrate · sequentially ^ Jia Ji" electric layer 1 1 0,-a polycrystalline silicon layer i 2 0 and a tungsten silicide layer 3 0,

200406876 V. Description of the invention (2) _ The steps of forming the gate of the transistor M0S to the hard mask 140 (such as the formation of a hard shadow lithography on su ^ 130, and the steps of T2 ,, And: the overly restrictive pattern w forms a plurality of stacked gate junctions separated from each other, and the shape is: a gap is formed on the side wall of each stacking pole structure; the first main-Β diagram to stop the contact window etching To avoid the occurrence of the problem, you need to cover the entire stacked interlayer structure, such as the gap between the structures. Finally, as shown in paragraphs (i) and (ii), the anisotropic pole junction (tChing) is used to perform the auto-alignment of the contact window, and the last name = is the aperture between the stacked gate structures. Because Si3N4 is relative to si () d: selection ratio , Quality curtain cover 140 and interval 15. It is not easy to be :: = a barrier effect, so that the window 170 can be completely etched to the surface of the silicon material 100 without damaging the stacked gate structure. Facing the day = the integrated circuit manufacturing process of Jinyuezai and Secretization, the above-mentioned automatic alignment contact window technology can not only effectively reduce the wire diameter, but also avoid difficult exposure during the lithography process and misalignment at the rest of the time (mis -a 1 ignment) and shorts and open caused by incompleteness. The general flash memory memory cell structure is mainly composed of a doped semiconductor substrate, an insulating layer, a floating gate, and a control gate (c 0 n t r ο 1 g a t e). The floating gate is used to inject or remove electrons, and the control gate is used to control the word line (b i t 1 i ne) voltage. Please refer to the second figure, which shows the structure of general P-channel flash memory cells. On a silicon wafer substrate 200, a gate dielectric layer 2 1 0, a first polycrystalline silicon layer 2 2 0, 200406876 Description of the invention (3) ^, ', 彖 layer 2 3 0 and The stacked structure composed of the second polycrystalline stone layer 240 is formed by a plurality of separated stacked structures 250 after lithography and etching. Then, a space 2,60 is formed on the sidewall of each stacked gate structure 250, and a dielectric layer 27o is formed to cover the entire stacked gate structure and fill a gap of the stacked gate structure 250. Finally, corner etching is performed. This is the contact window process in the traditional flash memory cell and passes through the gate gap layer 2 5 0, 5 window 280 3. [Abstract] One of the purposes of the present invention is to use a layer as a contact window for etching The buffer layer of time, the role of the layer. The purpose is to use the polycrystalline silicon layer not used in the memory cell to automatically align the contact window to reduce the aperture of the contact window and improve the process of the present invention. The invention is a technology using a contact window. First, a second polycrystalline silicon layer is separated from each other in each of the stacked structures, in which an insulating double polycrystalline silicon layer is formed on a side wall of the insulating laminated structure, and a plurality of gap layers and a semiconductor substrate are formed and removed. Part of the dielectric layer is used in the memory cell, that is, instead of the traditional hard day after day layer as a buffer layer, a plurality of stacks are formed on the conductor substrate, which contains a polycrystalline spar layer, and an insulating layer is formed on the first layer. A polycrystalline silicon layer is above and above. A gap layer is then formed on the dielectric layer on the plurality of stacked junctions. Part of the second polycrystalline silicon layer is used to form a contact window in two stacks. The polycrystalline second-type curtain method is performed as the contact level. Dynamically align the edges and squares of the stacked structure, with each structure and complex as a relief. 200406876 V. Description of the invention (4) IV. [Embodiment] Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can be widely implemented in other embodiments. That is, the scope of the present invention is not limited by the proposed embodiments, but should be based on the scope of patent applications filed by the present invention. Moreover, in this specification, different parts of the semiconductor element are not drawn according to dimensions. Certain dimensions have been exaggerated compared to other related dimensions to provide a clearer description and understanding of the invention. The third diagrams A to C show the first embodiment of the present invention. Please refer to the third diagram A. First, a gate dielectric layer 3 1 0 is formed on the half-conductor substrate 3 0. The semiconductor substrate 3 0 may be a doped silicon wafer, and the gate dielectric layer 3 10 can be a silicon dioxide layer (S i 0 2). Next, a first polycrystalline silicon layer 3 2 0 is formed over the gate dielectric layer 3 1 0. The first polycrystalline silicon layer 3 2 0 can be formed by chemical vapor deposition (CVD for short). It is formed to be used as a floating gate in a memory cell, a gate electrode of a general transistor control element, or even not used for control. An insulating layer 3 3 0 is formed on the first polycrystalline silicon layer 3 2 0 to prevent conduction between the two gates. In this embodiment, the insulating layer 3 3 0 is an oxide layer-nitride stone. -Structure composed of oxide-nitride-oxide (referred to as 0N0), such as a Si 02 / Si 3N4 / Si 02 structure, S i 3 Ν 4 in this ONO structure is used to increase the ability to isolate impurities to avoid leakage current , And can slightly increase the dielectric constant value, Si 02 is used to improve the nitride

200406876 V. Description of the invention (5) The problem of poor interface properties between (n i t r i d e) and Shi Xicai. Finally, a second polycrystalline silicon layer 3 4 0 is formed over the insulating layer 3 3 0. The second polycrystalline silicon layer 3 4 0 can be formed by chemical vapor deposition for control in the memory cell. Gate or blank gate not used for control. The gate dielectric layer 3 1 0, the first polycrystalline silicon layer 3 2 0, the insulating layer 3 3 0, and the second poly silicon layer 3 4 0 constitute a stacked structure in the memory cell. In addition, a dielectric layer 3 95 can be formed between the insulating layer 3 3 0 and the second polycrystalline silicon layer 3 4 0 as a mask for etching the insulating layer. Then, the lithography and etching steps of pattern transfer are performed on the stacked structure, and the stacked structures 3 8 0, 3 8 5 and 3 9 0 which are separated from each other are formed by removing part of the stacked structure. The etched portion includes a gate oxide layer 3 1 0, a first polycrystalline silicon layer 3 2 0, an insulating layer 3 3 0, and a second polycrystalline silicon layer 3 4 0, and a portion of the semiconductor substrate is exposed after the etching. The surface of the material 300, the structure after etching is as shown in the third A figure. The above-mentioned lithography and etching steps for pattern transfer of the stacked structure are known techniques, so they will not be described in detail in this embodiment and the drawings. Instead, the stacked structures are formed by etching directly as shown in the drawings. The stacked structures 3 8 0, 3 8 5 and 3 9 0. Among them, the position of the first polycrystalline silicon layer 3 2 0 in the stacked structures 3 8 0 and 3 8 5 may be a gate electrode of a general transistor control element or not used for control, so the second polycrystalline silicon layer 3 The position 40 is regarded as a dummy gate. On the other hand, the stacked structure 390 is used as a memory cell. The first polycrystalline silicon layer 3 3 0 is used as a floating gate, and the second polycrystalline silicon layer 3 4 0 is used as a control.

200406876 V. Description of the invention (6) Use of gate electrode (c ο n t r ο 1 g a t e). After the lithography and surname engraving steps of the pattern transfer are completed, the semiconductor substrate 300 can be subjected to ion implantation (〇〇 ^ \ implantation) to form the source and the electrode (source) of the memory element. drain) on a semiconductor substrate 300. Similarly, the electrical properties of the source, non-electrode and various regions are not shown in the figure.

Next, please refer to the third figure B. After the ion implantation is completed, in order to avoid the conduction phenomenon on the side walls of the stack structure 380, 385, and 390, it is necessary to stack the structures 380, 3. A gap layer 3 50 is formed on the side walls of 8 5 and 3 9 0 for insulation purpose, and can be used as a stop layer when the window is engraved in the future. The formation method of the gap layer 3 50 is' the gap layer material is first uniformly formed by chemical vapor deposition on the surfaces, sidewalls and exposed semiconductor bottoms of the stacking bonds 3 8 0, 3 8 5 and 3 9 0. The surface of the material 300 can be engraved to remove the part in the surface direction with anisotropic dry money. In this embodiment, the gap layer 3 50 may be silicon nitride (S i 3 N 4) or a multilayer structure composed of an oxide layer and a nitride layer. Next, a dielectric layer 360 is formed to cover the stacked structures 380, 385, and 390, and fill the gaps between the stacked structures 380, 385, and 390. Wherein, the dielectric layer 36 can be a ceria layer.

Finally, the step of touching the window 370 for money. From the foregoing, it is known that in each stack structure, the portion corresponding to the position of the first polycrystalline silicon layer 3 2 0 can be used as a gate electrode of the memory cell or not used for control, especially in the contact hole 3 7 The floating gates at positions after 0 are not used to inject or dissipate electrons, but are used as a selection gate as a buffer for the remaining floating gates.

Page 10 200406876 V. Description of the Invention (7) The second part of the polycrystalline silicon layer 34 above the selection gate becomes a blank gate with no way, such as stacked structures 380 and 385. The biggest feature of the present invention is to use this unused polycrystalline spar layer as the clock punching layer at the time of contacting the last name, so that the contact window of the small-scale hole scale can be etched with a larger aperture range. It is the use of automatic alignment window technology to reduce the problem of small-area contact windows that are not easy to expose during lithography or susceptible to errors during etching. T +, as shown in Figure 3c, the dielectric layer 36 is first 〇Perform a lithography step, use a non-isotropic dry etching, and set a larger aperture range to etch the dielectric layer. During the etching process +, to achieve the purpose of stopping the extra etching range The blank gate and the interstitial layer 3 5 0 will be etched and eliminated, but because of the polycrystalline stone and nitride stone, the etching choice of silicon dioxide is higher than that of etchingse 1 ecti ν ity). The formed dielectric layer 360 will be easier to be etched than the blank gate and gap layer 35. In this way, even if the position alignment is slightly shifted during the etching, the contact window etching can be successfully completed without etching. Under- or over-etching Problem. Finally, a contact window plug 375 is formed in the contact window 370, so that the contact window plug 375 and the semiconductor substrate 300 are electrically connected. Next, another embodiment of the present invention will be described. As shown in the fourth figure, a gate dielectric layer 410, a first polycrystalline stone layer 4 2 0, an insulating layer 4 3 0, and a second polycrystalline silicon layer are sequentially formed on a semiconductor substrate 400. & 4 〇, and after appropriate pattern transfer lithography and etching steps, separate stacked junctions are formed 200406876 V. Description of the invention (8) structure. In addition, it can also be used in the insulating layer 4 3 0 and the second compound A dielectric layer 4 95 is formed between the silicon layers 4 4 0 as a mask for etching the insulating layer. Then, a gap layer 4 5 0 is formed on the side wall of each stacked polycrystalline silicon structure, and is formed on the semiconductor A barrier layer 4 6 0 is formed on the substrate 4 0, the stacked polycrystalline silicon structure and the gap layer 4 5 0, and a dielectric layer 4 7 0 is formed over the barrier layer 4 6 0 in a blanket manner. Finally, the unused blank gate is used as a buffer layer, and the contact window 480 is etched with the automatic alignment window technology, and a contact is formed. The window plug 48 5 in the contact window 4 8 0 causes the contact window plug 48 5 to be electrically connected to the semiconductor substrate 400. The barrier layer 4 60 may be an oxide layer structure or a nitride layer. The structure is a multilayer structure composed of an oxide layer and a nitride layer. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention. Without departing from the essence of the present invention, The scope can still be changed and implemented, and these changes should still be within the scope of the present invention. Therefore, the scope of the present invention is defined by the scope of the following patent applications.

Λ Page 12 200406876 Brief description of the drawings 5. [Simplified description of the drawings] Figures A to C show the traditional automatic alignment window technology used in the transistor M0S process. The second figure shows the conventional manufacturing process of the flash memory memory cell contact window. Figures 3A to 3C show one embodiment of the automatic alignment window technology of the polycrystalline silicon buffer of the present invention. . The fourth figure shows another embodiment of the automatic alignment window technology of the polycrystalline silicon buffer of the present invention. Symbol 100 1 10 120 130 140 150 160 170 200 210 220 230 240 240 Description: Broken wafer substrate gate dielectric layer polycrystalline silicon layer tungsten silicide layer hard curtain layer gap layer dielectric layer contact window stone evening wafer bottom Material gate dielectric layer

Page 13 200406876 Simple illustration of the diagram 2 5 0 Stacked gate structure 2 6 0 Gap layer 2 7 0 Dielectric layer 2 8 0 Contact window 3 0 0 Semiconductor substrate 3 1 0 Gate dielectric layer

3 2 0 first polycrystalline silicon layer 3 3 0 insulating layer 3 4 0 second polycrystalline silicon layer 3 5 0 gap layer 3 6 0 dielectric layer 3 7 0 contact window 3 7 5 contact window plug 3 8 0 stack Structure 3 8 5 Stacked structure 3 9 0 Stacked structure 3 9 5 Dielectric layer 400 Semiconductor substrate 4 1 0 Gate dielectric layer

4 2 0 First polycrystalline silicon layer 4 3 0 Insulating layer 4 4 0 Second polycrystalline silicon layer 4 5 0 Gap layer 4 6 0 Barrier layer

Λ P.14 4 4200406876 Brief description of drawings 470 Dielectric layer 4 8 0 Contact window 4 8 5 Contact window plug 4 9 5 Dielectric layer ❿

Page 15

Claims (1)

4 200406876 6. Scope of patent application 1. A method for forming an automatic alignment contact window, comprising: providing a semiconductor substrate;-forming a plurality of stacked structures on the semiconductor substrate, each of the stacked structures being separated from each other and including a A first polycrystalline silicon layer, an insulating layer on the first polycrystalline silicon layer, and a second polycrystalline silicon layer on the insulating layer; forming a gap layer on a sidewall of each of the stacked structures; forming A dielectric layer on the plurality of stacked structures, the plurality of gap layers and the semiconductor substrate; and Taking part of the second polycrystalline silicon layer as a buffer layer, removing part of the dielectric layer to form a contact window between part of the two stacked structures. 2. The method for forming an auto-aligned contact window as described in item 1 of the patent application scope, wherein the insulating layer includes an oxide layer. 3. The method of forming an auto-aligned contact window as described in item 1 of the scope of the patent application, wherein the insulating layer includes a nitride layer. 4. The method of forming an auto-aligned contact window as described in item 1 of the scope of the patent application, wherein the insulating layer includes an oxide-nitride-oxide layer (0N0) structure. 5. The method for forming an automatic alignment contact window as described in item 1 of the scope of the patent application, further comprising forming a dielectric layer between the insulating layer and the second polycrystalline silicon layer. Page 16 200406876 6. Scope of patent application 6. The method for forming an automatic alignment contact window as described in item 5 of the scope of patent application, wherein the gate dielectric layer comprises silicon dioxide. 7. The method of forming an auto-aligned contact window as described in item 1 of the patent application scope, wherein the gap layer includes a nitride layer. 8. The method of forming an auto-aligned contact window as described in item 1 of the patent application scope, wherein the gap layer includes a multi-layer structure composed of an oxide layer and a nitride layer. 9. The method for forming an auto-aligned contact window as described in item 1 of the scope of patent application, wherein the plurality of stacked structures further includes forming a gate dielectric layer on the semiconductor substrate and the first polycrystalline silicon layer between. 10. The method for forming an automatic alignment contact window as described in item 1 of the scope of patent application, further comprising forming a contact window plug in the contact window, wherein the contact window plug is electrically conductive with the semiconductor substrate. On the connection. 1 1. A method for automatically aligning a contact window of a polycrystalline silicon buffer, comprising: providing a semiconductor substrate; forming a plurality of stacked structures on the semiconductor substrate, each of the stacked structures being separated from each other and including a first compound A silicon layer, an insulating layer on the first polycrystalline silicon layer, and a second polycrystalline silicon layer on the insulating layer, part of which Page 17 200406876 VI. Scope of patent application δ Mystery complex spar complex is a plurality of blank gates; a gap layer is formed on a side wall of each of the stacked structures; forming A barrier layer is on the plurality of stacked structures, the plurality of gap layers and the semiconductor substrate; a blanket forms a dielectric layer on the barrier layer; and the plurality of blank gates serve as a buffer layer Removing a portion of the dielectric layer to form a contact window between any two of the stacked structures containing the blank gate; and forming a contact window plug in the contact window, wherein the contact window plug and the The semiconductor substrate is electrically connected. 1 2 The method for automatically aligning a contact window of a polycrystalline silicon buffer as described in item 11 of the scope of patent application, wherein the insulating layer includes an oxide layer. 13. The method for automatically aligning a polycrystalline silicon buffer contact window as described in item 11 of the scope of the patent application, wherein the insulating layer includes an oxide layer-nitride layer-oxide layer (0N0) structure. 14. The method for automatically aligning a contact lens of polycrystalline spar buffer as described in item 11 of the scope of patent application, further comprising forming a silicon oxide layer between the insulating layer and the first polycrystalline layer. 1 5Automatic alignment of polycrystalline silicon buffer as described in item 丨 丨 200406876 VI. Scope of patent application The contact window method, wherein the gap layer includes a nitride layer. 16. The method for automatically aligning a contact window of a polycrystalline silicon buffer according to item 11 of the scope of the patent application, wherein the gap layer includes a multilayer structure composed of an oxide layer and a nitride layer. 17. The method for automatically aligning a contact window of a polycrystalline silicon buffer as described in item 11 of the patent application scope, wherein the barrier layer comprises an oxide layer. 18. The method for automatically aligning a contact window of a polycrystalline silicon buffer according to item 11 of the scope of the patent application, wherein the barrier layer includes a nitride layer. 19. The method for automatically aligning a contact window of a polycrystalline silicon buffer according to item 11 of the scope of the patent application, wherein the barrier layer comprises a multilayer structure composed of an oxide layer and a nitride layer. Page 19