SU1689950A1 - Multichannel scheduler - Google Patents

Abstract

The invention relates to computing and can be used to control the processing of applications in real-time computing and queuing systems built on the basis of a single computer. The purpose of the invention is to increase the speed. The device contains a block for selecting the maximum code, a control block, a register, a priority node, and each channel has a counter, three triggers, two K elements. In the device, the selection of the highest priority subscriber's application is made taking into account the rate of change of priority in streams for wok. 3 il.

Description

The invention relates to computing and can be used to control processing of applications in real-time computing systems built on a multi-program computer.

The purpose of the invention is to increase the speed of the device.

Figure 1 shows the block diagram of the device} figure 2 - block diagram of the block select the maximum code; FIG. 3 is a block diagram of a counter explaining its operation principle.

The device (Fig. 1) contains triggers 1, 2, elements 3 and 4, counters 5, triggers 6, block 7 for selecting the maximal code, signal code 8 for the device, node 9 for priority, register 10, block 11 for control , in the structure of which the element I 12 is included,

element NOT 13, shaper 14 im-, pulse, element ШШ 15, element 16, pulse generator 17, query inputs 18, outputs 19, start input 20, signal output 21.

Block 7 (FIG. 2) contains bit-wise nodes 22, which include bit analysis nodes 28, which consist of AND 24 n OR 25 elements, OR-NOT 2i i elements, inputs 27, and outputs 28. Block 7 is made by auth. No. 950083. The counter circuit diagram (Fig. 3) contains counting triggers with counting inputs 29, elements OR 30 and 31, element 32, counting inputs 33, 34, reset input 35, information outputs 36, overflow output 37.

In the initial state, the triggers 1, 2, 6, and also the register 10 are in the zero position (the inputs are forced (L

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the installation is not shown in the drawing). The subscriber entering into operation, at input 17, sets the corresponding trigger 2 to the single state and, depending on the subscriber’s priority, can set the trigger 1 to the input 8 (in the case of the single state of the trigger 1 on each operation cycle of the device to the contents of the counter 5 the number two is added. The unit is added to the second digit of counter 5 - otherwise it is added to the lower bit).

If there is no processing request, the input potential 20 establishes a zero potential, which enters the input of the imaging device 14 and the element NOT 13. From the element NOT 13, the unit potential flows to element AND 12, which is initially closed with zero potential from element OR 15.

With the receipt of applications from the subscriber, the corresponding trigger 2 is set to one, from the output of which AND 12 is opened through the element OR 15, and the clock pulses from the generator 11 are sent to the corresponding counter 5. At the same time, a single signal goes to the input of the element 16 and exit 21, signaling the presence of a processing application. A single impulse is formed by this signal, the duration of which is determined by the time of the choice of the next application for processing. At this signal, the element 12 is closed through the element 13 and the counter 5 stops counting, the pulse shaper 14 produces a single pulse (with a delay for the transient time in the circuit: counter 5, trigger 6, block 7, node 9), through which element 16 opens node 9, after which the position number of the subscriber is recorded in register 10. From the output of node 9, the corresponding triggers 1, 2, 6 and counter 5 are set to zero.

At the end of processing the subscriber's application, if there is a surcharge from this or another subscriber. The computer gives out another single impulse, and for processing it is selected the application with the highest priority.

The operation of the device for the general case will be considered on the example of processing two flows of the application. Let the triggers 2 q and 2 be set to unit

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let it trigger 1,. set to one, and trigger 1 to zero. The triggers of the 2 remaining subscribers are set to zero.

On input 20 from a computer, a zero potential arrives (even if it is occupied by processing the subscriber’s k-ro request). Element AND 12 is open, and counters 5 and LL are counting.

Element And 16 is closed with zero potential from the output of the driver 14. The control input of the register 10 receives a zero potential, prohibiting the reception of a code on it.

The third inputs of the K 3, 3 elements (2. 4-f 4) receive a single potential from flip-flops 24 and 2. At the first input of a 3f element, a single potential comes from the direct output of flip-flop 1, and from the inverse output a zero potential flows to the first input of the element And 4, therefore, the element And 4 / (closed, and the element K 3 open. Similarly, closed element And 3, and element And 4.2. Open. Clock pulses from the generator 17 through the open element And 12 arrive at the second inputs of all elements And 3 and 4. These pulses through the open elements And 3 / and 4 are received respectively at the second input account 5x and the first input of the counter 5g (see FIG. 3). The contents of the 5 / counter are changed by two units for each cycle, and the counter by 5% .- per unit with the arrival of each clock pulse. The codes from these counters go to the first one. and the second group of inputs of block 7.

Suppose that at this time the maximum code arrives at the first inputs of block 7, then a single level will be formed at its first output. This signal is fed to the input of node 9. Thus, in the case when several unit level signals are formed at the outputs of block 7, the unit potential is at the same output of node 9. But when the next application completes processing, the processor sets the unit potential at input 20 of the device. On this signal, element 12 is closed, and counters 5 stop counting.

But the end of the transient unit potential comes from the shaper 14 on the element K 16.

The unit potential from node 9 goes to the third reset input of the counter 5, sets it to the zero state, and to the reset input to the zero flip-flop 6 ". In addition, this signal sets the corresponding register register 10 to single. On output 19, a single potential, indicating that the processor must choose to process the next request.

If during the operation of the device the contents of any counter 5 overflows, the overflow signal (exit 37 in FIG. 3) sets the corresponding trigger 6 to one state. The unit potential from this trigger b is fed to the first (to the most significant bit) input of the group of block 7. Counter 5 continues counting the clock pulses. Its contents determine the waiting time after a counter overflow. According to the processor readiness signal, in this case, the processing selects the application from this stream.

If during the operation of the device the contents of several counters overflow, the application is selected for processing from a stream with a long waiting time, and if they are equal, with the lowest position number. As far as the choice is made for servicing the applications from these flows, the corresponding output 5 and triggers 1, 2, 6 are set to zero from the corresponding output of the node. If the computer is free and there is no application for processing, zero potentials are sent from the triggers 2 to the OR 15 element, and from its output the zero potential goes to the elements And 12 and 16. The input zero from the computer also receives a signal of zero level. In this case, elements 12 and 16 are closed.

Claims (1)

Invention Formula A multichannel dispatching device containing a control unit, a register, and in each channel two triggers, a counter and two elements AND, the control unit contains the first element AND, element KE and a pulse generator, and in the control unit the output of the pulse generator is connected to the first input of the first element And $ whose second input through the element is NOT connected to the device launch input, 15 20 6899506 the single input of the first trigger of each channel is the device's request input, the register outputs are a group of device information inputs, characterized in that, in order to improve speed, it contains a block for selecting the maximum code, priority node, U in each channel is the third trigger, in the control unit is the second element AND, the OR element and the pulse shaper, and in each channel the counter contains counting triggers by the number of bits, two OR elements and the element K, the first counting input of each counter is connected to the counting the trigger input of the first discharge of the counter, the trigger output of the first discharge of the counter is connected to the first inputs of the first and second OR elements of the counter, the second counting input of the counter is connected to the second input of the first OR element of the counter, the output of the first OR element 25 of the counter is connected to the counting input of the second discharge trigger of the counter, the output of the second discharge of the counter is connected to the counting input of the trigger of the third discharge of the counter and the second input of the second OR element of the counter, the output of the second element OR of the counter and the discharge of the counter bits starting from the third Are information outputs of the counter and are connected to the input , d) the element AND of the counter, the output of which is the output of the overflow of the counter, the output of the trigger of each digit of the counter, starting with the third one, is connected to the counting input of the trigger 40 of the next digit of the counter, the reset inputs of the trigger trigger are connected to the reset input of the counter, in the control unit the output of the OR element is connected to the third input of the first element 45 And the first input of the second element And is the signal output of the device, the start input of which is connected by the input of the pulse shaper to the control, the output of which is connected to the second input of the second element And of the control unit and the clock input of the register, the information inputs of which are connected to the outputs priority node whose inputs connect 55 with the outputs of the block select the maximum code, the old bit of each group of inputs of the block select max. The second code is connected to the output of the second trigger of the same name channel, the remaining inputs of this group of inputs of the maximum code selection block are connected to the information outputs of the counter of the same channel, the single input of the third trigger of each channel is connected to the same signal input of the device, the direct outputs of the first and second triggers in each channel connected, respectively, to the first and second inputs of the first element of its channel, the direct output of the first trigger and the inverse output of the second trigger of the channel are connected respectively with the first and second inputs of the second element AND of its channel, the third inputs of the first and second elements of the channels are connected to the output of the first element AND of the control unit, the output of the first element AND of each channel is connected to the second counting input of the counter, the first counting input of which is connected with the output of the second element And its channel, the output of the overflow counter is connected to the single input of the second trigger of its channel, each output of the priority node is connected to the reset inputs of the counter and the first, second and third triggers one alternating channel outputs of the first flip-flops are connected to the channel control unit of the OR inputs, the output of the second AND gate of which is connected to the control input of the priority of the node. eight, fig 20 27 Step 1 X, 36Z 36t