SU1062683A1 - Information input device - Google Patents

Abstract

A DEVICE FOR INPUTING INFORMATION containing a pulse generator, a frequency divider, an analog switch and an analog-to-digital converter, the output of which is the information output of the device, the output of the pulse generator is connected to the input of the frequency divider, the inputs of the analog switch are information inputs of the device different from that, in order to speed up the device, an OR element, a counter, a multiplexer, a trigger, a decoder, the first and second delay elements are entered into it (Register, output the output of the pulse generator is connected to the gate input of the multiplexer; the output of the frequency divider is connected to the inputs of the first and second delay elements and the first input of the OR element, the output of which is connected to the counting input of the counter; with the reset input of the frequency divider, the inhibit input of the pulse generator and the trigger output, the setup input l of which is the trigger input of the device, the second input of the element OR connect The output of the multiplexer, the information inputs of which are the control inputs of the device, the address inputs of the multiplexer are connected to the (L information input of the register and the outputs of the parallel counter code whose output is connected to the installation input of the trigger, the decoder outputs are connected to the analog input addresses the switch, the output of which is connected to the input of the analog-to-digital converter 35 eozer, the start input of which is connected to the output of the first delay element, the clock input of the register is connected with the output of the second delay element; 00

Description

The invention relates to computing technology and can be used in multichannel information-measuring information collection systems.

A device for inputting information containing an A / D converter, sensors, a display unit, two AND gates, an encoder, a HE element, a memory block, a control unit, two OR gates, a timer, two switches, an eppa selection unit, an e add prior information, threshold element, comparator and computing unit l,

The disadvantage of this device is that it does not provide the possibility of condensing the incoming information and has a very complex and cumbersome structure:

The closest in technical essence to the invention is a multichannel device for digital filtering, which contains a quantum generator, an ADC, a permanent storage unit, a communication unit, a frequency divider, a switch, prohibition elements, memory nodes, a multiplication unit 2j,:

The disadvantages of this device are the impossibility of condensing the incoming information and the lack of selective selection of input information about

The purpose of the invention is to increase the speed of devices. A;

This goal is achieved by the fact that the input device containing a pulse generator, a frequency divider, an analog KoiviMyTaTOp and an analog-to-digital converter, the output of which is the information output of the device, the output of the pulse generator is connected to the input of a frequency divider, the inputs of the analog switch are information inputs of the device, the element OR, the counter, the multiplexer, the trigger, the decoder, the first and second delay elements, the register whose output is connected to the input d the decoder and is the address output of the device, the output of the pulse generator is connected to the gate input of the multiplexer, the output of the frequency divider is connected to the inputs of the first and second delay elements and the first input of the OR element, the output of which is connected to the counter input of the counter, the reset input of which is connected to the reset input of the frequency divider , the prohibition input of the pulse generator and the output of the trigger, the installation input in l of which is the trigger input of the device, the second input

the OR element is connected to the output, the multiplexer, whose information inputs are the device control inputs, the multiplexer address inputs are connected to the register information inputs and the parallel counter code outputs, the output of which is connected to the O input of the trigger, the decoder outputs are connected to

The address inputs of the analog switch, the output of which is connected to the input of the analog-digital converter, the start input of which is connected to the output of the first delay element, the clock input of the register are connected to the output of the second delay element. :

Phi, g 1 shows the device layout; fig 2 is temporary

Qi diagram of device operation modes;

The device for collecting information consists of 1 pulse generator, 5 frequency divider 2, first 3 and second 4 delay elements, element OR 5, counter 6, trigger 7, multiplexer 8, register 9, de-. the encoder 10, the analog clone switch 11, the A / D converter 12, the inputs 13, the start input 14 of the device, the control buses 15, the address 16, the information output buses 17 to the device.

The principle of the device operation is that in the information received at the inputs of the channels of the selector-multiplexer 8, the system prohibits the passage, i.e., ,,,: gaps in the information present on one or another input 13 of the analog information, and this is achieved by increase the speed (frequency) of the survey (view) of these inputs without connecting them to the input of the ADC, while

as the switching of the analog switch 11 through the working (non-throughput) inputs is performed with a lower frequency determined by the switching cycle. The first (high) frequency is generated by the pulse generator 1, the second is removed from the splitter 2 4acTOTJJt.

(-I), P

where is the switching cycle period

(period of pulse repetition from divider 2 is often ± s); Td - period of high frequency (frequency generator 1 pulses); And - the number of analog inputs

information; AUn is the time for converting information into an ADC. Value (due to the fact that at least one input of analog information must be connected to the input of ADC 12, since it is silently turning on the device with information skipping over all Ehoda; All the analog information inputs that are passed through will be viewed; At the same time, the device is built 1 in such a way that information is generated on the 16 address buses, which characterizes only the number of the information input switched on the ADC 12, thereby ensuring with the connection between the information of the working input and its address (but | Measure) 5: The pulses of the register of the 9 address, corresponding to the working input of the analog information, should arrive with some delay in relation to the moment when the data at the input of the output of the counter 6 of the code address corresponding to the number of the working input. This delay is formed by the second delay element 4, its value must be less than TO in order to have time to write to the address register 9 before the next next pulse of the input information passes, as follows from the following description of the operation of the information collection device. The pulses for triggering the A / D converter 12 arrive at divider 2 frequencies with some delay, which is necessary to unambiguously digitize the information of the working input. This delay is formed by the first delay element 3, its value is determined by the time of establishing transients in the device from the time the information on the address bus 16 is changed to the moment the commutator switch 1.1 operates. The follow-up period T of the interrogation pulse I (Fig 2) determines the interrogation rate of the p-inputs of analog information; the total number of pulses at the output of the splitter 2 frequency determines the total switching time of the analog switchboard; at the input of the counter 6 addresses there are imps III; The numbers marked and marked correspond to the working inputs of the information. In the initial state at the input on the buses 17, the information output and. The device address busses 16., signals are absent. By the control busbars 15, the position code of the multiplexer 8 is supplied with a positional code defining the numbers of the transmitted and working inputs of analog information. At the inputs 13 of the analog information is present information. The trigger 7 is in the zero state and blocks the pulse generator 1 on the input of the generation inhibit and the frequency divider 2 on the installation input, and keeps the address counter 6 on the installation input on the zero state. When the start pulse arrives on input 14, the trigger 7 switches Enable the 1 pulse generator, 2 frequency divider and address counter 6. Starting from this moment, at the outputs of the pulse generator 1 and the splitter frequency 2, successive pulses of respectively high frequency and switching frequency are generated - From the pulse generator 1 output, the first pulse from the high frequency pulse sequence arrives at the gate input of the selector-multiplexer 8. If from the device control buses 15, there is a signal level at the first input of the selector-multiplexer channels, corresponding to the working input of analog information (FTSG, 2), and at the outputs of the counter bits, addresses, the zero combination corresponding to the inputs of the selector-multiplexer address B also the input number of the analog information, then the gate-pulse to the output of the selector-multiplexer does not run; In this case, the first pulse passes through the logical element OR 5 (which coincides in time with the first pulse from the generator 1 Pulse) from the output of frequency divider 2. This pulse is applied to the counting input of the 6 .address counter, at the outputs of the bits of which the code combination is changed by one. This combination is fed to the data inputs of the address register 9 and the selector-multiplexer address inputs; 8, From the output of the frequency divider 2, the pulse is also sent to the elements 3 and 4 of the delayed signal When the delayed address of the first output pulse arrives at the input of the register 9 record 9 the frequency divider 2 records the code combination into the register 9 addr; From the output of the register 9 address, information about the number of the analog information input (in this case, the first number) is output to the bus 16 of the device address and the inputs of the decoder 10 rez, which influences the inputs upravle.ni analog switch 11 triggers the switch is connected from the first analog data input to the ADC input of 1.2; When a pulse arrives from the output of the first element 3, the input to the start of the A / D converter 12 digitizes information in the latter, and the converted information from the outputs of the ADC bits enters the information output buses 17 to the device; At the same time, the code combination arriving at the inputs of the address of the selector-multiplexer 8 from the bits of the counter of the address 6 connects the next (second) input of the channels of the selector-multiplexer If there is a level corresponding to the Pass through this control input bus 15 (FIG. 2) analog information, the incoming regular (second) high frequency pulse from the pulse generator 1 to the input of the selector-multiplexer 8 gate passes to the output of the selector-multiplexer 8 and through the logical element OR 5 enters and the input of the counter is addressdv. At its output of the bits, the code combination is changed by one unit evenly, s. The information on the data inputs of the address register 9 and the selector-multiplexer address inputs changes accordingly. In this case, the records in the address register 9 are not - occurs because the impulse arrives at the input of the register entry 9 of the address with a much rarer frequency determined by the period Tc. Therefore, the switching of the analog switch 11 also does not occur, on buses 16 and 17, respectively, the address and information output of the device the information does not change, while in the selector-multiplex 8, changing the information on the address inputs results in connecting the following. (third) input of the channel ... If the third input. on the device control buses -15 there is a level corresponding to the analog information omission (fcg , 2), then all the processes in the device are repeated. If during the next (fourth) connection of the channels input the multiplexer 8 selector on the device control buses 15 there is a level corresponding to the working input of analog information, then the output selector-multiplexer 8 n stepping the input strobe pulses from the pulse generator 1 does not pass, the selector-multiplexer 8 as it were blocked for pulses on Payuschie post. entrance strobe; a. This continues until the output of the splitter 2 frequency produces a regular (intermittent) pulse of the switching cycle. This pulse arrives at the input of elements 3 and 4 of the delay and through the logical element OR 5 at the input of the address counter, 6 at the outputs of the bits the address counter 6 is generated accordingly. code combination (in this case for the input of analog information 4), which connects the next input of channels of the selector-multiplexer 8 and enters the data inputs of register 9, the address, ао After the time determined by the delay on delay element 4, to the input of register 9 the address receives the same impulse of the switching cycle, the information on this (fourth) working input of analog information is written to the register 9 address, and, from the register output 9, the information is output to the device address buses 16 and the desh inputs 10, address: through the analog switch 11, the corresponding (fourth) input of analog information to the input of the ADC is 1.2 o When the delayed on element 3 delays the same pulse of the switching cycle to the input of the ADC 12, information is digitized, and the converted information from the outputs of the bits of the ADC 12 is fed to the buses 17 of the information output of the devices, and "I A similar process occurs in the device until the counter 6 of the address overflows about the Number of bits of the counter 6 adSres per It is chosen equal to the number of analog information inputs. When the counter 6 of the address overflows, an impulse arises at its input, which triggers trigger 7 to the initial state. In this case, the latter blocks the generator of 1 pulses, a divider of 2 frequencies and a counter 6 addressd.,; The device returns to its original state, which is preserved until the arrival of the delay pulse at the input 1.4. Thus, by introducing a selector-multiplexer into the information-gathering device and organizing communication with the address counter, trigger and control buses, it expands in comparison with the known device, the functionality in terms of providing a programmable selection of the working input of analog information; By connecting from the interrogation of the information inputs that are passed through (due to the difference in the interrogation frequency of the inputs being passed and the switching frequency), the collection device provides a true compaction of the incoming information.

By using the device, it is possible to reduce the polling period of the analog information inputs and, therefore, more often to measure by the working information inputs, which helps to obtain a more accurate characteristic of the change in the incoming information,;

In addition, organizing the skipping of non-working inputs, as well as inputs at which information repeats within several polling cycles (changes slowly or slightly), can reduce the amount of subsequent memory used to store information:

When using one instance of an analog information collection device, the savings from reducing the amount of used memory will be

-Kr6 1 (

where is the total number of inputs of analog information;

slave - the number of working channels; L - the cost of the memory block,

the amount of which is appropriate. em amount of information

5 arriving at all entrances

/five

ig. /

 working Snod nponijCKatMbiu Snu8

Claims (1)

A DEVICE FOR INFORMATION INPUT, comprising a pulse generator, a frequency divider, an analog switch and an analog-to-digital converter, the output of which is the information output of the device, the output of the pulse generator is connected to the input of the frequency divider, the inputs of the analog switch are information inputs of the device, characterized in that, with In order to improve the performance of the device, an OR element, a counter, a multiplexer, a trigger, a decoder, the first and second delay elements, _(a register whose output connected to the input of the decoder and is the address output of the device, the output of the pulse generator is connected to the gate input of the multiplexer, the output of the frequency divider is connected to the inputs of the first and second delay elements and the first input of the OR element, the output of which is connected to the counter input of the counter, the reset input of which is connected to the input resetting the frequency divider, the inhibitor input of the pulse generator and the trigger output, the installation input at ¹¹ 1 of which is the trigger input of the device ', the second input of the OR element is connected to the output multiplexer, the information inputs of which are the control inputs of the device, the address' § inputs of the multiplexer are connected to the information inputs of the register and the outputs of the parallel counter code, the output of which is connected to the installation input in ^{9 bp of the} trigger, the decoder outputs are connected to the address inputs of the analog switch, the output of which is connected with the input of an analog-to-digital converter, the trigger input of which is connected to the output of the first element (delays, the clock input of the register is connected to the output of the second element delays. ":