SU1672457A1 - Computer system monitor - Google Patents

Abstract

The invention relates to computing and can be used for embedded control of asynchronous digital computing systems, as well as in equipment for automated control of digital blocks. The purpose of the invention is to expand the field of application by increasing the class of detectable faults when monitoring sequential and asynchronous digital blocks. For this purpose, the third and fourth elements AND and three elements OR are introduced into the control node containing two triggers and two AND elements. 1 tab., 7 Il.

Description

The invention relates to computing and can be used for embedded control of asynchronous digital computing systems, as well as in equipment for automated control of digital blocks.

The purpose of the invention is to expand the field of application by increasing the class of detectable faults (occurring in synchronous and asynchronous computing sleep themes) with continuous sequences and asynchronous digital blocks.

Fig. 1 shows a functional diagram of a control assembly, Fig. 2 shows a circuit for connecting a control assembly to a monitored unit for the case of

use in a known object; figure 3 is a timing diagram of the operation of the control node in the scheme shown in figure 2; FIG. 4 is a wiring diagram of a control node in a test diagnostics system operating in the single-ended mode (for synchronous computing systems); figure 5 is a timing diagram of the operation of the control node in the scheme shown in figure 4; FIG. 6 is a scheme for connecting a control node to an asynchronous computing system in standby mode; figure 7 is a timing diagram of the operation of the node control in standby mode according to the scheme shown in figure 6.

The control node (see, figure 1) contains the elements OR 1--3, triggers 4 and 5,

CN vj CE 4 SL

elements And 6-9 and has the first information input 10, the input 11 synchronization, the second information input 12, the input 13 of the initial installation, the outputs 14-17 result.

Items And 6-9 provide the formation of signals at the outputs 14-17 in accordance with the table.

In addition, figure 2 additionally shows the object 18 of the control and the node 19 of the control. In Fig. 4, in addition to the object 18 of the control and the node 19 of the control, depicts the test memory block 20, the multichannel signature analyzer 21 and the display block 22. 6, in addition to the control unit 19 and the display unit 22, the master unit 23 (active computing device), the slave unit 24 (passive computing device), the register memory unit 25, the measuring information processing unit 26 and the OR element 27 are additionally depicted.

The node works as follows.

The node can work in single-shot and standby mode.

In the single-ended mode, signals Y, Y2, Yj, Y4 are generated at the corresponding outputs 14–17 of the node when all possible combinations of input signals X. and X are input to inputs 10 and 12, respectively.

according to equation (1)

Y (X1 & X2

Yz xi & g

  X, gc X,

% xD x4

In each cycle, a single signal is formed at one of the outputs of the node, indicating the occurrence of a certain combination of input signals. Triggers 4 and 5 are installed according to the synchronization signal C, which is fed to the input 11 of the node. Initial installation of triggers 4 and 5 again. carried out before applying each clock pulse by kazachi signal R initial installation to the input 13 of the node. The signal corresponding to the logical unit from the output of the element OR 3

0

five

0

five

0

five

„

five

enters the inputs of the initial installation of the triggers 4 and 5. This mode of operation can be used when the node operates as a comparison circuit in the external means of test diagnostics (if necessary, a comparison in each step of the monitored and reference signals). In the standby mode of operation of the node, the occurrence of a certain combination of signals X and X at inputs 10 and 12 for a specified period of time is monitored. Such situations arise in the organization of asynchronous communication between computing devices on the principle of controlling — controlled (active — passive). Thus, when operating in the standby mode, the node is intended for use as part of embedded controls of computing systems with the asynchronous principle of communication.

between computing devices. i

Example. Let the active level of the control (X,) and response (X0) signals be a single level. The arrival of the active control signal X at the input 10 of the node generates at the output of the first element OR 1 a signal of a logical unit that, when it arrives at the information input of the first trigger 4, sets the trigger to one when it arrives at the input C of the unit sync pulse from the input 11 of the node. The signal corresponding to the logical unit from the direct output of the first trigger 4 is fed to the first input of the first element OR 1. The first trigger 4 is blocked in the one state. The arrival for a certain period of time t of the response signal X at the input 13 of the node generates at the output of the second element OR 2 a signal of a logical unit, which at

corresponding to the logical unit, arriving at the inputs R of the initial installation of both triggers 4 and 5. At the same time, the signal of the initial installation at input 13 is given with a period t, after which an analysis of the signals X, and X supplied to the inputs 10 and 12 is performed. In addition, both flip-flops 4 and 5 are zeroed by applying to the R inputs of the initial setup of flip-flops 4 and 5 a signal corresponding to a logical unit from the output of the third element OR 3, to the second input of which the output of the first element AND 6 receives the signal Y 1 This allows prepare the knot counter ol to receive new information for a shorter period of time.

Claims (2)

Claim of the invention A computer system control node containing two triggers and two 51 Admission to the information input of the second trigger 5 sets the trigger to one state. The signal corresponding to the logical unit from the direct output of the second trigger 5 is fed to the first input of the second element OR 2. The second trigger 5 is blocked in a single state. In the known device, only pairs of sets X, O, 1, are included in the test. Thus, situations X (1, X 1 (exchange resolution) and X. O, Xg O (pause) are not checked. In this node, there are two options for the initial installation, The initial installation signal R is supplied from the input 13 of the node to the first input of the third element OR 3, at the output of which a signal is generated corresponding to five 0 five 0 five 0 element And, the direct output of the first trigger is connected to the first inputs of the first and second elements And, the direct output of the second trigger is connected to the second input of the first element And, and the outputs of the first and second elements And are respectively the first and second outputs of the node, characterized in that, in order to expand the field of application by increasing the class of detectable faults when monitoring sequential and asynchronous digital blocks, it contains the third and fourth elements AND and three elements OR, with this The first direct outputs of the first and second triggers are connected to the first inputs of the first and second OR elements, respectively, the second inputs of which are the first and second information inputs of the node, respectively; the outputs of the first and second OR elements are connected to the information inputs of the first and second triggers, respectively; the second inputs and the output of the third element OR are connected respectively to the input of the initial installation of the node, the output of the first element AND and the reset inputs of the first and second triggers, the second input of the second element I is connected to the inverse output of the second trigger, the first inputs of the third and fourth elements I are connected to the inverse output of the first trigger, the second inputs of the third and fourth elements I are connected respectively to the direct and inverse outputs of the second trigger, and are the third and fourth outputs of the node result respectively. 70 e p oE MZV- J / C / 7). To block C control & /five . 77 In the encoder FIG. 2 Test 18 20 Etal.reacci } Fig.Z Out reaction WITH YU 27 22 start / stop Fiel WITH Request 23 Answer V r c Phage. five eleven WITH hertz With R Yu W 22 P. J eleven /9 YU 25 G7 Allow records 2S FIG. 6