SU1163361A1 - Storage fith self-check - Google Patents

Abstract

1. A SELF-MONITORING STORAGE DEVICE containing the address register, main memory, buffer memory, the input of the address register is the first input of the device, the first output of the address register is connected to the corresponding main memory input, the second output of the address register is connected to the first input of the buffer memory and the main memory input, the first output of which is connected to the second input of the buffer memory, the third input of which is the second input of the device, and the output of the buffer memory is the first output of the device, In order to increase the reliability of the device, it contains an additional memory, a word register, a search register, a control unit, an error register, a group of AND elements, an OR element, the first input of the additional memory being the third input of the device, the second input the additional memory is connected to the second input of the address register, and the output is connected to the input of the word register, which is connected to the first inverse of the elements of the AND group and the first input of the control unit, the second input of which is connected to the output of the buffer memory, one control unit is connected to the input of the error register, the output of which is connected to the second output of the device, the output of the OR element is i the third output of the device, and the input is connected to the outputs of the AND elements of the group, the second inputs of which are connected to the output of the search register whose input is connected to the second the output of the main memory, the third output of which is connected to the third input of the coitrol unit.

Description

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2. A device according to claim 1, characterized in that the control unit comprises two groups of adders modulo two, two groups of elements AND and the element AND, where the inputs of modulators modulo two of the first group are combined and are the first input of the control unit, the inputs of element AND combined and are the second input of the control unit, and the inputs of the modulo two second groups are combined and are the third input of the control unit, the outputs of the adders

modulo two of the first group are connected to the corresponding inputs of elements AND of the first group, the other inputs of which are connected to the corresponding inputs of the element I, the output of which is connected to one input of elements AND of the second group, the other inputs of which are connected to the corresponding outputs of modulators two second groups, and the outputs of the elements And groups are the corresponding outputs of the control unit.

The invention relates to computing technology and is intended for organizing a buffer memory in information processing devices with a hierarchical memory organization.

The purpose of the invention is to increase the reliability of the device.

The invention makes it possible to monitor the correct operation of the buffer memory and exclude from operation the defective blocks of the buffer memory dynamically, without accommodating the operator, which ensures high reliability of the buffer memory.

FIG. 1 shows a block diagram of a self-monitoring memory device; in fig. 2 - the main memory is functional; in fig. 3 - functional control unit diagram.

The self-monitoring memory device contains the address register 1, the main memory 2, the buffer memory 3, the additional memory 4, the register 5 words, the search register 6, the control unit 7, the error register 8, the group 9 of elements AND, the element OR 10 (Fig. 1). In addition, the first 11, second 12 and third 13 inputs of the device are designated, the first 14, second 15 and third 16 outputs of the device.

The input of the register 1 address is the first input 11 of the device, the first output of the register 1 address is connected to the corresponding input of the main memory 2, the second output of the register 1 address to the first input of the buffer memory 3 and the second, the input of the main memory 2, the first output of which connected to the second input of the buffer memory 3, the third input of which is the second input 12 of the device, and the output of the buffer memory 3 is the first output 14 of the device. The first input of the additional memory 4 is the third input 13 of the device, the second input of the additional memory 4 is connected to the second output of the register 1 address, and the output is connected to the input of the 5 register words, the output of which is connected to the first inverse

the input of elements AND of group 9 and the first input of control unit 7, the second input of which is connected to the output of the buffer memory 3. The output of control unit 7 is connected to input 5 of error register 8, the output of which is connected to the second output 15 of the device. The output of the element OR 10 is the third output 16 of the device, and the input is connected to the outputs of elements AND of group 9, the second inputs of which are connected to the output of the search register 6,

 the input of which is connected to the second output of the main memory 2, the third output of which is connected to the third input of the control unit 7. The address register 1 is intended for receiving and storing the address for accessing the operational memory.

The main memory 2 is intended for storing and issuing information about the presence of the requested data in the buffer memory and contains (Fig. 2) an index memory 17 consisting of / C columns and L rows,

0 a group of comparators 18, an encoder 19. The output of register 1 of address is connected to the first input of the index memory 17 and the first input of each comparator from group 18, the second inputs of which are connected to the corresponding outputs of the index memory 17, also connected to the third input of the control unit 7, the outputs of the comparators from group 18 are connected to the input of the search register 6 and the input of the encoder 19, the output of which is connected to the second input of the buffer memory 3,

The second output of register 1 of the address is connected to the second input of the index memory G7.

The buffer memory 3 has a block structure and consists of L rows and K columns and has a capacity of LX K data blocks. A block is a quantum of information, one-to-one

relevant information in the RAM. The buffer memory is built on a partially associative principle: the address of the column is determined by the part of the address of the address from register 1 of the address, the desired number is addressed by the result of the associative

0 main memory lookup 2. Loading

buffer memory 3 at the second input of the device 12.

Additional memory 4 is intended for storing information about the degradation of buffer memory blocks 3. The capacity of its LXK bits (K words are L bits long). If the i-th bit of degradation in the J-M word is set to "1, then the data block in the i-th row and j-th column of buffer memory 3 is inaccessible for use. The zero value of the degradation bit allows the use of the corresponding block of buffer memory 3.

Register word 5 is designed to receive and store information read from additional memory 4; bit depth is L bits.

Search register 6 is designed to record the result of an associative search in main memory 2, the bit size is L bits.

The control unit 7 is designed to organize the monitoring of the correct operation of the buffer memory 3 and the main memory 2. In the case of controlling the output information parity from the buffer memory 3 and the main memory 2, the control unit 7 (FIG. 3) contains two groups 20 and 21 modulo-two adders, two groups of 22 and 23 I elements and And 24 element. The modulo-adders two first group 20 inputs are combined and are the first input of control unit 7, And 24 element inputs are combined and are the second input of control unit 7, and the inputs of the modulo two second group nN 21 are combined and the third input of the control unit 7.

The outputs of the adders modulo two of the first group 20 is connected to the corresponding inputs of the elements of the first group 22, the other inputs of which are connected to the corresponding inputs of the element 24, the output of which is connected to one input of the elements of the second group 23, the other inputs of which are connected to the corresponding outputs of the adders module two of the second group 21. The outputs of the elements And groups 22 and 23 are the cc / b corresponding outputs of the control unit 7 and are connected to the input of the register 8 error.

Error register 8 is designed to fix the failures detected by the control unit 7 and transmitted to the information processing device.

The device works as follows.

When performing the operation for accessing the RAM, the address for accessing the RAM is received at the first input of the device (Fig. 1) and is stored in the address register 1. The lower part of the address, which determines the address of the column, simultaneously arrives at the first input of the buffer memory 3, the second input of the main memory 2 and the second input of the additional memory 4. The older part of the address from the register 1 of the address goes to the first input of the main memory 2, the presence or absence of the requested data in the buffer memory 3.

The lower part of the address goes to the index memory 17 (Fig. 2), where one of the K columns is selected. The read L cells arrive at the inputs of the respective comparators 18, where they are compared with the upper part of the address. The result of the associative search (signals from the outputs of the comparators 18) is stored in the search register 6. At the same time, the signals from the outputs of the comparators 18 are fed to the encoder 19, the output of which forms the address of the row of the buffer memory, which enters the second input of the buffer memory 3. From the address obtained from the main memory 2 of the row and the younger part

 the address (addressing column) buffer memory 3 reads the data that is transmitted to the first output of the device 14.

At the same time, L bits are read from the additional memory 4 at the lower part of the address, which are stored in word register 5.

Assume that the requested data is found in the i-th range (i-th bit of register 6

search is set to a single value). In this case, if this block of buffer memory 3 is not disabled (the 1st bit of register 5 words is reset to zero), the output of the i-ro element And group 9 initiates a single signal, which, having passed the element

0 OR 10, enters the third output of the device, indicates the presence of valid data in the buffer memory 3 and allows their use.

If this block of buffer memory is disabled, then the G-th bit of the word register has

5 is a single value (read from additional memory 4) and there is no single signal at the output of the i-th element AND group 9. In this case, the output of the element OR 10 is a zero signal, which prohibits the use of data from the buffer memory 3 and initiates the need to form a memory access. The information read from the buffer memory 3 and the index memory 17, together with the control bits, goes to the block

g 7 control, where it is controlled by parity.

The contents of the selected column of the index memory 17 (L cells) are fed to the input of modulo-two adders of the first group 20. The control results are sent to the output

elements of the first group 22 and are recorded in the register of 8 errors, if the inverse inputs of these elements are zero signals (the degradation bits in the register 5 words are set to zero).

If a failure in the 1st cell data is detected

The 5th index memory 17 and the 1st bit of the register of the 5th word is set to one, this failure is considered invalid (at the output of the i-th element AND of the first group 22

zero signal), i.e., the failure is not recorded in the 8 error register.

The data from the buffer memory 3 is controlled by parity on modulo-two adders of the second group 21. The result of the control is transmitted to the output of the AND elements of the second group 23 if the output of the AND 24 element contains a zero signal (not all degradation bits in the register 5 words in one state nii).

Thus, the blocking of buffer memory failures is accomplished when the entire column of the buffer memory is turned off. If a fault is detected in the 8 error register during the access to the RAM, in the i-th cell of the addressable column of the index memory 17 (the i-th bit of the error register is one), a single signal from the second output 15 of the device causes a firmware interrupt, in which results in a migration to the fault handling firmware.

This firmware, if necessary, sets the corresponding bit in the additional memory 4. For this purpose, the third input 13 of the device is used.

Thus, the further use of the buffer memory block corresponding to the failed index memory cell,

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is prohibited. So, if as a result of an associative search in the main memory 2, the i-th bit of the register 5 words and the search register 6 is set to one, the output 5 of the i-ro element And group 9 sets a zero signal, which prohibits the use of data from The i-th buffer memory cell despite the fact that the main memory 2 showed that the requested data is contained in the buffer memory 3.

In addition, the single 1st bit of the register 5 word blocks the output of a fault — the i-th cell of the index memory 17, which allows, after a shutdown, not to react to faults in the given cell.

Similarly, if a data failure of the buffer memory 3 is detected, the corresponding data block or the entire column is disabled (in this case, the faults detected in the output data of the buffer memory 3 are blocked).

The proposed device monitors the correct operation of the buffer memory, and allows you to exclude from operation the defective blocks of the buffer memory dynamically, without operator intervention, which ensures high Reliability of the buffer memory.

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Claims (2)

1. A MEMORY DEVICE WITH SELF-CONTROL, containing an address register, main memory, buffer memory, wherein the input of the address register is the first input of the device, the first output of the address register is connected to the corresponding input of the main memory, the second output of the address register is connected to the first input of the buffer memory and the second input main memory, the first output of which is connected to the second input of the buffer memory, the third input of which is the second input of the device, and the output of the buffer memory is the first output of the device, distinguishing the fact that, in order to increase the reliability of the device, it contains additional memory, word register, search register, control unit, error register, group of AND elements, OR element, and the first input of additional memory is the third input of the device, the second input of additional memory is connected with the second input of the address register, and the output is connected to the input of the word register, the input of which is connected to the first inverse input of the AND elements of the group and the first input of the control unit, the second input of which is connected to the output of the buffer memory, output b the control lock is connected to the input of the error register, the output of which is connected to the second output of the device, the output of the OR element is the third output of the device, and the input is connected to the outputs of the elements AND groups, the second inputs of which are connected to the output of the search register, the input of which is connected to the second output of the main memory , the third output of which is connected to the third input of the control unit. ns Fig.] ABOUT 2. The device according to π. 1, characterized in that the control unit contains two groups of adders modulo two, two groups of elements And and element And, and the inputs of adders modulo two of the first group are combined and are the first input of the control unit, the inputs of the element And are combined and are the second input of the control unit and the inputs of the adder modulo two of the second group are combined and are the third input of the control unit, the outputs of the adders modulo two of the first group are connected to the corresponding inputs of the elements And of the first group, the other inputs of which are connected to the inputs of the And element, whose output is connected to one of the inputs of the And elements of the second group, the other inputs of which are connected to the corresponding outputs of the adders modulo two of the second group, and the outputs of the And elements are the corresponding outputs of the control unit.