SU1674252A1 - Backup memory units - Google Patents

Abstract

The invention relates to computing and can be used in information processing systems. The aim of the invention is to increase the yield of memory chips. The device contains (K + 1) memory matrices 1, two of which are redundant, N row address decoder 2, N column address decoder 3, N row address code 5 converters, N column code 4 address converters, programmable logic matrix 6, switches of output 7 and input 8 data, switches of backup rows 9 and columns 10, selectors of the address of backup rows 11 and backup columns 12. The device eliminates multiple failures when using backup memory arrays containing defective columns and rows. 2 Il.

Description

About vj 4Ь Ю СЛ Ю

The invention relates to computing and can be used in information processing systems.

The aim of the invention is to increase the yield of memory chips.

Figure 1 shows a block diagram of a storage device with redundancy; figure 2 is an example of the principle of operation of a storage device with redundancy.

The device contains memory matrices 1.1-1.N, N decoders for row addresses 2.1-2.N and N decoders for column addresses 3.1-3.N, N converters for address code columns 4.1-4.М, N converters for address code rows 5.1- 5.N, programmable logic array 6 (PLA), output data switch, input data switch 8, first 9.1 and second 9.2 standby row switches, first 10.1 and second 10.2 standby switches, spare row address selector 11 and address selector 12 backup columns.

The principle of operation of the redundant storage device is as follows.

Memory matrices 1.1-1.N may contain defective columns, rows, or individual cells, the location of which is predetermined during technological testing or storage testing by the operating system. The code converters for the address of the column 4.1-4.N and the addresses of row 5.1-5.N are, for example, storage devices whose address input receives the addresses of the column and the row, respectively, and the contents of the cells are the actual number of the used column or row of the memory matrix. ti. If technological testing of memory arrays is carried out, then the address converters can be permanent memory devices programmed in the process of making crystals. When testing by the operating system, RAM can be used as converters during the testing process. The blocks and communications necessary for entering information into the address transformers in the latter case are not critical for the operation of the proposed device and are not shown in the functional diagram. The amount of additional memory required for storing information in address converters is small compared with the volume of basic matrices. So, with a matrix size of 256 kbps, its size is 512 rows by 512 columns, the required amount of additional 9K memory, i.e. less than 4% of main memory.

If the total number of defective rows in all memory matrices does not exceed the number of rows of a single matrix, and the total number of defective columns in all memory matrices does not exceed the number of columns of a single matrix, always by transforming the row and column addresses you can achieve the address was no more than one defective row and no more than one defective column. Therefore, after address conversion, the maximum error rate will be 2 (there is a defective row in one matrix, a defective column in the other). Therefore, to eliminate defects, it is sufficient to have two reserve matrices — a matrix of reserve rows and a matrix of reserve columns. But if there are simultaneously defective rows and defective columns in the backup matrices, it is impossible to simply switch the data from the main matrix to the backup matrix, since there will still be a defective area (defective columns in the matrix of the reserve rows and defective rows in the matrix of the reserve columns). At the same time, suitable areas can be identified in the backup matrices that do not take part in storing data. These are memory cells located: in the matrix of reserve rows - by addresses of memory cells formed by defective rows and columns in the matrix of spare columns: in the matrix of spare columns - by addresses of memory cells formed by defective rows and columns in the matrix of backup rows. If the address is now filed so that it falls on the defective row in the main matrix and on the defective column in the backup row matrix, then you can put the data not in the backup row matrix, but in the backup column matrix. Similarly, you can do when the filed address falls on the defective column in the main matrix and on the defective row in the matrix of defective columns.

By taking all this on an example. After redirection, suppose that the defective rows and columns are located in the memory matrices, as shown in Fig. 2 (the right-hand hinges for each matrix indicate the areas of the defective rows, and the left-shaded ones - the areas of the defective columns). If, for example, at the specified address, the 1st row area and the 3rd column area are accessed, a double error is possible, which is eliminated by redirecting data from the 1st and 3rd matrices to the backup row matrix and matrix of reserve columns. If, for example, but the specified address is accessed by the 1st row area and the 5th column area, then a one-time error may occur that should be eliminated by forwarding the data from the 1st matrix to the backup row matrix, but for a defective column at this address, you need to place the data in the area shown by horizontal shading in the matrix of reserve columns. This can be done because there is no need to place data in this area in any other cases, since there are no defects in the main matrices at these addresses. Similarly, if, for example, a address to the 1st column area and to the 6th row area occurs at a given address, then a one-time error is possible that should be eliminated by transferring data from the 1st matrix to the matrix of the reserve columns. but because of a defective row at this address, you must put the data in the area shown by vertical hatching in the matrix of backup rows.

The operation of the redundant storage device is as follows.

Memory matrices 1.1-1.N may contain defective columns, rows, or individual cells, the location of which is predetermined during technological testing or memory storage by the operating system. The obtained information is used by the converter 5 of the code of the address of the rows and the converter 4 of the code of the address of columns (as described above), as well as for burning the PLA 6 (which can be played, for example, by the ROM). The PLM is formed so that at a given address at the first J inputs there appears a code equal to the number of the matrix containing the defective row, and at the outputs J 2J-1 (numbering starts with zero) - a code equal to the number of the matrix containing the defective column. Data arriving at the input of the memory in the absence of defects at a given address, comes through the switch 8 input data to the data inputs of the main matrix.

If at the given address there is a defective row and a defective column located in the matrices of the main accumulator, then at the outputs of the PLA from 0th to J - the 1st code appears, equal to the number of the matrix with the defective row, and at the exits with J-ro by - code equal to the number of the matrix with the defective column. At the output of the selectors 11, 12, the addresses will not be active levels. Therefore, when writing, data from the matrix with the defective row and from the matrix with the defective column will be placed in the Nth and N-1th memory matrices, respectively. With

reading data from a matrix with a defective row and from a matrix with a defective column will be replaced with data from the Nth and N-1th memory matrices, respectively.

If at the given address there is a defective row located in the matrices of the main accumulator and a defective column in the matrix of the reserve rows 1 .N-1, then a code equal to the matrix number c appears at the outputs of the PLM from 0 to J-1 defective line, and at the outputs from J-ro to - code equal to N-1 (matrix of reserve rows). The output of the address selector 11 will not be the active level, and the output of the column address selector 12 will be active. Consequently.

5, when writing, data from a matrix with a defective row through the switch 8 of the input data and the switch 10.1 of the reserve columns will be placed in the matrix 1.N of the memory. When reading data from a matrix with a defective

0 by the line through the switch 9.2 of the backup lines and the switch 7 of the output data will be replaced by the data from the memory matrix 1.N.

If at the given address there is a defect5 column located in the matrices of the main accumulator and a defective row in the backup row matrix 1.N, then a code equal to N appears at the outputs of the PLM from 0 to J-1 (the backup matrix columns), and

0 at the outputs with J-ro no 2J-1-U - code. equal to the number of the matrix with a defective column. The output of the address selector 11 will be the active level, and the output of the column address selector 12 will be inactive. Consequently.

when writing, the data from the matrix with the defective row through the switch 8 input data and the switch 9.1 of the reserve rows will be placed in the matrix 1.N-1 of the memory. When reading data from a matrix with a defective

0 by the row through the switch 10.2 of the reserved columns and the switch 7 of the output data will be replaced by the data from the 1N memory matrix.

The defects of the individual cells of the decrypted 5 DOB rows, the column decoders can be equated to the defects of the rows or columns and eliminated in the same way.

The device has the ability to eliminate multiple errors and use memory matrices containing both defective rows and defective columns as backup drives.

Claims (1)

Invention Formula 5 A redundant storage device containing a K memory matrix, where K is the number of bits, one of which is a backup, K row address decoders and K column address decoders, the outputs of which are connected to the row and column address inputs of the corresponding memory matrixes, programmable a logical matrix whose inputs are the address inputs of rows and columns of the device, an input data switch, the K-1 information outputs of which are connected to the data inputs of the corresponding memory matrices, the data outputs of which Connected with the corresponding information inputs of the output switch, the information outputs of which are the information outputs of the device, the information inputs of the switch of the input data are information inputs of the device, which are different in that, in order to increase the output of usable memory chips, additional the backup memory matrix, the row address decoder and the column address decoder, the outputs of the connectors are connected to the address inputs of the rows and columns, respectively Redundant memory array, K + 1 lines of code converters address. K + 1 column address code converters, first and second backup row switches, first and second backup column switches, reserve row address selector, backup column address selector, row address code transformer inputs are combined and connected to the address inputs of a programmable logic matrix, address inputs columns of which are connected to the inputs of the address code converters of columns whose outputs are connected to the inputs of the corresponding address decoders columns, outputs of the address row address converter are connected to the inputs of the corresponding row address decoders, the K-th and (K + 1) -th information outputs of the input data switch are connected to the information inputs of the first switch of the backup rows and the first switch of the backup columns, whose information outputs are connected respectively with first and additional data inputs backup memory matrices, the data outputs of which are connected to the information inputs of the second switch of the backup rows and the second switch of the backup columns, the information outputs of which are connected respectively to the Km and (K-1) - m information inputs of the output switch, the control inputs of the first switch backup rows and second switch backup columns connected to the outputs of the backup row address selector, the control inputs of the first switch of the backup columns and the second switch of the backup rows are connected to the outputs of the backup row address selector the columns, the control inputs of the switches of the input and output data are connected respectively to the inputs of the selectors of the address of the reserve rows and columns and to the outputs of the programmable logic array.