JPH11163847A - Data receiving device and data transmission system - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To receive transmission data at high speed and reliably without being influenced by environmental conditions. SOLUTION: In a data receiving device 3 capable of reading transmission data transmitted from a data transmission device 2 in synchronization with a data reading clock having a period equal to the transmission period, a plurality of data transmission devices having a period equal to the transmission period and different phases are provided. A clock generating unit 35 for generating a clock of a predetermined clock; a data reading unit 31 for reading transmission data using one of a plurality of clocks determined according to a predetermined condition as a data reading clock; Is included, a pattern data reading unit 31, which reads data of a predetermined pattern in synchronization with each of the plurality of clocks,
39, and a data reading clock determining unit 34 that determines one of a plurality of clocks as a new data reading clock in accordance with a predetermined rule based on the plurality of reading data read by the pattern data reading unit. Have.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving apparatus and a data transmission system, and more particularly to a data receiving apparatus and a data transmitting system which are suitably used for a measuring apparatus having a measuring unit for transmitting measured data and a measuring apparatus main body for receiving the measured data. And a data transmission system.

[0002]

2. Description of the Related Art For example, a plurality of types of amplifier units corresponding to signals to be measured such as voltage, current and temperature are prepared in advance as options, and an amplifier unit corresponding to a signal to be measured is appropriately selected and mounted on a main body. By doing
2. Description of the Related Art A waveform display device capable of performing multipurpose measurement has been conventionally known. This waveform display device includes an amplifier unit and a main body. Here, the amplifier unit transmits to the main body the digital data converted by sampling the signal to be measured amplified or attenuated by a predetermined gain. Specifically, the amplifier unit includes an A / D converter that inputs a signal to be measured and converts the signal into digital data that is parallel data, and converts the converted parallel data into serial data and converts the converted serial data. And a photocoupler for transmitting the converted serial data to the main body while maintaining an insulated state with respect to the main body.

On the other hand, the main body performs reception of measurement data, display of a waveform or the like based on the measurement data, printing, and the like.
As a specific configuration, the main body unit includes a clock generation unit that generates various clocks, and the clock generation unit includes:
A system clock, a sampling clock for sampling by the A / D converter of the amplifier unit, a data transmission clock that is a synchronization signal for transmitting serial data by the P / S converter of the amplifier unit, and serial data for the main unit. A data reading clock, which is a synchronization signal for receiving the data, is generated. The main unit includes a data reading unit for reading serial data transmitted from the amplifier unit, and a photocoupler for transmitting a sampling clock and a data transmission clock to the amplifier unit while maintaining an insulation state with respect to the amplifier unit. And

Next, a procedure of data transmission between the main unit and the amplifier unit will be described with reference to a timing chart shown in FIG.

As shown in FIG. 1A, at time t1, when a sampling clock is output from the clock generation unit of the main unit, the A / D conversion unit of the amplifier unit performs the sampling input via the photocoupler. In synchronization with the rise of the clock, the signal to be measured is sampled and converted into parallel data. Next, the P / S converter converts the parallel data into serial data in synchronization with the rising edge of the data transmission clock shown in FIG. 2C input via the photocoupler, and transmits the data to the main body via the photocoupler. Send. In this case, the data transmission clock is the system clock shown in FIG.
Since the data is generated by frequency division, the transmission cycle for one bit of serial data is set to a time T0 corresponding to a time corresponding to two cycles of the system clock.

At this time, the sampling clock transmitted from the main unit to the amplifier unit and the serial data transmitted from the amplifier unit arrive at the amplifier unit and the main unit, respectively, with a delay time caused by a response delay of the photocoupler. I do. Therefore, when the P / S converter transmits the serial data having the value “1”, the sampling clock of the serial data is output from the clock generator of the main unit as shown in FIG. Time t1
At the time t2, which is delayed by the response delay time T1 by both the photocouplers of the main unit and the amplifier unit from the time, the data reaches the data reading unit of the main unit.

On the other hand, as shown in FIG. 1 (e), the data reading section of the main body section has a data reading clock in which a time longer than the response delay time T1 of both photocouplers is delayed in advance by a phase with respect to the sampling clock. , The serial data is read at time t3. Next, the data reading unit reads the next serial data at a time t4 delayed by the transmission cycle T0 from the time t3. Similarly, the data reading unit reads the subsequent serial data every transmission cycle T0. As described above, the serial data is transmitted from the amplifier unit to the main unit by the serial data being read by the data reading unit in synchronization with the data reading clock.

[0008]

However, this waveform display device has a response delay time T1 of the photocoupler described above.
When the data varies due to a temperature change or the like, there is a problem that the data reading unit may not be able to read the transmission data correctly.

Specifically, for example, when the response delay time T1 of the photocoupler varies according to the fluctuation of the ambient temperature or the like, the minimum response delay time T11 until the serial data reaches the data reading section of the main body (FIG. 7). (F)) and
The difference from the maximum response delay time T12 (see (g) in the figure) (hereinafter referred to as “variation time of response delay”) is the transmission cycle T.
May exceed zero. In such a case, since there is no period in which the serial data at the minimum response delay time T11 and the serial data at the maximum response delay time T12 overlap and exist, the serial data must be read reliably. Can not.

On the other hand, as shown in FIGS.
By lengthening the transmission cycle of serial data by about twice, the serial data when the response delay time due to temperature change is minimum and the serial data when the response delay time is maximum are overlapped in time. It is also possible for them to be present. In this case, by reading the serial data during a period in which the two serial data overlap, even if the response delay time varies due to a temperature change or the like, the serial data can be read reliably. However, in such a case, as a result of lowering the data transmission speed, another problem that transmission and reception of serial data cannot be performed at high speed occurs. Also in this case, high-speed transmission and reception can be ensured by transmitting and receiving parallel data. However, in such a case, in order to insulate between the amplifier unit and the main body, it is necessary to provide a photocoupler as an insulating means in each parallel data transmission path. There is a problem that the manufacturing cost of the entire waveform display device increases.

The present invention has been made in view of such a problem, and is not affected by environmental conditions such as temperature change.
It is a main object of the present invention to provide a data receiving device and a data transmission system capable of receiving transmission data transmitted from a data transmitting device at high speed and reliably.

[0012]

According to a first aspect of the present invention, there is provided a data receiving apparatus for reading transmission data transmitted from a data transmission apparatus with a period equal to a transmission period of a unit bit in the transmission data. In a data receiving device configured to be readable in synchronization with a clock, a clock generating unit that generates a plurality of clocks having a period equal to the transmission period and different phases from each other, and a plurality of clocks determined in advance according to predetermined conditions Any one of the clocks
A data reading unit that reads transmission data using one of them as a data reading clock; and a pattern data reading unit that reads data of a predetermined pattern in synchronization with each of a plurality of clocks when data of a predetermined pattern is included in the transmission data. Data reading unit for determining one of a plurality of clocks as a new data reading clock in accordance with a predetermined rule based on a plurality of read data read by the pattern data reading unit in synchronization with the plurality of clocks And a clock determining unit.

In this data receiving apparatus, when power is turned on or transmission is started, the clock actually used as the data reading clock is one of a plurality of clocks generated by the clock generating unit in accordance with a predetermined condition. Are determined in advance. On the other hand, during normal data reception, the pattern data reading unit reads the data of the predetermined pattern in synchronization with each of the plurality of clocks when the transmission data includes the data of the predetermined pattern. In this case, the plurality of clocks are synchronized with the transmission cycle of the unit bit in the transmission data, and have different phases. Therefore, each data corresponding to the predetermined pattern read in synchronization with the plurality of clocks is a different type of pattern according to the delay time of the transmission data due to the delay element between the data transmitting device and the data receiving device. For this reason, for example, by associating in advance the type of the pattern to be read and the type of the clock having the optimum phase for reliably reading the transmission data in the state of the delay time when each pattern occurs, the The clock determination unit determines the most appropriate clock as a new data reading clock according to the type of the pattern that has received the predetermined pattern according to the association as a predetermined rule. Therefore, even when the delay time due to the delay element changes due to a change in the ambient temperature or the like, an appropriate clock can be determined as the data reading clock in accordance with the change in the delay time, so that the transmission data can be transmitted at high speed. In addition, it is possible to reliably receive.

According to a second aspect of the present invention, there is provided the data receiving apparatus according to the first aspect, wherein the data reading clock determining unit is an exclusive OR between the plurality of read data read by the pattern data reading unit. The data reading clock is determined based on

It is also possible to detect a change in delay time based on data obtained by reading a predetermined pattern by a plurality of clocks. On the other hand, in this data receiving device, the data reading clock determining unit determines the data reading clock based on the exclusive OR of the plurality of read data read by the pattern data reading unit. In this case, for example, a change in the delay time can be detected by comparing the exclusive OR of the predetermined pattern that has already been determined with the exclusive OR obtained when the predetermined pattern is read. Therefore, for example, when the data reading clock determination unit is configured by an integrated circuit such as a CPU, the number of data to be input to the integrated circuit can be reduced.
This makes it possible to effectively utilize the input terminals of the integrated circuit.

According to a third aspect of the present invention, in the data receiving apparatus according to the first or second aspect, the data of the predetermined pattern includes 3-bit data in which the levels of adjacent bits are different from each other. It is characterized by the following.

The type of the predetermined pattern can be determined as appropriate. On the other hand, as a predetermined pattern, 3-bit data in which levels of adjacent bits are different from each other, for example, “01”
If "0" or "101" is used, intermediate bit data ("1" or "0" in the above example) is read in synchronization with a plurality of clocks, respectively, and the delay time of the read intermediate bit data is A change in delay time due to a delay element between the data transmitting device and the data receiving device can be detected. In addition, at least 3
A change in delay time can be detected simply by transmitting and receiving a predetermined pattern of bits. Therefore, it is possible to determine the most appropriate read data in a short time after the change.

According to a fourth aspect of the present invention, there is provided a data transmission system including the data receiving apparatus according to any one of the first to third aspects and a data transmitting apparatus.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the accompanying drawings, a data receiving apparatus and a data transmission system according to the present invention will be described below.
An embodiment applied to a waveform display device will be described.

As shown in FIG. 1, a waveform display device 1 according to an embodiment of the present invention includes an amplifier unit 2 corresponding to a data transmitting device according to the present invention, and a main unit 3 corresponding to a data receiving device according to the present invention. It is comprised including. Here, the amplifier unit 2 is configured to be detachable from the main body 3, and a plurality of types according to signals to be measured such as voltage, current, and temperature are prepared in advance as options. For this reason, by attaching the amplifier unit 2 corresponding to the type of the signal to be measured to the main body 3, the two constitute the waveform display device 1 integrally.

First, the outline of the waveform display device 1 will be described. In the waveform display device 1, for example, when a voltage signal is used as a signal to be measured, the voltage signal SIN is input to the amplifier unit 2 via a probe (not shown), so that the amplifier unit 2 samples the voltage signal SIN. After converting the data into waveform data which is digital data, the waveform data is transmitted to the main unit 3. on the other hand,
The main unit 3 receives the waveform data, and based on the received waveform data, can display the signal waveform of the voltage signal SIN on the display unit or print it with a printer.

Next, the configuration of the waveform display device 1 will be described with reference to FIG.
This will be described with reference to FIG.

The amplifier unit 2 includes, for example, an attenuator 21 for attenuating a voltage signal SIN as a signal to be measured by a predetermined attenuation, a range amplifier 22 for attenuating or amplifying the voltage signal SIN with a predetermined gain, An A / D converter 23 that generates waveform data as 12-bit parallel data by sampling SIN in synchronization with a sampling clock transmitted from the main unit 3;
A P / S converter 24 for converting waveform data, which is 2-bit parallel data, to serial data and outputting serial data synchronized with a data transmission clock transmitted from the main unit 3, and generating a predetermined test pattern And a photocoupler 26 for insulating the amplifier unit 2 and the main unit 3 from each other and transmitting the serial data output from the P / S converter 24 to the main unit 3.

On the other hand, the main unit 3 corresponds to a data reading unit in the present invention, and converts a waveform data, which is serial data transmitted from the amplifier unit 2, into parallel data. A DMA controller 32 for transferring the obtained waveform data to a data RAM 33 to be described later, and a data RAM for storing the waveform data.
33, a CPU 34 which corresponds to a data reading clock determining unit in the present invention and incorporates an internal register described later and executes various controls in the waveform display apparatus 1, a clock generating unit 35 described later, , 37, and 45, a data reading clock selector 38 for selecting a clock for data reading from the four types of clocks transmitted from the amplifier unit 2, and a CPU 34 together with the pattern data reading in the present invention. A data change information generation unit 39 corresponding to the
A display unit 40 for displaying signal waveforms and the like; a printer 41 for printing signal waveforms and the like displayed on the display unit 40;
An operation unit 42 in which various operation switches are provided, and a CPU
A ROM 43 for storing an operation program of a data 34, a clock determination table for data reading described later, a clock change table, and the like, and a RAM 44 for temporarily storing a calculation result of the CPU 34 and the like are provided.

The clock generator 35 generates various clocks. For example, the clock generator 35 oscillates a 48 MHz reference signal shown in FIG. 24C shows a system clock of 24 MHz, a clock for transmitting data of 12 MHz shown in FIG. 14D, a sampling clock of 1 MHz shown in FIG. 14A, and 12 M clocks shown in FIGS.
And four kinds of clocks CKA to CKD. Here, the system clock is output to the CPU 34 and used as an operation clock. The sampling clock is supplied to the amplifier unit 2 via the photocoupler 37.
And is used as a sampling clock. The data transmission clock is
The signal is supplied to the P / S converter 24 of the amplifier unit 2 via the photocoupler 36 and is used as a clock for synchronizing the serial data DS. Further, clocks CKA to CK
D is supplied to a data reading clock selecting unit 38 and a data change information generating unit 39, and as will be described later, one of them is used as a data reading clock when reading the serial data DS. It is used as a read clock for generating data change information which is a reference when changing the type of the clock for use. Note that each of the clocks CKA to CKD is synchronized with the unit bit transmission cycle (equal to the cycle of the data transmission clock) in the serial data DS, and the rising edge of the clock is equal to the rising edge of the data transmission clock. , 0 degrees, 90 degrees, 180 degrees, and 270 degrees.

As shown in FIG. 2, the data change information generator 39 includes four D-FFs (D-type flip-flops) 51 to 54 and three EX-ORs (Exclusiv).
e OR) 55-57. In the data change information generation unit 39, the D-FFs 51 to 54 convert the serial data DS transmitted from the amplifier unit 2 into four.
Latch data D1a to D1d are generated by latching in synchronization with the clocks CKA to CKD. The EX-ORs 55 to 57 store the latch data D1.
The exclusive OR is calculated between a and D1b, between D1b and D1c, and between D1c and D1d, and data change information D as the calculation result is calculated.
ab, Db-c, and Dc-d are output to the CPU 34, respectively.

Next, the overall operation of the waveform display device 1 will be described. In addition, in order to make the explanation easy to understand,
Any one of the clocks CKA to CKD has already been determined by the CPU 34 as a data reading clock,
When the clock selection signal SS is output from U34, the clock specified by the selection signal SS is used as the data read clock as the data read clock selector 38.
To the S / P converter 31. A clock determination process in which the CPU 34 determines any one of the four types of clocks CKA to CKD as a data reading clock will be described later.

First, the clock generator 35 of the main body 3
However, as shown in FIG. 3A, at time t21, a sampling clock is output to the A / D converter 23 of the amplifier unit 2 via the photocoupler 37, and a data transmission clock is output via the photocoupler 36. Output to the P / S converter 24. The A / D converter 23 converts the input signal Sin input via the attenuator 21 and the range amplifier 22 into parallel data DP, and outputs the parallel data DP to the P / S converter 24. The P / S converter 24 converts the parallel data DP into serial data DS in synchronization with a data transmission clock, and converts the converted serial data Ds.
S is output to the photocoupler 26. In this case, as shown in FIG. 3 (i), the P / S converter 24 generates, in this order, 12-bit serial data DS of one frame from the least significant bit D0 to the most significant bit D11, and , In this order. Thus, the amplifier unit 2
The serial data DS is output every period of the sampling clock in synchronization with the data transmission clock.

Next, the S / P converter 31 of the main body 3
The serial data DS transmitted from the amplifier unit 2 is sequentially converted into parallel data DP in synchronization with the data reading clock output from the data reading clock selector 38, and then output to the DMA controller 32. D
The MA controller 32 transfers the parallel data DP to the data RAM 33 and stores it in the data RAM 33, and outputs a transfer end signal STE to the CPU 34.
The CPU 34 responds to an operation signal from the operation unit 42 to
By outputting the transfer command signal STS to the A controller 32, the parallel data DP stored in the data RAM 33 is read, and the signal waveform of the input signal SIN is displayed on the display unit 40 based on the read parallel data DP.
To be displayed. Further, the CPU 34 causes the printer 41 to print the signal waveform displayed on the display unit 40 according to the operation signal of the operation unit 42.

Next, the clock determining process by the CPU 34 will be described with reference to FIG.

First, at the start of transmission, such as when the power is turned on, or when the test data transmission switch provided on the operation unit 42 is operated (at time t31 shown in FIG. 4), the CPU 34
Is transmitted to the test data generator 2 via the photocoupler 45.
5 and outputs the test data transmission signal STD to the data reading clock selector 38.
By outputting AO, four types of clocks CKA-C
KD are sequentially output. The test data generation unit 25
For example, one frame of test data DTE in which D0, D1, and D2 include patterns of values "0", "1", and "0" are output to the / S converter 24, respectively. P /
The S converter 24 converts the test data DTE into serial data DS in synchronization with the data transmission clock,
The data is transmitted to the main unit 3 via the photocoupler 26.

Next, the S / P converter 31 of the main body 3
With respect to D1 in the test data DTE, the clock CKA sequentially output from the data reading clock selecting unit 38
To CKD, and outputs the latched four data to the DMA controller 32 as pattern data. More specifically, as shown in FIG. 6F, at time t32, it is synchronized with the clock CKA, at time t33, it is synchronized with the clock CKB, and at time t3.
4, the test data DTE is latched in synchronization with the clock CKD at time t35 and in synchronization with the clock CKD at time t35, and the latched four data Da, Db, Dc, D
The pattern data composed of d is output to the DMA controller 32. The DMA controller 32 transfers the pattern data to the data RAM 33 for storage, and
A transfer end signal STE is output to U34. CPU3
4 indicates a transfer command signal S to the DMA controller 32.
By outputting the TS, the pattern data stored in the data RAM 33 is read. Next, the CPU 34
Based on the read pattern data, one of CKA to CKD is determined as a data read clock according to a data read clock determination table stored in the ROM 43 in advance.

More specifically, as shown in FIGS. 4F to 4M, the value of D1 in the pattern data read by the four types of clocks CKA to CKD is the response delay time of the photocouplers 26, 36, and 37. In accordance with at least eight types of delay patterns 1 to 8 caused by such variations,
Eight types of pattern data are generated by the S / P converter 31. FIG. 5 shows the contents of a data reading clock determination table stored in the ROM 43. This table shows the clocks CKA to CKA for each pattern data 1 to 8 consisting of combinations of the values of Da to Dd.
Means which of KD should be determined.

For example, the delay pattern 1 shown in FIG.
, Da = “1”, Db = Dc = Dd = “0”, and the data D read in synchronization with the clock CKA
Since only a is a normal read value, as shown in the column of pattern data 1 in FIG.
Is determined as the data reading clock. FIG.
In the case of the delay pattern 2 shown in (g), Da = Db =
"1", Dc = Dd = "0", and the clock CK
Data Da read in synchronization with A and CKB, respectively
, Db are normal read values. In this case, the clock C
Either KA or CKB can be determined as the data reading clock. However, the CPU 34 determines the clock CKA that can read the serial data DS more stably as the data reading clock in response to a change in the delay time. I do. Similarly, in the case of the delay patterns 3 to 7 shown in FIGS. 4H to 1L, the CPU 34 reads the data D1 having the value "1" more stably from the clocks which can be read normally. A possible clock is determined as a data reading clock. On the other hand, in the case of the delay pattern 8 shown in FIG. 4 (m), since Da = Db = Dc = Dd = "0", and the data D1 could not be read properly regardless of any clock, the data The clock for reading cannot be determined. In such a case, the CPU 34
The fact is displayed on the display unit 40 as a data reading error.

By determining the data reading clock according to the above-described procedure, the photocouplers 26, 36, 3
7, the S / P converter 31 can reliably read the transmission data even if the transmission data, which is the serial data DS, has a variation in the delay time due to manufacturing variations such as 7. As a result, it is possible to eliminate the need for a photocoupler sorting operation and the like, and it is possible to receive transmission data quickly and reliably without being limited by variations in delay time. According to the configuration shown in the present embodiment, if the variation in the delay time of the transmission data is within about 1.5 times the transmission cycle of the unit bit, the transmission data can be read normally. it can. The contents of the test data DTE and the clocks CKA to CKA
The number of readings by KD is appropriately changed, and the clock C
By shifting the timing of reading the transmission data by KA to CKD, the transmission data can be reliably read even if the delay time of the transmission data varies extremely.

Next, during normal data transmission, when the delay time of transmission data changes, the CPU 34
Will be described with reference to FIG.

During normal data transmission, the S / P converter 31 reads the serial data DS and converts it into parallel data DP in synchronization with the data reading clock determined in the transmission data reading clock determination processing described above. . In this case, the CPU 34 stores parallel data DP corresponding to one frame of the latest read serial data DS in an internal register. CPU3
Reference numeral 4 denotes twelve latest data change information Da-b, D corresponding to each bit in one frame of the serial data DS generated by the data change information generator 39.
bc and Dc-d (total 36) are also stored in the internal register. The CPU 34 generates parallel data DP including a predetermined pattern in which the values of three consecutive bits are “0”, “1”, and “0” (hereinafter, this parallel data DP is also referred to as “predetermined pattern parallel data DP”). )
Is read, the data change information Da-b, Db-c, and Dc-d corresponding to the value "1" are read from the internal register.

In this case, for example, the current delay time is as shown in FIG.
Is the delay pattern 4 shown in FIG.
Is determined based on the clock CKB based on
Data change information Da-b, Db-c, D read by U34
In the case of cd, all the signals Da to Dd originally take the value "1", and as a result, all the data change information takes the value "0" as shown in the delay pattern 4 in FIG. On the other hand, when the delay time of the serial data DS changes due to a change in the ambient temperature or the like, the delay pattern changes from the delay pattern 4 to, for example, the delay pattern 5, as shown in the delay pattern 5 in FIG. Since Da to Dd have the values "0", "1", "1", and "1", respectively, the data change information Da-b, Db-c, and Dc for the bit of the value "1" in the predetermined pattern. -d has a value "1", a value "0", and a value "0", as shown in the delay pattern 5 of FIG. As a result, the CPU 34
By referring to the clock change table stored in the OM 43, since the value is different from the delay pattern 4 shown in the figure, it is determined that the delay time has changed to the delay time corresponding to the adjacent delay pattern 5. In this case, the delay time gradually changes stepwise. Therefore, the CPU 34
Is data change information Da- about delay patterns 1 and 5.
b, Db-c, and Dc-d are the same as each other, but it is almost impossible to directly change from the delay time corresponding to the delay pattern 4 to the time corresponding to the delay pattern 1, so that the delay pattern 5 Is determined to have changed to the delay time corresponding to.

Next, the CPU 34 determines the data reading clock as the optimum clock CKC in the delay pattern 5, and sends the data reading clock from the clock CKB to the clock CK to the data reading clock selector 38.
Change to C. Thereby, the S / P converter 31
Receives the serial data DS in synchronization with the clock CKC.

As described above, during normal data reception, C
The PU 34 detects a change in the delay time of the serial data DS and changes the clock to a more appropriate data reading clock in accordance with the detected change in the delay time. Even if the time changes, the serial data DS can always be read stably and reliably.

The present invention is not limited to the above embodiment of the present invention. For example, in the embodiment of the present invention,
Although an example in which the present invention is applied to a measuring device such as a waveform display device is shown, the present invention is applicable to industrial equipment, office equipment, and the like. Also, in the embodiment of the present invention, an example is shown in which the amplifier unit 2 and the main body 3 are applied to a measuring device that is integrated, but the present invention is not limited to this and is independent of each other. It can also be applied to certain measuring devices.

Further, in the embodiment of the present invention, an example in which the present invention is applied to data transmission of serial data is shown. However, the present invention is not limited to this, and is applicable to data transmission of parallel data. You may. Also, the predetermined pattern is not limited to the example shown in the embodiment of the present invention, and can be appropriately changed. For example, in the embodiment of the present invention, a pattern example of a value “0”, a value “1”, and a value “0” has been described as the predetermined pattern in the present invention. However, the present invention is not limited to this. A pattern of “1”, value “0”, and value “1” may be used. In this case, one of a plurality of clocks is newly added based on a plurality of read data of the value “0”. It can be determined as a proper data reading clock. Also, the configuration for generating pattern data and data change information can be changed as appropriate. Further, in the embodiment of the present invention, the change in the delay time is detected based on the data change information generated by the data change information generating section 39. The pattern data shown in FIG. 5 may be constantly generated in synchronization with the CKD, and a change in the delay time may be detected based on the generated pattern data. Further, in the embodiment of the present invention, the data reading clock is determined first by transmitting the test data DTE first. However, the present invention is not limited to this, and the delay time of the transmission data is standard. The configuration may be such that any one of the predetermined clocks CKA to CKD is determined assuming the value, and the method may be changed as appropriate.

In the embodiment of the present invention, a photocoupler has been described as an example of a delay element in a data transmission path. However, the present invention is not limited to this.
It may be an internal delay time of a line driver and a line receiver.

[0044]

As described above, according to the data receiving apparatus of the first aspect, the data reading clock determination unit is configured to synchronize the plurality of read data read by the pattern data reading unit in synchronization with the plurality of clocks. By determining one of the plurality of clocks as a new data reading clock in accordance with a predetermined rule based on a predetermined rule, even if the delay time due to the delay element changes due to a change in ambient temperature or the like, the transmission data Can be received quickly and reliably. In addition, when data is transmitted and received between a data transmitting device and a data receiving device that are insulated from each other, the data can be transmitted and received at high speed using serial data. As a result, the size and cost of the device can be reduced.

According to the data receiving apparatus of the present invention, the data reading clock determining unit determines the data reading clock based on the exclusive OR between the plurality of read data read by the pattern data reading unit. By determining the clock, for example, when the data reading clock determination unit is configured by an integrated circuit such as a CPU, the number of data to be input to the integrated circuit can be reduced, and the input terminals of the integrated circuit can be effectively used. can do.

Further, according to the data receiving apparatus of the third aspect, the data of the predetermined pattern is configured to include the 3-bit data in which the levels of adjacent bits are different from each other. The most appropriate read data can be determined in a short time.

Further, according to the data transmission system of the fourth aspect, it is possible to provide a data transmission system capable of performing data transmission at high speed and reliably.

[Brief description of the drawings]

FIG. 1 is a block diagram of a waveform display device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a data change information generation unit in the waveform display device according to the embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the waveform display device according to the embodiment of the present invention, wherein FIG.
Is a signal waveform diagram of a sampling clock, (b) is a signal waveform diagram of a reference signal, (c) is a signal waveform diagram of a system clock, (d) is a signal waveform diagram of a data transmission clock,
(E) to (h) are data reading clocks CKA, respectively.
To (CKD), and (i) is a signal waveform diagram of serial data.

4A and 4B are timing charts for explaining the operation of the waveform display device according to the embodiment of the present invention when transmitting test data, where FIG. 4A is a signal waveform diagram of a test data transmission signal, and FIGS. (E) is a signal waveform diagram of the data reading clocks CKA to CKD, and (f) to (m) are signal waveform diagrams of test data at the time of delay patterns 1 to 8.

FIG. 5 shows an RO of the waveform display device according to the embodiment of the present invention.
FIG. 7 is an explanatory diagram showing the contents of a data reading clock determination table stored in M.

FIG. 6 shows an RO of the waveform display device according to the embodiment of the present invention.
FIG. 9 is an explanatory diagram showing the contents of a clock change table stored in M.

7A and 7B are timing charts for explaining the operation of the conventional waveform display device, wherein FIG. 7A is a signal waveform diagram of a sampling clock, FIG. 7B is a signal waveform diagram of a system clock, and FIG. Credit clock signal waveform diagram,
(D) is a signal waveform diagram of transmission data, (e) is a signal waveform diagram of a data reading clock, and (f) to (i) are signal waveform diagrams of transmission data according to delay times.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Waveform display apparatus 2 Amplifier unit 3 Main part 31 S / P conversion part 34 CPU 35 Clock generation part 39 Data change information generation part

Claims (4)

[Claims] 1. A data receiving apparatus configured to be able to read transmission data transmitted from a data transmission apparatus in synchronization with a data reading clock having a cycle equal to a transmission cycle of a unit bit in the transmission data. A clock generation unit that generates a plurality of clocks having a cycle equal to the cycle and different phases from each other, and using the transmission data as one of the plurality of clocks determined in advance according to a predetermined condition as the data reading clock. A data reading unit to be read; a pattern data reading unit that reads data of the predetermined pattern in synchronization with each of the plurality of clocks when data of the predetermined pattern is included in the transmission data; and the plurality of clocks. A plurality of read data read by the pattern data reading unit in synchronization with Based, the data receiving apparatus characterized by comprising a data reading clock determining unit for determining one of said plurality of clock as a new said data read clock in accordance with a predetermined rule. 2. The data reading clock determining unit determines the data reading clock based on an exclusive OR of a plurality of read data read by the pattern data reading unit. The data receiving device according to claim 1. 3. The data receiving device according to claim 1, wherein the data of the predetermined pattern includes data of three bits whose levels of adjacent bits are different from each other. 4. A data transmission system, comprising: the data receiving device according to claim 1; and the data transmitting device.