JP2012120071A - Semiconductor device and image processing device - Google Patents

Abstract

A semiconductor device capable of synchronizing the timings of a plurality of data transmission paths at a low cost.
A semiconductor device 100 for serially transmitting data from a transmission side to a reception side, wherein synchronization determination code transmission means 301 and 302 for transmitting a code for synchronization determination between data transfers, and transmission side and reception The clock signal providing means 103 for providing a common clock signal to the side, a plurality of transmission lines 117 for transmitting the same data in synchronization with the clock signal, and the phase of the clock signal provided to the receiving side are different from each other by predetermined amounts. A clock generation unit 110 that generates a plurality of delayed clock signals by delaying, a plurality of reception buffers 111 that capture data transmitted through a transmission line in synchronization with the delayed clock signal, and a code based on a predetermined rule Verify and receive one receive buffer from multiple receive buffers and one delayed clock signal from multiple delayed clock signals A selection means 113 and 115 for respectively selecting the.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device that transmits serial data.

  In data transfer between LSI devices such as ASIC, a method is known in which data transmitted on a plurality of serial transmission paths is synchronized using an LSYNC signal. LVDS (Low voltage differential signaling) is often used for data transfer of image data, and a technique for obtaining synchronization using an LSYNC signal has been proposed (for example, see Patent Document 1).

  Patent Document 1 discloses an image transfer apparatus that performs timing synchronization by using an LSYNC signal that flows on a serial transmission path for the purpose of synchronizing I / F between devices.

  However, since the image transfer apparatus disclosed in Patent Document 1 uses a plurality of relatively expensive LVDS I / Fs, there is a problem that the cost for mounting the ASIC increases. Further, since a procedure such as training is required for synchronizing the signal level by the LVDS I / F, this also increases the cost.

  In view of the above problems, an object of the present invention is to provide a semiconductor device capable of synchronizing the timings of a plurality of data transmission paths at low cost.

  In view of the above problems, the present invention is a semiconductor device in which a transmitting side and a receiving side are serially transmitted data from a transmitting side to a receiving side in synchronization with a clock signal, and a synchronization determination code is transmitted between data transfers. Synchronization determination code transmission means, a clock signal provision means for providing a common clock signal to the transmission side and the reception side, a plurality of transmission paths for transmitting the same data in synchronization with the clock signal, and a reception side Clock generation means for generating a plurality of delayed clock signals by delaying the phases of the clock signals by different predetermined amounts, and capturing data transmitted through the plurality of transmission paths in synchronization with the plurality of delayed clock signals A plurality of reception buffers, and the code is verified based on a predetermined rule, and one reception buffer is selected from the plurality of reception buffers. Having a selecting means for selecting each one of the delayed clock signal from the delayed clock signal.

  A semiconductor device capable of synchronizing the timings of a plurality of data transmission paths at low cost can be provided.

It is an example of the hardware block diagram of an image processing apparatus. It is an example of a block diagram of a data transmission apparatus. It is an example of the timing chart figure which shows operation | movement of a data transmission apparatus. It is an example of the figure explaining the difference of what a line buffer can capture normally, and what is not so. It is a figure which shows an example of the synchronizing signal at the time of transfer of image data. It is an example of the figure which expanded the line synchronous signal, the line gate signal, and the image data signal paying attention to one line transfer. It is an example of the timing chart figure of the signal which abbreviate | omitted the line gate signal. It is an example of the figure explaining the invalid area | region of the image data containing the synchronous determination data. It is a figure which shows the structural example which transmits increment data to an invalid area | region in the image data transmission side device. It is an example of the flowchart figure which shows the procedure in which each comparator determines whether an increment pattern is normal. It is an example of the figure which shows the structural example which transmits increment data to an invalid area | region in the image data transmission side device. It is an example of the figure which shows the structural example which embeds a line synchronizing signal in an invalid area | region in the image data transmission side device. FIG. 6 is an example of a flowchart illustrating a procedure for determining whether or not a line buffer has successfully captured an image data signal.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
FIG. 1 shows an example of a hardware configuration diagram of the image processing apparatus 200. The data transmission apparatus according to the present embodiment transmits image data between the ASIC 216 and the printing unit 228 or between the imaging unit 227 and the ASIC 216. When the ASIC 216 and the printing unit 228 are focused, the ASIC 216 is the transmitting side and the printing unit 228 is the receiving side, and when the imaging unit 227 and the ASIC 216 are focused, the imaging unit 227 is the transmitting side and the ASIC 216 is the receiving side.

  Since the configuration of the image processing apparatus 200 is known, it will be briefly described. The image processing apparatus 200 includes a controller 230, an operation panel 225, a facsimile control unit (FCU) 226, an imaging unit 227, and a printing unit 228.

  The controller 230 includes a CPU 214, an ASIC 216, an NB (North Bridge) 215, an SB (South Bridge) 217, a MEM-P (System Memory) 211, a MEM-C (Local Memory) 212, and an HDD (Hard Disk Drive). ) 213, a memory card slot 223, a NIC (network interface controller) 218, a USB device 219, an IEEE 1394 device 221, and a Centronics device 222.

  The CPU 214 is an IC for executing various types of information processing, and executes applications, platforms, and the like in parallel on a process basis by an OS such as UNIX (registered trademark). The ASIC 216 is an image processing IC. The ASIC 216 renders the print data received from the terminal and transmits the print data to the printing unit 228 by performing an appropriate dither process for each object such as a character, a figure, and a background. The ASIC 216 separates the image area of the image data captured by the imaging unit 227 into a photograph, a character, and the like, and performs edge enhancement of the character, gradation complementation of the photograph, and the like.

  The NB 215 is a bridge for connecting the CPU 214 and the ASIC 216. The SB 217 is a bridge for connecting the NB 215 and peripheral devices. The ASIC 216 and the NB 215 are connected via an AGP (Accelerated Graphics Port).

  The MEM-P 211 is a memory connected to the NB 215. The MEM-C 212 is a memory connected to the ASIC 216. The HDD 213 is a storage connected to the ASIC 216 and is used to perform image data accumulation, document data accumulation, program accumulation, font data accumulation, form data accumulation, and the like.

  The memory card slot 223 is connected to the SB 217 and used for setting (inserting) the memory card 224. The NIC 218 is a controller for performing data communication using a MAC address or the like via the network 500 or the like. The USB device 219 is a device for providing a serial port compliant with the USB standard. The IEEE 1394 device 221 is a device for providing a serial port compliant with the IEEE 1394 standard. The Centronics device 222 is a device for providing a parallel port conforming to the Centronics specification. The NIC 1218, the USB device 219, the IEEE 1394 device 221, the Centronics device 222, and the PCI (Peripheral Component Interconect) bus are connected to the NB 215 and the SB 217.

  The operation panel 225 is hardware (operation unit) for the user to input to the device 100 and hardware (display unit) for the image processing apparatus 200 to provide visible information to the operator. The operation panel 225 is connected to the ASIC 216. The FCU 226, the imaging unit 227, and the printing unit 228 are connected to the ASIC 216 via the PCI bus, and the data transmission apparatus of this embodiment is assumed to be applied instead of the PCI bus, for example.

  FIG. 2 shows an example of a configuration diagram of the data transmission apparatus 100. The data transmission apparatus 100 includes an image data transmission side device 101 and an image data reception side device 102. The image data transmission side device 101 includes an image data output FF (flip-flop) 107, an image data transmission output buffer 108, a PLL 105, and a clock tree 121.

  The image data transmitting device 101 and the image data receiving device 102 are LSI devices such as FPGAs, MPUs, DSPs, etc. in addition to the ASIC 216 described above, and may be ICs that transmit or receive data. The image data transmission side device 101 is an image data transmission source device, and the image data reception side device 102 is an image data reception destination device.

  The image data receiving side device 102 includes an image data receiving input buffer 109, a plurality of line buffers 111, a plurality of comparators 112 connected to each line buffer 111, a selector 114, a PLL 104, a delay buffer 110, a clock tree 122, And a selector 115. Note that the OSC 103 is connected to the PLL 104.

  The output side of the PLL 105 of the image data transmission side device 101 is connected to the clock tree 121, and the clock tree 121 is connected to a plurality of image data output FFs 107, respectively. Each image data output FF 107 is connected to each image data transmission output buffer 108.

  The image data reception input buffer 109 is connected to the image data transmission output buffer 108 for each data transmission path 117, and a plurality of line buffers 111 are provided for each data transmission path 117. A data line is connected between the pair of line buffers 111 and the comparator 112 on the input side of the selector 113, and a received image data output line 114 is connected on the output side. A selector signal line is connected from each comparator 112 to the two selectors 113 and 115.

  The PLL 104 is connected to the same number of delay buffers 110 as the data transmission lines 117, and each delay buffer 110 is connected to the corresponding clock tree 122 and to the input side of the selector 115. Each clock tree 122 is connected to the line buffer 111. A clock tree 123 and a distribution signal line 116 are connected to the output side of the selector 115.

  The image data output FF 107 outputs the image data to the image data transmission output buffer 108 in synchronization with the clock from the PLL 105. The image data transmission output buffer 108 is a buffer for temporarily storing image data.

  The image data receiving input buffer 109 is a buffer for temporarily storing image data. The line buffer 111 captures the received image data for each data transmission path 117. The image data captured by the line buffer 111 may be less than or larger than one line. The comparator 112 extracts a specific code (hereinafter referred to as a synchronization determination code) included in the image data received by the line buffer 111, and selects the line buffer 111 that normally receives the image data.

  The selector 113 selects one image data from the outputs of the plurality of line buffers 111 using the selection result of the comparator 112. The delay buffer 110 shifts (delays) the clock phase of the clock signal supplied from the PLL 104. The selector 115 selects one clock signal from the clock signals output from each delay buffer 110 using the selection result of the comparator 112.

  The image data transmission side device 101 and the image data reception side device 102 of this embodiment perform synchronous communication with a clock oscillated by the OSC 103. The clock transmitted from the OSC 103 once passes through the image data receiving side device 102 and is input to the image data transmitting side device 101 via the clock distribution signal line 106.

  The clock transmitted by the OSC 103 is common to the image data transmission side device 101 and the image data reception side device 102, but it can be considered that a phase difference has occurred between the two devices due to the wiring length and path relationship. Therefore, in the sense of a certain phase difference, the distribution route of the clock transmitted by the OSC 103 may have a configuration other than that illustrated.

  The clock input to the image data transmission side device 101 via the clock distribution signal line 106 is distributed to each image data output FF 107 via the PLL 105. Since a clock is commonly supplied from the clock tree 121 to each image data output FF 107, each image data output FF 107 serves as a synchronization circuit of the image data transmission side device 101. The image data output FF 107 is a final stage FF (flip-flop) that outputs image data from the image data transmission side device 101, and outputs the image data in synchronization with the distributed clock.

  The image data output from the image data output FF 107 is input from the image data transmission output buffer 108 to the image data receiving side device 102 via each data transmission path 117.

  The image data receiving side device 102 temporarily stores the image data in the image data receiving input buffer 109, and then captures it in the line buffer 111. The line buffer 111 is configured as an FF, and since the clock is supplied from the PLL 104 to each line buffer 111, each line buffer 111 receives the duplicated image data in synchronization with the clock.

  In the present embodiment, the phase of the clock supplied to each line buffer 111 is explicitly shifted by the delay buffer 110. That is, each delay buffer 110 is prepared in the same number as the line buffer 111 so as to generate a plurality of clocks having different phases. For this reason, the image data captured by each line buffer 111 may be the same or not. Of the clocks supplied by the delay buffer 110, the line buffer 111 to which a clock having the same phase as that of the image data transmitting device 101 is supplied is said to be “synchronized” with the image data transmitting device 101.

  The number of buffer stages (capacity) of the line buffer 111 establishes an I / F between the number of clock cycles necessary for determining the synchronized line buffer 111 and a subsequent block that processes the image data of the synchronized line buffer 111. The number of cycles until is the minimum number of buffer stages. For example, a total of 5 clocks are required for the number of clocks until the comparator 112 verifies the synchronization determination code of the line buffer 111 and the number of clocks for the selectors 113 and 115 to select the image data received at that clock number. Further, when three clocks are required until the clock output from the selector 115 is switched to the synchronous clock of the subsequent block (not shown), the number of buffer stages of the line buffer 111 is 5 + 3 = 8 stages, respectively. If no clock consumption is required for switching the synchronous clock of the subsequent block, the number of buffer stages of the line buffer 111 is five. By designing the number of buffer stages in this way, the number of buffer stages of the line buffer 111 can be minimized.

  One stage of image data is taken into the line buffer 111 by one clock, but considering the loss of image data at the timing (phase) of each clock, which will be described later with reference to FIG. There are preferably a number of line buffers 111. Therefore, the number of line buffers 111 is the same as the number of buffer stages of the line buffer 111 at the maximum.

  The image data receiving device 102 processes the received image data using the synchronized image data output from the selector 114 and the synchronization clock output from the selector 115 (for example, outputs to the subsequent stage).

FIG. 3 is an example of a timing chart illustrating the operation of the data transmission apparatus 100. The meaning of each signal is as follows.
Send Clock: Clock signal in the device that sends image data
Send Data: Image data output signal
Receive Clock: Clock signal in the image data receiving device
Receive Data: Image data input signal
ClockA: Clock signal A whose phase is shifted by a fixed amount in the delay buffer in the image data receiving device
ClockB: Clock signal B whose phase is shifted by a certain amount in the delay buffer in the device receiving image data
ClockC: Clock signal C whose phase is shifted by a certain amount in the delay buffer in the image data receiving device
ClockX: Clock signal X whose phase is shifted by a fixed amount in the delay buffer in the device receiving image data
Receive DataA: Image data obtained by receiving Receive Data with ClockA
Receive DataB: Image data obtained by receiving Receive Data with ClockB
Receive DataC: Image data obtained by receiving Receive Data with ClockC
Receive DataX: Image data obtained by receiving Receive Data with ClockX
Send Data is image data transmitted by the image data transmission side device 101. Send Clock is a clock output from the clock tree 121, for example.

  Send Data is output from the image data output FF 107 toward the image data receiving device 102 and received by the line buffer 111. At this time, the operation clock output from the PLL 104 of the image data receiving device 102 is Receive Clock, and the image data subjected to delay due to wiring delay or inter-signal skew is Receive Data.

  In the case of an ideal data transfer with no delay due to wiring delay or inter-signal skew, the change point of the image data coincides with the rising edge of the clock without time lag. However, as shown in FIG. 3, the rising edge of the clock overlaps or overlaps with the change point of the image data of the plurality of Receive Data, and the line buffer 111 captures the Receive Data using the rising edge of the Receive Clock as a trigger. And may not be able to receive normally.

  Therefore, each delay buffer 110 generates clocks ClockA, ClockB, ClockC,... ClockX in which the phase of the Receive Clock is shifted by a certain time. Each clock ClockA, ClockB, ClockC,... ClockX is supplied to the line buffer 111, and the line buffer 111 captures ReceiveData triggered by the rising edge of the clock ClockA, ClockB, ClockC,. Receive Data A to X are generated respectively.

  For this reason, among the image data Receive Data A to X received by the line buffer 111, there are those that are normally captured by the line buffer 111 and those that are not, depending on the timing relationship between Clock A to X and Receive Data.

  FIG. 4 is an example of a diagram illustrating the difference between what the line buffer 111 can normally capture and what is not. FIG. 4 shows a part of the Receive Data, and each timing indicated by a plurality of “◯” and “×” indicates the timing of capturing the image data of each clock. The timing at which the line buffer 111 can be captured normally by the clock is indicated by “◯”, and the timing at which the line buffer 111 cannot be captured normally is indicated by “x”. As shown in FIG. 4, whether or not data can be captured normally is determined by the relative relationship between Receive Data and the rising edge (image data capturing timing) of each clock.

  Assuming that multiple Receive Data A to X are not delayed until one cycle of one clock at the maximum, the delay buffer 110 can be connected to any one of Clock A to X if Clock A to X are distributed within one cycle. It is considered that one of the buffers 111 can always receive Receive Data. Therefore, it can be seen that the amount by which the delay buffer 110 shifts the phase needs to be a time obtained by setting the period of one clock cycle for capturing image data to 1 / X.

  For example, when X (the number of buffer stages of the line buffer) = 4 and the period of one clock cycle is 20 ns, the time that the delay buffer 110 should shift one of ClockA to X is “20 ÷ 4≈5 ns”. Therefore, the delay buffer 110 generates four clocks having a phase difference of 0 ns (source oscillation clock), 5 ns, 10 ns, and 15 ns. The four line buffers 111 operate to receive with each clock.

  The value of X can be made smaller than the number of buffer stages in the line buffer 111 by determining the frequency of the source clock, the timing characteristics at the time of reception (timing width that can be normally captured), and the like. If X is appropriately determined, an appropriate resolution can be obtained for a plurality of Clocks A to X, and any one of the plurality of Clocks A to X can surely capture image data.

  As described above, the line buffer 111 includes one that correctly captures image data and one that captures abnormal image data. Therefore, it is the comparator 112 that determines which of the line buffers 111 has received correctly. A method for determining the image data received normally by the comparator 112 will be described later.

  When the comparator 112 identifies the image data that has been normally received, the comparator 112 outputs a coincidence signal to the selectors 113 and 115, so that the selector 113 selects the image data in the line buffer 111 that has been normally received and receives the received image. The selector 115 selects the clock supplied to the line buffer 111 that has been normally received and outputs it to the distribution signal line 116. In this way, the image data receiving device 102 can receive the synchronized image data.

[Extraction method by comparator]
When each line buffer 111 captures image data at different clocks, a procedure will be described in which the comparator 112 determines which clock the captured image data is normally received.

  FIG. 5 shows an example of a synchronization signal or the like when transferring image data. 6 and 7 are enlarged views of a part of FIG.

  The image data is obtained by reading one original with the imaging unit 227 or sent to the printing unit 228 in the image processing apparatus 200. That is, this image data is rasterized bitmap data.

  When one page of image data is transferred, a signal indicating the effective area of the image data includes, for example, a frame gate signal. The image data transferred while this signal is valid (“1” for the high active signal, “0” for the low active signal) is valid as image data for one page. . The ASIC 216 connected to the imaging unit 227 and the printing unit 228 connected to the ASIC 216 monitor the frame gate signal and detect that there is image data to be received.

  Similarly, there is a line synchronization signal as a synchronization timing signal indicating the start of line transfer of image data. The ASIC 216 connected to the imaging unit 227 and the printing unit 228 connected to the ASIC 216 detect the start of data transfer for one line from the effective pulse of the line synchronization signal.

  The line gate signal is a signal indicating an effective image area in the transfer of one line of image data. The image data transferred while this signal indicates validity is valid data as image data for one line. In the figure, High active is assumed.

  Accordingly, while the frame gate signal is valid ("1"), the line synchronization signal is valid for the number of lines of the image data, and the line gate signal after each line synchronization signal indicates valid data for each line. .

  The receiving side of the image data can receive the image data by detecting these control signals and taking in the image data.

  FIG. 6 is an example of an enlarged view of the line synchronization signal, the line gate signal, and the image data signal, focusing on one line transfer. Since the image data signal shown in FIG. 6 is invalid data except in the area where the line gate signal is valid, the transmission source transfers invalid data outside the valid area of the image data.

  The invalid data of the image data may be fixed to “0” uniformly, fixed to “1”, or may be completely random data (indefinite value). This invalid area in which invalid data exists is generated due to mechanical control restrictions of the scanner and plotter device, and always exists in the current control method of the scanner device and plotter device. In the present embodiment, the synchronization determination code used for the selection of the line buffer 111 by the comparator 112 is transferred in this invalid area.

  Note that either the line synchronization signal or the line gate signal in FIG. 6 can be omitted. FIG. 7A is an example of a timing chart of a signal in which the line gate signal is omitted, and FIG. 7B is an example of a timing chart of a signal in which the line synchronization signal is omitted.

  In the example of FIG. 7A in which there is no line gate signal, the number of clocks from which the effective image data starts from the line synchronization signal is fixed in advance so that the image data receiving device 102 can detect the line synchronization signal from the line synchronization signal. Image data can be received by counting a fixed number of clocks. In other words, a fixed-length area from the line synchronization signal is an invalid area.

  In the example of FIG. 7B in which there is no line synchronization signal, the image data receiving device 102 receives image data while the line gate signal indicates valid. In other words, the area where the line gate signal does not show validity is the invalid area.

  FIG. 8 is an example of a diagram for explaining an invalid area of image data including a synchronization determination code. The hatched image data signal in FIG. 8 is invalid as image data, but is used as an area for transferring a synchronization determination code for synchronization determination in this embodiment. Since the line synchronization signal (including frame gate signal and line gate signal) is transmitted from the image data transmission side device 101 to the image data reception side device 102 together with the image data signal and the clock signal, the comparator 112 detects the line synchronization signal. Then, it is possible to determine whether or not the image data has been correctly captured in the line buffer 111 by using the synchronization determination code in the invalid area from when the image data is started.

  FIG. 9A shows an example of a configuration in which the synchronization determination code is embedded in the invalid area in the image data transmission side device 101, and FIG. 9B shows an example of a diagram for explaining the image data signal output by the selector 301. In FIG. 9A, the increment pattern is a synchronization determination code. A transmission image and a pattern generator 302 are connected to the input side of the selector 301. The output side of the selector 301 is branched and connected to the image data output FF 107. A frame gate signal and a line gate signal are input to the pattern generator 302, and the line gate signal is supplied to the selector 301 via a selector line.

  The pattern generator 302 is activated when the frame gate signal is asserted (when it becomes high active in the figure), and generates an increment pattern. In the figure, an increment pattern is generated that is incremented by one for each clock, but may be incremented by two if it is a regular pattern. Further, when the frame gate signal is negated, the pattern generator 302 returns the output value to the initial value (1 in the figure).

The pattern generator 302 stops incrementing when the line gate signal is asserted. Therefore, the pattern generator 302
・ Increment the count pattern between the assertion of the frame gate signal and the assertion of the line gate signal.
・ A constant value is output while the line gate signal is asserted.
・ Increase the count pattern from the time the line gate signal is negated until the frame gate signal is negated,
-When the frame gate signal is negated, the initial value is output.

  The selector 301 outputs a transmission image when the line gate signal indicates validity, and outputs an increment pattern when the line gate signal does not indicate validity.

  As shown in FIG. 9B, when the frame gate signal is asserted, the increment pattern increases by one for each clock. When the line gate signal is asserted, the increment pattern becomes a constant value (8 in the figure), and when the line gate signal is negated, the increment pattern increases by one for each clock. Thereby, in the figure, the increment pattern is counted up from 1 to 13.

  Since the selector 301 outputs the transmission image while the line gate signal is asserted, the image data signal output from the selector is a signal in which the increment pattern 8 is replaced with the transmission image.

  Therefore, the line buffer 111 receives numerical values 1 to 8, a transmission image, and numerical values 9 to 13. Since the number of clocks from the start of the frame gate signal to the start of the line gate signal and the number of clocks from the end of the line gate signal to the end of the frame gate signal are fixed, the line buffer 111 correctly outputs the image data signal. If it can be received, it should be able to receive numerical values 1-8 and numerical values 9-13. The same applies to the case where the increment pattern is embedded from the line synchronization signal to the start of the line gate signal. Therefore, the comparator 112 can specify the line buffer 111 that can normally capture the image data signal depending on whether or not the numerical values 1 to 8 and the numerical values 9 to 13 have been received. Since the number of bits differs depending on the numerical value, the increment pattern may be stored in units of the number of bits that can store the maximum number of bits.

  FIG. 10 is an example of a flowchart illustrating a procedure in which each comparator 112 determines whether or not the increment pattern is normal. This procedure is performed only at the beginning of page transfer, and thereafter, the image data signal of the line buffer 111 determined to be coincident by the comparator 112 is transferred to the received image data output line 114 until the transfer of the entire page is completed. Just output. Further, this procedure may be executed for each line so that the selectors 113 and 115 select the normal line buffer 111 more reliably.

  When the frame gate signal is asserted (S10), the comparator 112 starts detecting the increment pattern and determines whether or not it matches the predetermined increment pattern (S20). In the figure, it is determined whether or not the numerical values 1 to 8 are detected in order (by a predetermined number of clocks).

  If even one of the numerical values 1 to 8 is not detected from the line buffer 111 (No in S20), the comparator 112 outputs a mismatch signal to the selector (S60).

  When all the numerical values 1 to 8 are detected from the line buffer 111 (Yes in S20), the comparator 112 waits until the line gate signal is negated (S30).

  When the line gate signal is negated, the comparator 112 restarts the detection of the increment pattern and determines whether or not it matches the predetermined increment pattern (S40). In the figure, it is determined whether or not numerical values of 9 to 13 are detected in order (by a predetermined number of clocks).

  If even one of the numbers 9 to 13 is not detected from the line buffer 111 (No in S40), the comparator 112 outputs a mismatch signal to the selector (S60).

  When all the numerical values of 9 to 13 are detected from the line buffer 111 (Yes in S40), the comparator 112 outputs a coincidence signal to the selector (S50).

  By doing so, the comparator 112 specifies the line buffer 111 that can normally capture the image data signal among the plurality of line buffers 111 and the clock that can normally capture the image data signal among the plurality of clocks ClockA to X. Can do. Note that the determinations in steps S30 and S40 may be omitted, or the determinations in steps 10 and S20 may be omitted.

  Since there are a plurality of line buffers 111, two or more line buffers 111 may be able to capture image data signals normally. In this case, the selectors 113 and 115 can select the clock and the line buffer 111 connected to the comparator 112 that outputs the coincidence signal first, or the comparator 112 that outputs the coincidence signal last. It is also possible to select a line buffer 111 and a clock connected to. Further, in order to select a more stable line buffer 111 when the phase of the clock signal is disturbed, the phase difference of the supplied clock signal is the center line buffer among the two or more line buffers 111 that have successfully captured the image data. It is preferable to select 111 (“○” line buffer in the middle of FIG. 4).

As described above, the increment pattern embedded in the invalid area may be any value as long as it changes regularly or is a known constant value.
FIG. 11A shows another configuration example in which the increment data is transmitted to the invalid area in the image data transmission side device 101. In FIG. 11A, the description of the same part as in FIG. 9A is omitted. In FIG. 11A, the line gate signal is not supplied to the pattern generator 302. In such a configuration, the pattern generator 302 does not output a constant value while the line gate signal is asserted, but continues to count up in synchronization with the clock while the frame gate signal is asserted.

  FIG. 11B is an example for explaining an image data signal output from the selector 301. When the frame gate signal is asserted, the increment pattern increases by one for each clock. Therefore, in the figure, the count is incremented from 1 to 60 as an example. Since the selector 301 transmits the transmission image instead of the increment pattern while the line gate signal is asserted, the image data signal is a numerical value 1 to 8, a transmission image, and a numerical value 56 to 60.

  Therefore, the comparator 112 can specify the line buffer 111 that can normally capture the image data signal depending on whether or not the numerical values 1 to 8 and the numerical values 56 to 60 have been received. The operation procedure of the comparator 112 in this case only changes the numerical value detected in step S40 of FIG. As described above, the image data receiving device 102 can determine the line buffer 111 from which the image data is to be extracted if the synchronization determination code embedded in the invalid area by the image data transmitting device 101 is known. For example, it may be a decrement pattern instead of an increment pattern, or a constant value (for example, repetition of the same numerical value of 0 to 9). In the case of a decrement pattern, the comparator 112 determines the line buffer 111 depending on whether or not a numerical value that decreases by one can be detected in order, for example. When a constant value is embedded, the comparator 112 determines the line buffer 111 depending on whether or not the same numerical value can be detected a predetermined number of times.

  Even if the image data transmission side device 101 does not have a configuration for embedding numerical values in the invalid area, such as the pattern generator 302, if the invalid image is a transmission image in which the invalid area is always "0" or always "1". The comparator 112 can select the line buffer 111 almost in the same manner.

  FIG. 12A shows a configuration example in which the line synchronization signal is embedded in the invalid area in the image data transmission side device 101. A transmission image and a line synchronization signal are input to the input side of the selector 301, and the line synchronization signal is a selector line of the selector 301. The selector 301 outputs a transmission image when the line synchronization signal is not valid, and outputs the line synchronization signal only when the line synchronization signal is valid. With such a configuration, the line synchronization signal can be included in the image data signal.

  FIG. 12B is a diagram illustrating an example of the image data signal in which the line synchronization signal is embedded in the invalid area. As described above, the number of clocks from the line synchronization signal to the effective area of the transmission image is fixed. In FIG. 12B, the value of the invalid area is “0”. When such a transmission image and a line synchronization signal are input to the selector 301, an image data signal in which “1” is embedded in the invalid area is output in synchronization with the line synchronization signal. Each of the line buffer 111 receives an image data signal, and there are a case where “0” is taken in by a fixed number of clocks and a case where it is not. Therefore, the comparator 112 determines whether the line buffer 111 is normal depending on whether one “1” is detected and whether the number of “0” is a fixed-length number based on the line synchronization signal. It is possible to determine whether or not an image data signal is captured. In the case of a transmission image in which “1” instead of “0” is embedded in the invalid area, the image data transmission side device 101 may embed “0” in the transmission image in synchronization with the line synchronization signal.

  FIG. 13 is an example of a flowchart illustrating a procedure for determining whether or not the line buffer 111 has successfully captured an image data signal.

The comparator 112 starts the comparison when the line synchronization signal is valid (S110).
When the line synchronization signal is detected, the comparator 112 determines whether “1” is detected (S120).

  If “1” is not detected from the line buffer 111 (No in S120), the comparator 112 outputs a mismatch signal to the selector (S150).

  When “1” is detected from the line buffer 111 (Yes in S120), the comparator 112 determines whether or not a fixed number of “0” is detected (S130).

  When the fixed number of “0” is not detected from the line buffer 111 (No in S130), the comparator 112 outputs a mismatch signal to the selectors 113 and 115 (S150).

  When a fixed number of “0” is detected from the line buffer 111 (Yes in S130), the comparator 112 outputs a coincidence signal to the selectors 113 and 115 (S140).

  Through the processing described above, even if the image data transmission side device 101 does not have the pattern generator 302, the image data reception side device 102 selects the line buffer 111 that normally captures the image data signal using the invalid area. it can.

  Therefore, as described above, the data transmission apparatus 100 according to the present embodiment has a plurality of data captured by clocks having different phases even if the I / F state between devices varies due to temperature conditions, aging deterioration, and other external factors. Since the line buffer 111 that normally captures the image data signal is selected from the line buffer 111, synchronization can be established following changes due to external factors. Developers can provide ASICs that are relatively small, inexpensive, and easy to design timing, without the need for mounting area and analog adjustments on the ASIC, or by placing a dedicated IP for LVDS.

DESCRIPTION OF SYMBOLS 100 Data transmission apparatus 101 Image data transmission side device 102 Image data reception side device 103 OSC (clock oscillation source)
104, 105 PLL
106 Clock distribution signal line 107 Image data output FF (flip-flop)
108 Image data transmission output buffer 109 Image data reception input buffer 110 Delay buffer 111 Line buffer 112 Comparator 113, 115 Selector 114 Received image data output line 116 Distribution signal line

JP 2006-080877 A

Claims (10)

A semiconductor device that serially transmits data from the transmission side to the reception side in synchronization with the clock signal between the transmission side and the reception side,
Synchronization determination code transmission means for transmitting a code for synchronization determination between data transfers;
A clock signal providing means for providing a common clock signal to the transmitting side and the receiving side;
A plurality of transmission lines that transmit the same data in synchronization with the clock signal;
Clock generating means for generating a plurality of delayed clock signals by delaying the phases of the clock signals provided to the receiving side by different predetermined amounts;
A plurality of reception buffers that respectively capture data transmitted through the plurality of transmission paths in synchronization with the plurality of delayed clock signals;
Selection means for verifying the code based on a predetermined rule and selecting one reception buffer from the plurality of reception buffers and one delay clock signal from the plurality of delay clock signals;
A semiconductor device having: When the number of the clock generation means is X and the period of one clock cycle of the clock signal is T, each clock generation means delays the phase of the clock signal by a time corresponding to the phase of T / X.
The semiconductor device according to claim 1. The number of buffer stages of the plurality of line buffers is the number of clocks from when the reception buffer starts to receive data until the selection unit selects one reception buffer from the plurality of reception buffers, or the plurality of delay clocks. More than the number of clocks until one delayed clock signal is selected from the signal,
The semiconductor device according to claim 1 or 2, wherein The number of buffer stages of the plurality of line buffers is determined after the selection unit selects one reception buffer from the plurality of reception buffers or after selecting one delay clock signal from the plurality of delay clock signals. More than the number of clocks plus the number of clocks required to switch the block operating clock,
The semiconductor device according to claim 3.   5. The semiconductor device according to claim 1, wherein the code is a numerical value that regularly increases in synchronization with a clock signal.   5. The semiconductor device according to claim 1, wherein the code is a constant numerical value after the line synchronization signal is embedded. The selection means selects the reception buffer to which the delayed clock signal at the center is supplied in a timing among the plurality of reception buffers storing the code that has been verified.
The semiconductor device according to claim 1, wherein: The selecting means receives the data transfer from the time when the frame gate signal is valid until the time when the line gate signal is valid or from the time when the line gate signal is valid until the time when the frame gate signal is valid. Extracting the code from the data stored in the buffer;
The semiconductor device according to claim 1, wherein: The selection means extracts the code from the data stored in the reception buffer, with a fixed time from the time when the line synchronization signal indicates valid as the interval of data transfer,
The semiconductor device according to claim 1, wherein:   An image processing apparatus equipped with the semiconductor device according to claim 1.

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