JPH09116036A - Non-volatile storage cell transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize stable operation without deteriorating the performance characteristic of a MOSFET, by providing a field-effect transistor on the front side of a semiconductor layer and providing, on the back side of the semiconductor layer, a control section for controlling a threshold voltage of the field-effect transistor and holding the threshold value. SOLUTION: A non-volatile storage transistor 100 has a MOSFET 10 which includes a source region 13a, a drain region 13b, a channel region 15, a first gate insulating film 17 and a first gate 19 provided on a front side 11a of a semiconductor layer 11. On a back side 11b of the semiconductor layer 11, an insulator 21 made of a ferroelectric material and a second gate 23 as an auxiliary electrode are provided, thus forming a control section 20. Therefore, a storage cell capable of performing stable operation such that the FET side operating as a switching element is not affected by the ferroelectric film may be provided. Also, the structure of double-gate MOSFET may be employed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory cell transistor using a ferroelectric substance.

[0002]

2. Description of the Related Art Nonvolatile memory cell transistors (hereinafter, also referred to as memory cells) using a ferroelectric substance are well known as those disclosed in Documents 1 and 2 below.

Reference 1: Ferroelectric thin film integration technology, Science Forum, 1992.

Reference 2: IEEE TRANSACTIONS ON ULTRASONI
CS, FERROELECTRICS, AND FREQUENCYCONTROL VOL.38, NO.
6, pp.663-671, NOVEMBER 1991.

The memory cell of Document 1 is composed of a switching MOSFET (Field Effect Transistor) and a capacitor (capacitance), and the insulating film of this capacitor is entirely or partially made of a ferroelectric material. Of the three types of lines connected to each cell, a positive voltage is applied to the word line to turn on the MOSFET, and the ferroelectric is polarized by the voltage difference between the remaining bit line and the drive line, and then the MOSFET. Turn off. At this time, even if the MOSFET is turned off, polarization remains in the ferroelectric substance (residual polarization), and this is used to store information.

The memory cell of Reference 2 is a MOSFE.
It is composed of T alone and has a structure in which a ferroelectric film is used as the gate insulating film of the MOSFET. That is, Si
It consists of a source / drain region provided on the substrate, a ferroelectric film provided on the surface of the substrate so as to straddle these regions, and a gate electrode provided on the ferroelectric film.
In this memory cell, the magnitude of the threshold voltage changes depending on the polarization polarity of the ferroelectric film. Therefore, by utilizing this, the on / off state of the MOSFET is stored in a nonvolatile manner.

[0007]

However, the above-mentioned non-volatile memory cell transistor has the following problems.

The memory cell of the above-mentioned document 1 has an advantage that writing and erasing can be performed at a high speed and a writing voltage can be lowered, as compared with a flash memory or the like. However, since both the MOSFET and the capacitor are required, the cell area becomes large. Also,
Since reading is performed by detecting the current charged in the capacitor, a detection amplifier with a complicated design is required.

Further, in the memory cell of the above-mentioned document 2, since each cell is composed of a single MOSFET, there is an advantage that the cell area can be reduced. However, since the ferroelectric film is used as the gate oxide film, the following new problem arises. Generally, a ferroelectric material (for example, Bi ₄
All of the elements contained in Ti ₃ O ₁₂ , PZT, BaMgF _4, etc. easily react with silicon (Si) which is usually used as a substrate material of MOSFET, and also cause a deep impurity level. Further, when the ferroelectric film is directly provided on the Si substrate as in the memory cell structure of Reference 2, the ferroelectric film is easily peeled off. Therefore, an SiO ₂ film or the like is provided between the substrate and the ferroelectric film. Although it is common to improve the adhesion, there is a possibility that the element in the ferroelectric material is taken into the SiO ₂ film as an ion and becomes a mobile charge. Therefore, there has been a concern that the fixed charges increase and adversely affect the operating characteristics of the MOSFET, such as fluctuations in threshold voltage and deterioration of mobility.

Therefore, a non-volatile memory cell transistor is desired which can be expected to operate stably without deteriorating the operating characteristics of the MOSFET.

[0011]

Therefore, according to the nonvolatile memory cell transistor of the present invention, the structure of the field effect transistor is provided on the front surface side of the semiconductor layer, and the field effect transistor is provided on the back surface side of the semiconductor layer. It is characterized in that a control unit for controlling the threshold voltage and holding the threshold voltage is provided.

At this time, the control unit may be composed at least of a ferroelectric film provided on the back surface of the semiconductor layer and an auxiliary electrode provided on the ferroelectric film.

For example, the following structure is preferable.

A semiconductor layer having a source region, a drain region, and a channel region which is a current path between these regions, a first gate insulating film provided on the surface of the semiconductor layer so as to extend over the both regions, and A first gate provided in a region facing the channel region on the first gate insulating film;
All or at least a part of the insulating film of a double-gate MOS transistor including an insulating film provided on the back surface of the semiconductor layer and a second gate provided on a region of the insulating film facing the first gate Is composed of a ferroelectric material.
Here, for example, as a material of the insulating film, Ba ₄ Ti ₃
Only a ferroelectric substance such as O ₁₂ , PZT, or BaMgF ₄ may be used, or a laminated film in which a SiO ₂ film or the like is further provided on the semiconductor layer side may be used. Alternatively, a film mainly made of SiO ₂ or the like may be used, and a layer made of a ferroelectric material may be put in a part of the region facing the second gate.

The memory cell having the above structure operates as follows. When a voltage is applied between the semiconductor layer and the auxiliary electrode (second gate) to polarize the ferroelectric film under the auxiliary electrode, the polarity of the auxiliary electrode causes the semiconductor layer region on the back surface side of the semiconductor layer to be uncovered. In the vicinity of the interface between the semiconductor layer and the ferroelectric film, a layer (accumulation layer) or a layer in which positive charges are accumulated in a region (charge layer forming region) almost equal to a region facing the auxiliary electrode is formed. A layer (inversion layer) in which the charges of (1) are collected is formed. At this time, the threshold voltage of the FET changes depending on whether an accumulation layer or an inversion layer is formed in this charge layer formation region.
A memory cell capable of reading the on / off state of T can be realized.

As described above, when the ferroelectric film is provided on the surface of the semiconductor layer opposite to the side where the FET acting as the switching element is provided, the nonvolatile memory cell which does not adversely affect the operation of the FET. Can be

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. Each drawing merely schematically shows the size, shape, positional relationship and the like of each constituent component to the extent that the invention can be understood, and is not limited to the illustrated examples. Further, hatching and the like showing the cross section are omitted except for a part.

FIG. 1 is a schematic diagram for explaining the basic structure 100 of the nonvolatile memory cell transistor of the present invention, and is a sectional view of one memory cell. In the figure,
The hatching showing the cross section is omitted except for a part.
Note that this is a diagram for explaining the memory cell structure, and the form of the actually manufactured memory cell will be described later.

According to the nonvolatile memory cell transistor 100 of the present invention, the structure 1 of the FET is formed on the surface side of the semiconductor layer.
0 is provided, and a control section 20 for controlling the threshold voltage of the FET and holding the threshold voltage is provided on the back surface side of the semiconductor layer 11.

Here, as a non-volatile memory cell transistor, a so-called double gate type MOSF shown below is used.
The structure of the ET will be described as an example. That is, the semiconductor layer 11 is a layer (Si layer) made of a semiconductor substrate such as Si,
If one surface is a front surface 11a and the other surface is a back surface 11b, the source region 13a, the drain region 13b, the channel region 15 which is a current path between these regions, and the both regions are straddled on the front surface 11a side. Is provided with the structure of the MOSFET 10 including the first gate insulating film 17 provided on the surface 11a and the first gate 19 provided in a region facing the channel region 15 on the first gate insulating film 17. . Then, on the back surface 11b of the semiconductor layer 11, an insulating film 21 and a second gate 23 as an auxiliary electrode are provided in a region of the insulating film 21 facing the first gate 19, and these are used as a control unit 20. Here, a case where the entire insulating film 21 is made of a ferroelectric material will be described. Further, in FIG. 1, the first gate insulating film 17 and the insulating film 21 are
The first gate 19 and the second gate 2 are provided so as to cover the front surface 11a and the back surface 11b of the semiconductor layer 11.
In accordance with the shape of 3, the portions exposed from both gates may be removed by etching to be molded. Here, a region in the semiconductor layer 11 that is substantially equal to a region facing the second gate 23 in the vicinity of an interface with the ferroelectric layer (insulating film) 21 on the back surface 11b side is a charge layer forming region. (In the figure, it is schematically shown surrounded by a dotted line.) 25. In the charge layer forming region 25, when the second gate side is operated,
This is a region where a positive charge layer (accumulation layer) or a negative charge layer (inversion layer) is formed.

Of the above memory cell basic structure 100,
The operating characteristics of a generally well-known double gate MOSFET in which the insulating film 21 is an SiO ₂ film are described in Reference 3: IEEE Trans.on ED, vol.ED-30, no.10,1983, pp.1244-.
1251. According to Document 3, on the assumption that the depletion layer on the first gate side is connected to the depletion layer on the second gate side, the charge layer formation region on the second gate side described above
It is described that the threshold voltage V _t of the MOSFET structure on the first gate side changes depending on whether an accumulation layer or an inversion layer is formed. If this change amount (difference between the threshold voltage when the accumulation layer is formed and the threshold voltage when the inversion layer is formed) is ΔV _t , ΔV _t is
It can be represented by the following equation (1).

ΔV _t = (C _b / C _0f ) 2Φ _B (1) where C _0f is the capacitance of the first gate insulating film, C _b is the capacitance of the depletion layer on the second gate side, Φ _B is a semiconductor layer (Si layer) 11
This is the difference between the Fermi level of and the midgap. If the Si layer concentration is 1 × 1015 cm ^-3 , Φ _B is 0.4 V
And the thickness of the Si layer is 40 nm, half of which is the second
If the film thickness of the first gate insulating film is 20 nm, which is a depletion layer due to the gate, then ΔV _t is about 2.4 V from equation (1). From equation (1), it can be understood that the variation ΔV _t can be adjusted by considering the thickness of the first gate insulating film and the thickness of the Si layer. Therefore, the impurity concentration profile and the thickness of the semiconductor layer should be adjusted so that the double gate MOSFET can operate, that is, the depletion layers existing on both gate sides of the semiconductor layer can be connected (overlapped). If you decide
The second gate side acts to control the threshold voltage of the MOSFET.

Therefore, if each state can be stored, a memory cell for reading the on / off state of the MOSFET can be realized.

FIG. 2 shows the basic structure 100 of the memory cell of FIG.
Of these, in order to explain the operation of the control unit 20, the state under the second gate 23 is shown as an electrical conceptual diagram. The portion below the second gate 23 can be equivalently regarded as a capacitor. Considering that the flat band voltage is OV, the charge Q on the second gate 23 is equal to the ferroelectric layer 21.
When the direction of Dfe is positive and upward with respect to the inside electric flux density Dfe, the relationship of Q = -Dfe is established by Gauss' law. In this case Si layer surface (rear surface 11b of the Si layer in this case. Hereinafter the same) of the charge Q _S of the expressed and -Q = Q _S. When the gate voltage of the second gate is Vg, the following equation (i) is established.

Vg = Efe · dfe + Ψs (...) (i) where Efe is the electric field in the ferroelectric, dfe is the film thickness of the ferroelectric, and Ψs is the potential on the surface of the Si layer. Further, the surface charge Q _S of the Si layer can be expressed by a function of f (Ψ s), and the following equation (ii) holds.

Q _S = (Ψ s) = Dfe = Pfe + ε ₀ · Efe
(Ii) where Pfe is the remanent polarization of the ferroelectric substance and ε ₀ is the dielectric constant.

Since the electric field in the ferroelectric pair is 0 when the gate voltage is zero, the electric flux density Dfe is equal to the value of the remanent polarization Pfe. Therefore, a charge equal to the remanent polarization Pfe is generated on the back surface 11b of the Si layer as the surface charge Q _S of the Si layer. Here, since the strong surface charge Q _S of the Si layer when the inversion starts is on the order of 1 [mu] C / cm ^2, the residual polarization of the ferroelectric is typically on the order of 10 [mu] C / cm ^2, the ferroelectric layer 21 The storage layer or the inversion layer can be formed in the charge layer forming region 25 only by reversing the sign of the remanent polarization. Therefore, the control unit 20
It serves to control the threshold voltage of the FET structure 10.
Once polarization occurs in the ferroelectric substance, even if the voltage supply is stopped, the state is retained unless reverse bias is applied. Therefore, the state in which the storage layer or the inversion layer is formed is stored in a nonvolatile manner. . Therefore, at this time, if the gate voltage of the first gate 19 is set within the range of the change amount ΔV _t of the threshold voltage expressed by the equation (1), the on / off state of the MOSFET 10 is stored in a nonvolatile manner. be able to. That is, a nonvolatile memory can be realized by the basic structure 100 of FIG.

As can be understood from the above description, the non-volatile memory cell transistor of the present invention has a control unit having a structure including a ferroelectric material on the surface of the semiconductor layer opposite to the side where the FET is provided. Is provided, there is no fear of adversely affecting the operation of the FET that functions as a switching element. Further, since a double gate MOSFET structure can be adopted, a memory cell having the advantages of this structure, for example, large short-channel effect resistance, ideal subthreshold characteristics, and the like can be obtained. .

Next, an example of the form of the memory cell actually manufactured will be shown. FIG. 3 shows an example of the form of an actual memory cell (referred to as a memory cell 200) including the basic structure of FIG.
It is shown in a cross-sectional view of one cell. The structure of the memory cell 200 will be briefly described. The basic structure 100 of FIG. 1 is provided on the Si substrate 30 via the insulating oxide film SiO ₂ film 31. In this example, the insulating film 2 below the second gate 23
1 is a ferroelectric layer 21a provided immediately below the second gate 23, and the ferroelectric layer 21a and the semiconductor layer Si.
An adhesion film (SiO ₂ film) provided between the back surface 11b of the layer 11 and the ferroelectric film 21a to improve the adhesion.
21b as a laminated film. Also in this case, the FET structure 10 is formed on one surface (front surface) side of the semiconductor layer (Si layer) 11.
Is configured, and the control unit 20 is configured on the other surface (back surface) side. At this time, it can be considered that two capacitors continuously exist under the second gate 23. In this case as well, similar to the case of the basic structure 100, the charge almost equal to the remanent polarization is the surface charge of the Si layer. Occurs as. For this reason,
Similarly, the storage layer or the inversion layer can be formed in the charge layer forming region 25 by only reversing the sign of the remanent polarization of the ferroelectric layer.

Next, an example of a method for actually manufacturing the memory cell of the present invention will be briefly described. FIG. 4 and FIG.
FIG. 6D is a process diagram for describing an example of the method of manufacturing the nonvolatile memory cell transistor of the present invention, which is a cross-sectional view of one memory cell. A method of manufacturing the memory cell 200 of FIG. 3 will be described here. Further, hatching indicating a cross section is omitted except for a part.

First, a groove 30a for forming a second gate is formed in the Si substrate 30 by using a photolithography technique (FIG. 4A). The depth of this groove is, for example, about 300 nm.

Next, an insulating oxide film (SiO ₂ film) 31 (having a thickness of about 100 nm) is formed on the entire surface of the Si substrate 30 including the groove 30a, and a metal film 23a (having a thickness of 1) for forming a second gate later.
00 nm) and the ferroelectric film 24 (film thickness of about 200 nm) are sequentially provided by a suitable method (FIG. 4B). For example, the SiO ₂ film 31 is provided by thermal oxidation, and the metal film 23
For a, for example, when W (tungsten) is used, it is formed by magnetron sputtering or the like. In addition, the ferroelectric film 24 (for example, Bi ₄ Ti ₃ O ₁₂ , PZT, BaM
gF ₄ etc.) is formed by magnetron sputtering or the like using each material as a target.

Then, the portion of the insulating oxide film 31 outside the groove 30a is used as an etching stopper, and the upper surface of the film remaining in the groove 30a is ferroelectric until the surface of the film 31 outside the groove becomes the same height. By etching back the body film 24 and the metal film 23a, the ferroelectric layer 21a and the second gate 23 are formed.
A structure in which is formed is obtained ((C) of FIG. 4). Therefore, the upper surface of this structure is a substantially flat surface. The etching gas used at this time is the ferroelectric film 2
When 4 is a Bi ₄ Ti ₃ O ₁₂ film, chlorine gas is used, and PZT
Alternatively, in the case of BaMgF ₄ , Ar gas or the like is used.

On the sample (on the insulating oxide film 31, the ferroelectric layer 21a, and the second gate 23) on which the above processing is completed,
A SiO ₂ film 21b (film thickness of about 10 nm) is used as an adhesion film by a suitable method, for example, normal pressure CV using SiH ₄ and O _2.
Method D, or TEOS; deposited by low pressure CVD using (T etra E th o xy S ilane tetraethoxysilane) and O ₃ (in FIG. 4 (D)). Ferroelectric layer 21a and S
The laminated film with the iO ₂ film 21b is used as the insulating film 21.

Next, another semiconductor substrate 1 is formed on the adhesion film 21b.
1a is attached and provided by a suitable method ((A) of FIG. 5). At this time, in order to improve the adhesive strength,
Heat treatment is performed at a temperature of about 00 ° C.

Then, the other Si substrate 11a is thinned to a suitable thickness (for example, about 40 nm) to form a semiconductor layer (Si layer) 11 (FIG. 5B).

Next, a SiO ₂ film 17 is formed as a first gate oxide film (film thickness of about 20 nm) on the semiconductor layer 11 by a suitable method, for example, thermal oxidation (FIG. 5C).

Next, the first gate 19 is provided on the first gate oxide film 15. First, polySi (polysilicon)
With a film thickness of about 200 nm by the low pressure CVD method, and p
By implanting As ions into polySi and then annealing it, an n ⁺ -polySi film is formed (not shown). The ion implantation conditions are, for example, 20 ekV and 5 × 10 15 cm ^2.
And Also, annealing is performed by RTA (Rapid Thirmal Anneal).
al) for about 10 seconds at 1050 ° C. Then n ⁺
A photolithography technique using a mask for alignment is applied to the -polySi film to form a first gate 19 at a position facing the second gate 23 ((D) of FIG. 5).

Next, the source / drain regions 13a and 13a are formed in the Si layer 11 on the side of the first gate 19 by an ion implantation method.
After providing 3b, activation annealing is performed to complete the nonvolatile memory cell transistor 200 having the structure shown in FIG.

Next, a modification of the embodiment will be described. FIG. 6 is a cross-sectional view showing a modified example. Briefly, an insulating oxide film 31 is formed on the Si substrate 30, and the memory cell basic structure 100 of FIG. 1 is rotated 90 ° on the window 31a provided in the insulating oxide film 31 so that the side surface of the memory cell basic structure 100 faces downward. It is provided in the form like. Here, the insulating film 21 on the second gate side is formed of the ferroelectric layer 21a and the SiO ₂ film 21b.
It is shown as a laminated film with. As described above, other forms can be applied as the memory cell of the present invention as long as the basic structure of FIG. 1 is included.

Obviously, the present invention is not limited to the above-mentioned embodiments. For example, in each of the above-mentioned illustrated examples, the MOSFET is described as being on the upper side and the control section being on the lower side. However, the MOSFET may be formed upside down. Further, the combination of materials and the manufacturing method are not limited to those listed here, and various kinds can be used.

[0042]

As is apparent from the above description, according to the nonvolatile memory cell transistor of the present invention, the FET structure is provided on the front surface side of the semiconductor layer and the FET structure is provided on the back surface side.
At least a control part for controlling the threshold voltage of and holding the ON / OFF state is constituted by the ferroelectric film and the auxiliary electrode. Therefore, there is no concern that the ferroelectric film will affect the FET side that operates as a switching element, and a memory cell that operates stably can be obtained. Also,
Since the structure of the double gate MOSFET can be adopted, it is possible to obtain a memory cell which has the advantages of this structure, such as large resistance to the short channel effect and ideal subthreshold characteristics.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view for explaining a basic structure of a nonvolatile memory cell transistor of the present invention.

FIG. 2 is a diagram showing a state under an auxiliary electrode (second gate) in a memory cell basic structure as an electrical conceptual diagram.

FIG. 3 is a schematic cross-sectional view showing a form example of an actually manufactured memory cell including a memory cell basic structure.

4A to 4D are process charts for explaining an example of a method for manufacturing a memory cell.

5A to 5D are process diagrams for explaining an example of the method of manufacturing the memory cell, following FIG.

FIG. 6 is a modification of the memory cell.

[Explanation of symbols]

10: FET structure 11: Semiconductor layer (Si layer) 13a: Source region 13b: Drain region 15: Channel region 17: First gate insulating film 19: First gate 20: Control part 21: Insulating film 21a: Ferroelectric layer 21b: Adhesion film (SiO ₂ film) 23: Auxiliary electrode (second gate) 25: Charge layer forming region 30: Si substrate 31: Insulating oxide film 100: Memory cell basic structure 200, 300: Nonvolatile memory cell transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 27/108 H01L 29/78 617S 21/8242 29/786 21/336

Claims (3)

[Claims] 1. A structure of a field effect transistor is provided on a front surface side of a semiconductor layer, and a threshold voltage of the field effect transistor is controlled on the back surface side of the semiconductor layer to hold the threshold voltage. A non-volatile memory cell transistor having a control unit. 2. The nonvolatile memory cell transistor according to claim 1, wherein the control unit includes a ferroelectric film provided on the back surface of the semiconductor layer, and an auxiliary electrode provided on the ferroelectric film. A non-volatile memory cell transistor, which is characterized by comprising at least. 3. A semiconductor layer having a source region, a drain region, and a channel region which is a current path between these regions, and a first gate insulating film provided on the surface of the semiconductor layer so as to straddle the both regions. A first gate provided on a region of the first gate insulating film facing the channel region, an insulating film provided on a back surface of the substrate, and facing the first gate on the insulating film. The second provided in the area
Of a double gate MOS transistor with a gate,
A nonvolatile memory cell transistor, wherein all or at least a part of the insulating film is made of a ferroelectric material.