JPH08153803A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor device and a method for manufacturing a semiconductor device, which can improve the junction breakdown voltage of a diffusion layer by a simple process with a small number of processes when a high breakdown voltage transistor is formed in a well region. To do. A well 32 is formed in a semiconductor substrate 21, and the well 32 has a portion 37 that requires a high breakdown voltage and a portion 36 that does not require a high breakdown voltage, and a region 36 is formed in the well formed in a region 28 having a high concentration. Then, the region 37 is formed in the well formed in the region 27 having a low concentration. When forming the region 37, a discontinuous opening portion 25 is provided in an impurity implantation mask for forming a well, and the impurity distribution implanted by this mask is redistributed by heat treatment to obtain a region 27 having a relatively low concentration. Thus, a low concentration region and a high concentration region are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. In particular, the present invention relates to a semiconductor device in which a well (a well of a conductivity type different from that of the semiconductor substrate or a well of the same conductivity type) is formed in a semiconductor substrate and a semiconductor element portion is formed therein, and a method of manufacturing such a semiconductor device. It is a thing.

[0002]

2. Description of the Related Art Conventionally, it is known that a well structure having a conductivity type different from that of the surroundings is formed in a semiconductor substrate, and an element portion is formed therein.

For example, conventionally, in forming a CMOS or the like, a so-called well structure has been used in which an impurity region having a conductivity type different from that of the substrate is formed on a part of the surface of the semiconductor substrate.

The well structure and the conditions for forming the well not only require reliable electrical isolation between the elements inside the well region and the outside, but also prevent problems such as latch-up. As a measure, it is desirable to set the condition of relatively low resistivity, that is, the condition of high impurity concentration.

On the other hand, for a so-called high breakdown voltage transistor which requires a high breakdown voltage for the source and drain terminals of the MOSFET, the following is required. That is, when such a high breakdown voltage transistor is formed by forming a well region having a conductivity type different from that of the substrate on a part of the surface of a semiconductor substrate and using the well region to obtain, for example, a semiconductor planar technology for obtaining a MOS, a source and a drain are formed. In order to secure the junction breakdown voltage between the diffusion layer and the semiconductor substrate or the well region, it is desirable that the impurity concentration of the semiconductor substrate or the well region is low.

As can be understood from the above description, when a high breakdown voltage transistor is to be formed in a well region, for example, in a well region having a CMOS structure, the well concentrations are required to conflict with each other. Conditions that satisfy the characteristics of 1 cannot be obtained. Therefore, it is necessary to perform a different mask process, ion implantation process, etc., to form well regions having different impurity concentrations.

A conventional method of forming a high breakdown voltage transistor will be described below with reference to a series of schematic sectional views of FIGS.

FIG. 6A shows the structure after the active region 2 is formed on the surface of the N-type semiconductor substrate 1 by selective field oxidation or the like. Reference numeral 1a indicates LOCOS which is an element isolation region.

FIG. 6B shows a state after the p-type well region 4 is formed in the active region 2 by using the well forming mask 3. The mask 3 can be formed by a usual process such as photolithography, and the well region 4 is formed by a usual process such as ion implantation.

In FIG. 7, after forming an impurity region 5 for adjusting the threshold value of a transistor in the active region 2 in the well region 4, a gate insulating film 6 is formed, and a Poly-
It is a figure which shows after forming the gate electrode 7 of the transistor by materials, such as Si.

In FIG. 8, a mask 8 is used to form a relatively low concentration n in a region on the drain terminal side of a high breakdown voltage transistor.
^- showing the structure after the formation of the impurity region 9. The formation of such an n ⁻ region 9 is often used in a high breakdown voltage transistor which requires a high breakdown voltage for its drain.

In FIG. 9, a mask 10 is used to form a source n ⁺ region 11 and a drain n ⁺ region 12 of a high breakdown voltage transistor.
It is a figure after forming.

As shown in FIG. 10, in the p-type well region 4 formed in the n-type semiconductor substrate 1 by the above method, the gate electrode 7, the source n ⁺ region 11 and the drain n are formed.
A high breakdown voltage transistor having a ⁺ region 12 and the like is formed.

At the drain terminal of the high breakdown voltage transistor, the maximum operating voltage is limited by the junction breakdown voltage between the drain n ⁺ region 12 and the p type well region 4 depending on the impurity concentration of the p type well region 4. Has been done. Therefore, when the impurity concentration of the p-type well region 4 is increased due to characteristics such as latch-up, it is necessary to set the maximum operating voltage of the high breakdown voltage transistor low. Alternatively, for the well in which the high breakdown voltage transistor is formed, it is necessary to newly perform a mask process, an ion implantation process, etc., to form a dedicated well.

[0015]

SUMMARY OF THE INVENTION The present invention provides a semiconductor device capable of improving the junction breakdown voltage of a source / drain diffusion layer by a simple process with a small number of steps when a high breakdown voltage transistor is formed in a well region. It is an object to provide a method for manufacturing a semiconductor device.

[0016]

The invention according to claim 1 of the present application is a semiconductor device in which a well is formed in a semiconductor substrate, and a portion requiring a high breakdown voltage and a portion not requiring a high breakdown voltage are formed in the well. The portion that does not require high breakdown voltage is formed in a well formed in a region having a relatively high concentration, and the portion requiring high breakdown voltage is formed in a well formed in a region having a relatively low concentration. A characteristic semiconductor device is to solve the above problems.

The invention of claim 2 of the present application is configured such that, of the diffusion layers formed in the well, a diffusion layer requiring a junction breakdown voltage is in contact with the region having a relatively low concentration. The semiconductor device according to claim 1, wherein the above problem is solved.

According to a third aspect of the present invention, in a method of manufacturing a semiconductor device, which comprises a step of forming a well in a semiconductor substrate and forming a high breakdown voltage element in the well, an impurity implantation mask for forming the well is used. By providing a discontinuous opening portion and redistributing the impurity distribution injected by the mask having the opening portion by heat treatment, a region having a relatively low concentration is formed. A method of manufacturing a semiconductor device, characterized in that a region having a relatively high concentration is formed, which solves the above problem.

According to a fourth aspect of the present invention, in a method of manufacturing a semiconductor device, which comprises a step of forming a well in a semiconductor substrate and forming a high breakdown voltage element in the well, an impurity implantation mask for forming the well is used. A wide opening portion and a discontinuous narrow opening portion are provided, and the impurity distribution injected by the mask portion having the narrow opening portion is redistributed by heat treatment to form a region having a relatively low concentration. 4. The manufacturing of a semiconductor device according to claim 3, wherein a region having a relatively low concentration and a region having a relatively high concentration are formed by forming a region having a relatively high concentration by the implanted impurities. A method for solving the above problems.

The invention of claim 5 of the present application is such that, of the diffusion layers formed in the well, a diffusion layer requiring a junction breakdown voltage is formed in contact with the region having a relatively low concentration. A method of manufacturing a semiconductor device according to claim 3, wherein the above problem is solved.

In the present invention, the terms "relatively high concentration" and "relatively low concentration" indicate that it is sufficient that one is higher or lower than the other in comparison with each other. The low-concentration region is preferably provided with a structure having a sufficient breakdown voltage when a component part of the device is formed here.

In the semiconductor device of the present invention, a semiconductor element in which latch-up or the like is required to be prevented, and a circuit (element portion not necessarily required to have a high withstand voltage) formed by these elements are formed in a well having a relatively high concentration. Can be preferably embodied as a semiconductor device formed in the well, in which a device requiring a high breakdown voltage and a circuit (a high breakdown voltage element portion) formed thereof are formed in a well formed in a region having a relatively low concentration.

[0023]

According to the present invention, the withstand voltage of the diffusion layer junction of the high breakdown voltage transistor structure formed in the well region can be improved with a simple structure, whereby a higher maximum operating voltage can be obtained. Further, it is possible to achieve both the latch-up prevention measure and the high breakdown voltage transistor characteristics in the CMOS structure and the like by a simple and low-cost manufacturing method.

[0024]

EXAMPLES Examples of the present invention will be described in detail below. However, as a matter of course, the present invention is not limited to the examples described below.

Example 1 This example embodies the present invention as a method of forming a semiconductor device having a high breakdown voltage transistor portion.
Although this embodiment shows a structure in which the breakdown voltage is increased only for the drain terminal, it is possible to increase the breakdown voltage in other portions, and other various transistor structures can also be increased in breakdown voltage according to the present invention. Can be implemented.

In the semiconductor device of this embodiment, as shown in FIG. 5, a well 32 having a conductivity type different from that of the surroundings is formed in a semiconductor substrate 21 (here, an N-type Si substrate).
2 requires a high breakdown voltage (in this example, the drain region 37
In the structure in which the high breakdown voltage is not necessarily required (the portion relating to the source region 36 in this example), the portion not requiring the high breakdown voltage (here, the portion relating to the source region 36) is compared. Formed in the well formed in the region 28 having a relatively high concentration, and the portion requiring a high breakdown voltage (here, the portion related to the drain region 37) is formed in the well formed in the region 27 having a relatively low concentration. It is a semiconductor device.

In the semiconductor device of this embodiment, as shown in FIG. 5, among the diffusion layers (source / drain regions 36 and 37 in this case) formed in the well 32, a diffusion layer requiring junction breakdown voltage (here, The drain region 37) is in contact with the region 27 having a relatively low concentration.

In the semiconductor device of this embodiment, as shown in FIG. 5, a well 32 having a conductivity type different from that of the surroundings is formed in the semiconductor substrate 21.
And forming a portion requiring high breakdown voltage (drain region 37 here) in the well 32, a discontinuous opening portion 25 is provided in the impurity implantation mask 23 for forming the well (FIG. 1B). By redistributing the impurity distribution implanted by the mask having the opening portion 25 by heat treatment (FIG. 2), a region 27 having a relatively low concentration is obtained, and thus, a region 27 having a relatively low concentration is relatively distributed. The high-concentration region 28 is formed.

In particular, in this embodiment, a wide opening portion 25 'and a discontinuous narrow opening portion 25 are provided in an impurity implantation mask for forming a well, and the impurity distribution implanted by the mask portion having the narrow opening portion 25 is heat-treated. By redistributing, a region 27 having a relatively low concentration is formed, and by forming a region 28 having a relatively high concentration by the impurities injected from the wide opening portion 25 ', a region 27 having a relatively low concentration is formed. And a region 28 having a relatively high concentration
Was formed.

In this embodiment, a diffusion layer (source / drain regions 36 and 3 in this case) formed in the well 32 is formed.
Of 7), the diffusion layer (here, the drain region 37) requiring the junction breakdown voltage is formed in contact with the region 27 having a relatively low concentration.

The high voltage transistor forming method of this embodiment will be described in more detail with reference to a series of schematic sectional views of FIGS.

FIG. 1A shows a structure similar to that of FIG. 6A described above. That is, the active region 22 is formed on the surface of the N-type semiconductor substrate 21 by selective field oxidation or the like.
1 shows the structure after formation of. Reference numeral 21a indicates LOCOS which is an element isolation region.

FIG. 1B is a diagram showing a state after the p-type impurity region 24 is formed in the active region 22 by using the well forming mask 23. At this time, the mask 23 has a shape in which the opening 25 is discontinuously provided on the drain side that requires a high breakdown voltage, so that the mask 23 is surrounded by the p-type impurity region 24 formed by ion implantation or the like. Will form a region 26 into which no impurities are implanted.

FIG. 2 shows the result of the post heat treatment of FIG.
By diffusing the impurities in the p-type impurity region 24, the p-type impurity region 24 and the region 2 where the impurity is not implanted
6 shows a state in which the impurity concentrations of 6 are averaged. As a result, the p-type impurity region 27 having a relatively low concentration is formed. Further, the threshold adjustment impurity region 29, the gate insulating film 30,
The gate electrode 31 is formed to obtain the structure shown in FIG. FIG.
By the step of obtaining (b) and by this step, a relatively high-concentration region 28 and a relatively low-concentration region 27 are formed as p-type impurity regions, and these collectively form the p-type well region 32. ing.

FIGS. 3 and 4 are obtained by the same steps as those for obtaining FIGS. 8 and 9 described above. That is, FIG. 3 shows the structure after the relatively low concentration n ⁻ -type impurity region 34 is formed in the region on the drain terminal side of the high breakdown voltage transistor by using the mask 33. As mentioned above, such n ⁻
The formation of the region 34 is often used in a high breakdown voltage transistor that requires a high breakdown voltage in its drain.

In FIG. 4, the source n ⁺ region 36 and the drain n ⁺ region 37 of the high breakdown voltage transistor are formed by using the mask 35.
It is a figure which shows the structure after forming.

Next, referring to FIG. By the method as described above, the high breakdown voltage transistor having the gate electrode 31, the source region 36, the drain region 37, etc. in the p-type well region 32 having the low-concentration impurity region 27 formed in the n-type semiconductor substrate 21. Is formed. Where drain ⁺
The region 37 is a region 2 having a relatively low concentration in the well 32.
7, the junction breakdown voltage between the drain n ⁺ region 37 and the p-type well region is determined by the impurity concentration of the low-concentration impurity region 27. Therefore, a high operating voltage can be realized.

Further, according to this method, it is possible to increase the well concentration and prevent the latch-up failure (which is a serious problem in the case of a CMOS structure, etc.) and the like, and to achieve both the withstand voltage characteristics required for the high withstand voltage transistor. This can be realized without adding a new mask process, and it is possible to manufacture a high-performance semiconductor device at low cost.

Regarding the conduction type of the semiconductor shown in the above embodiments, the same applies even if the p type and the n type are replaced.

According to this embodiment, a higher maximum operating voltage can be obtained by improving the diffusion layer junction breakdown voltage of the high breakdown voltage transistor structure formed in the well region.

Further, it is possible to achieve both the prevention of latch-up and the high breakdown voltage transistor by a low cost manufacturing method.

Example 2 In this example, the present invention is embodied as a CMOS transistor having a transistor having the structure of Example 1 and having a complementary MOS on the same plane.

FIG. 11 shows the structure of this embodiment. In the semiconductor device of the present embodiment, the left side portion of FIG. 11 is a MOS transistor part having the same structure as that of the first embodiment, and the same reference numerals as those in the first embodiment are attached. On the right side of the figure of this structure, on the n-type semiconductor (Si) substrate 21, the source p region 36 ′ which is a p-type impurity diffusion layer and the drain p region 3 are formed.
7'is formed and Po is formed through the gate insulating film 30 '.
A ly-Si gate electrode 31 'is formed to form a MOS structure.

In this embodiment, it is possible to easily achieve the latch-up prevention and the like in the CMOS structure and the high breakdown voltage transistor at a low cost, and the other advantages of the present invention described above can be fully exhibited.

Example 3 In this example, a well of the same conductivity type as the substrate was formed, and a transistor having a portion requiring high breakdown voltage was formed on the well.

Here, an n-type well was further formed on an n-type semiconductor (Si) substrate, and an element requiring a high breakdown voltage portion was formed in this well in the same manner as in Example 1.

Such a structure can be adopted when, for example, a twin well is used, and has advantages such as improved CMOS latch-up resistance and improved parasitic transistor characteristics. In addition, this embodiment also has the same effects as the above-mentioned embodiments.

Needless to say, each of the examples including the present example exhibits the same action when the n-type and the p-type are reversed.

[0049]

As described above, according to the present invention,
In the case of forming a high breakdown voltage transistor in the well region, etc., it is possible to provide a semiconductor device and a method of manufacturing a semiconductor device that can achieve improvement in the junction breakdown voltage of the source and drain diffusion layers by a simple process with a small number of processes.

[Brief description of drawings]

1A to 1C are sectional views showing steps of Example 1 in order (1).

2A to 2C are sectional views showing the steps of Example 1 in order (2).

FIG. 3 is a sectional view showing the steps of Example 1 in order (3).

FIG. 4 is a sectional view showing the steps of Example 1 in order (4).

FIG. 5 is a sectional view showing the steps of Example 1 in order (5).

FIG. 6 is a sectional view showing the steps of the conventional example in order (1).

FIG. 7 is a sectional view showing the steps of the conventional example in order (2).

FIG. 8 is a sectional view showing the steps of the conventional example in order (3).

FIG. 9 is a sectional view showing the steps of the conventional example in order (4).

FIG. 10 is a sectional view showing the steps of the conventional example in order (5).

FIG. 11 is a cross-sectional view showing the structure of the semiconductor device of Example 2;

[Explanation of symbols]

 21 semiconductor substrate 22 active region 23 mask 25 discontinuous opening (narrow mask) 25 'wide opening (mask) 27 relatively low concentration region 28 relatively high concentration region 30 gate insulating film 31 gate 32 well 36 source Region 37 Drain region (portion requiring high breakdown voltage)

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/266 21/06 21/822 H01L 21/265 MA 27/06 Z

Claims (5)

[Claims] 1. A semiconductor device in which a well is formed in a semiconductor substrate, and a portion requiring a high breakdown voltage and a portion not requiring a high breakdown voltage are formed in the well, and the portion not requiring the high breakdown voltage has a relatively high concentration. A semiconductor device characterized in that it is formed in a well formed in a certain region, and a portion requiring a high breakdown voltage is formed in a well formed in a region having a relatively low concentration. 2. A diffusion layer, which requires a junction breakdown voltage, of the diffusion layers formed in the well, is in contact with the region having a relatively low concentration. The semiconductor device according to. 3. A method of manufacturing a semiconductor device, comprising a step of forming a well in a semiconductor substrate and forming a high breakdown voltage element in the well, wherein a discontinuous opening portion is provided in an impurity implantation mask for forming the well, A region having a relatively low concentration is formed by redistributing the impurity distribution injected by the mask having the opening portion by heat treatment to form a region having a relatively low concentration and a region having a relatively high concentration. A method of manufacturing a semiconductor device, comprising: 4. A method of manufacturing a semiconductor device, comprising a step of forming a well in a semiconductor substrate and forming a high breakdown voltage element in the well, wherein an impurity implantation mask for forming the well has a wide opening portion and a discontinuous narrow portion. By providing an opening portion and redistributing the impurity distribution implanted by the mask portion having the narrow opening portion by heat treatment, a region having a relatively low concentration is formed, and the impurity implanted from the wide opening portion has a relatively high concentration. 4. The method for manufacturing a semiconductor device according to claim 3, wherein a region having a relatively low concentration and a region having a relatively high concentration are formed by forming a region having a high concentration. 5. A diffusion layer that requires a junction breakdown voltage, of the diffusion layers formed in the well, is formed in contact with the region having a relatively low concentration.
Alternatively, the manufacturing method of the semiconductor device according to the item 4.