JPS63241965A - Insulated-gate field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent source, drain junction breakdown strength from decreasing and a leakage from increasing while a punch-through or a short channel effect is suppressed by selectively forming a channel impurity layer at the center of a channel region. CONSTITUTION:A channel impurity layer 6 is selectively formed at a center except the ends of source, 4, drain 5 side ends of a channel region. Thus, even when a channel impurity layer 6 is formed in a relatively high concentration, it can suppress the increase in the junction leakage of the source, 4 the drain 5 and the decrease in its bonding breakdown strength. Since a channel surface electric field near the drain is reduced, an impact ionization can be suppressed. Since its threshold value is determined by the channel impurity layer at the center of the channel region, a short channel effect can be suppressed. As a result that the increase in the junction capacity of the source, the drain can be suppressed, high speed operation characteristic is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application) The present invention relates to an insulated gate field effect transistor (MoS transistor) with a fine structure suitable for integrated circuits and a method for manufacturing the same.

(Prior Art) In recent years, the miniaturization, high integration, and speed-up of semiconductor integrated circuit elements have been remarkable. Particularly in integrated circuits using MoS transistors, elements have become increasingly finer, gate lengths have become shorter to 1 μm or less, and gate insulating films have become thinner, to about 100 μm or less. In such a miniaturized MOS transistor, the bunt-through breakdown voltage between the source and drain becomes extremely small, and a short channel effect occurs in which the threshold voltage decreases.

In order to solve these problems, it is necessary to increase the impurity concentration at the surface of the channel region, and for this reason, conventional methods have been used, for example, to form an impurity layer of the same conductivity type as the substrate on the substrate surface by ion implantation. This is being done more than ever. However, if the concentration of the channel impurity layer is increased to sufficiently compensate for the short channel effect and the reduction in bunch-through breakdown voltage, this will result in an increase in leakage current between the channel region and the source and drain diffusion layers, a decrease in the junction breakdown voltage, and a decrease in the junction breakdown voltage. The capacitance increases, which impedes the speeding up of the element. Also, if the gate length is short, the channel surface electric field near the drain becomes very large.
The reliability of the device becomes low due to phenomena such as impact and ionization.

(Problems to be Solved by the Invention) As described above, when MOS transistors are further miniaturized, various adverse effects on reliability and device characteristics arise due to the formation of a channel impurity layer.

SUMMARY OF THE INVENTION An object of the present invention is to solve such problems and provide a MOS transistor and a method for manufacturing the same, which make it possible to obtain excellent device characteristics and reliability even when miniaturized.

[Structure of the Invention] (Means for Solving the Problems) The MOS transistor according to the present invention has a channel impurity layer selectively formed in the center of the channel region excluding the source and drain side ends. Features.

In addition, in the method of the present invention for forming a MOS transistor having such a structure, a first mask material film having an opening in the gate region is formed on the semiconductor substrate, and then a second mask material film is selectively applied to the sidewalls of the opening. Forming a film, these first. Second
Using the mask material film as a mask, impurity ions are implanted to form a channel impurity layer. The material film of the gate N pole is formed in the first step. The pattern may be formed either before or after the formation of the second mask material film, but the pattern is formed to have dimensions defined by the openings in the first mask material film.

(Function) In the Mo8)-transistor of the present invention, the channel impurity layer is selectively formed not over the entire channel region but at the center. Therefore, even when the channel impurity layer has a relatively high concentration, an increase in source/drain junction leakage and a decrease in junction breakdown voltage are suppressed. Furthermore, since the channel surface electric field near the drain is relaxed, impact ionization is also suppressed. Since the threshold value is determined by the channel impurity layer at the center of the channel region, the short channel effect is also suppressed. Furthermore, increase in junction capacitance between the source and drain is also suppressed, thereby ensuring high-speed operation characteristics. Furthermore, with the structure of the present invention, the capacity of the channel portion can be reduced as a whole, and a device with high stream flow driving ability can be obtained.

According to the method of the present invention, the channel impurity layer includes a first mask material film having an opening defining a channel region (gate region) and a second mask material film selectively formed on the sidewall of the opening. By ion implantation using as a mask,
Formed in a self-consistent manner.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an n-channel MOS transistor of one embodiment. A polycrystalline silicon gate electrode 3 is formed on the surface of a p-type 3i substrate 1 via a gate insulator wA2, and using this gate electrode 3 as a mask, impurity ions are implanted to form an n
+ type source and drain diffusions 114.5 are formed. In the channel region between the source and drain diffusions 114.5, a p-type layer 6 is selectively formed as a channel impurity layer only in the center thereof.

FIGS. 2(a) to 2(e) show an example of the manufacturing process for obtaining this bottle-shaped MOS transistor structure.

After forming an element isolation region (not shown) on the p-type 3i substrate 1, first, as shown in (a), a thermal oxide film 2' is deposited with a thickness of approximately 20 mm.
4,000 layers of silicon nitride 117 (first mask material film) are deposited thereon by the CVD method, and these laminated films are patterned to form openings 10 between the gate wirings. Next, as shown in FIG.
00 people deposited. Then, anisotropic etching is performed on the entire surface to leave the oxide film 8 only on the side wall of the opening 10 of the nitride film 17, as shown in (C).
Using this as a mask, boron ions are implanted to form a p-type layer 6 in the center of the channel region. At this time, the ion implantation conditions are, for example, an acceleration voltage of 50 keV and a dose of ff11×101.
3/aR2.

After that, after selectively removing the oxide G18, a gate insulating film 11m2 is formed by thermal oxidation, a polycrystalline silicon film is deposited on the entire surface and this is etched back, and the nitride 117 is formed as shown in (d). It is buried only in the opening 10 and serves as a gate electrode. For the gate electrode, for example, 2
Heat treatment is performed for 0 minutes to perform phosphorus diffusion. Then, the nitride layer 117 is removed by etching, and impurity ions are implanted using the gate electrode as a mask to form n+ type source and drain diffusions 1114.5 as shown in (8).

After this, although not shown in the figure, CVD-based nIl is deposited on the entire surface.
Contact holes are formed in this to form source, drain, and gate electrode wirings.

Thus, according to the method of this embodiment, the p-type layer 6 as a channel impurity layer is selectively formed in the center of the channel region.
Formed in a self-consistent manner. Moreover, since the polycrystalline silicon 113, which is the gate electrode material, is patterned in such a way that it is buried in the opening 10 of the nitride film 7, short circuit accidents between gate wirings that often occur when patterning is performed by ordinary photoetching can be prevented. Ru.

In the MoS transistor according to this embodiment, the threshold value is determined by the channel impurity layer at the center of the channel region, and by making this a relatively high concentration, the short channel effect is suppressed. Moreover, since there is no channel impurity layer near the source and drain, the junction breakdown voltage between the source and drain is high and there is little junction leakage. The electric field on the surface of the channel region near the drain also becomes smaller. As a result, the reliability of the MOS transistor becomes high. Further, for the same reason, the junction capacitance between the source and the drain is reduced, and the capacitance of the gate portion is also reduced as a whole, so that a MoS transistor with excellent high speed performance, excellent cutoff characteristics, and large current driving ability can be obtained.

FIGS. 3(a) to (Q) show n-channel MOs of other embodiments.
The manufacturing process of an S transistor is shown. Parts corresponding to those in the previous embodiment are given the same reference numerals as in the previous embodiment. In this example, unlike the previous example, a channel impurity layer is formed with a gate electrode material film formed in advance. That is, first, as shown in (a), a gate insulator 1 made of a thermal oxide film of 120 layers is formed on a p-type 3i substrate 1! Polycrystalline silicon 113, which will become a gate electrode, is deposited on the entire surface by 2,000 layers via J2, and silicon nitride 1!7 (first mask material film) is formed thereon by 3,000 layers. Polycrystalline silicon! In step 13, phosphorus diffusion is performed by heat treatment at 900° C. for 20 minutes in POCffia gas. Thereafter, an opening 10 is formed in the gate region of the nitride film 7 by a well-known photoetching method. Then, as shown in (b), for example, 3000
CVD of human silicon oxide film 8 (second mask material film)
The p-type layer 6 as a channel impurity layer is removed by boron ion implantation, and is removed by anisotropic etching, leaving only the sidewall of the opening 1o, as shown in (C). Formed in the center of the area.

At this time, the ion implantation conditions are, for example, an acceleration voltage of 160ke.
V, the dose is 11X1013/12. After removing the oxidized llll8, a photoresist 9 is applied to the entire surface as shown in (d).

This photoresist 9 is etched back to form a nitrided I! layer as shown in (e). It remains only in the opening 10 of I7.

Then, as shown in (f), the nitride 117 is removed by etching. Thereafter, the polycrystalline silicon film 3 is etched using a photoresist 9 to form a gate electrode, and then impurity ions are implanted using this as a mask to form an n-medium source and drain diffusion layer 3 as shown in (Q). , 5.

This embodiment also provides the same effects as the previous embodiment. That is, as in the previous embodiment, the channel impurity layer is selectively and self-alignedly formed in the center of the channel region.
Furthermore, the characteristics and reliability of the obtained MOS transistor are excellent for the same reasons as in the previous embodiment.

The present invention is not limited to the above embodiments.

For example, in addition to a polycrystalline silicon film, a high melting point metal or its silicide can be used for the gate electrode. Also number 1. Various combinations of a polycrystalline silicon film, a high melting point metal film, etc. can be considered as the second mask material film. In addition to the channel impurity layer selectively provided at the center of the channel region, an impurity layer may be formed at a very low concentration over the entire channel region. The present invention is also effective when an epitaxial wafer is used as the substrate.

In addition, the present invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, in the MOS transistor according to the present invention, since the channel impurity layer is selectively formed in the center of the channel region, various problems can be solved when the channel impurity layer is formed in the entire channel region. resolved. In other words, while suppressing bunch through and short channel effects, the source
A reduction in drain junction breakdown voltage and an increase in leakage are prevented, and the reliability of the fine MOS transistor is improved. In addition, the increase in source and drain junction capacitance due to the channel impurity layer is suppressed, and at the same time, the capacitance of the gate region is also reduced.
Excellent properties can be obtained.

Further, according to the method of the present invention, since the channel impurity layer is formed in a self-aligned manner at the center of the channel region, it is possible to easily obtain a fine MOS transistor having excellent reliability and characteristics as described above.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a MOS t-transistor according to an embodiment of the present invention, FIGS. 2(a) to (e) are diagrams showing its manufacturing process, and FIGS. 3(a) to (Q) are diagrams showing other It is a figure which shows the manufacturing process of the MOS transistor of an Example. 1... P-type 3 as a substrate, 2... Gate insulating film, 3...
...Polycrystalline silicon gate electrode, 4...n++ source diffusion layer, 5...n+ type drain diffusion layer 6...p
Type layer (channel impurity layer), 7... silicon nitride film (
First mask material 11, 8... silicon oxide film (second mask material film), 9... photoresist, 10...
...Aperture. Applicant's agent Patent attorney Takehiko Suzue No. 1 LjlJJ No. 20 (1) No. 20 (2) Third layer (1)

Claims (5)

[Claims] (1) source and drain diffusion layers of conductivity type opposite to the substrate, which are formed on a semiconductor substrate at a distance from each other, and a gate electrode formed on a channel region between these source and drain diffusion layers via a gate insulating film; In an insulated gate field effect transistor having a channel impurity layer of the same conductivity type as the substrate doped at the surface of the channel region of the substrate for threshold control, the channel impurity layer is doped with the source of the channel region; An insulated gate field effect transistor characterized in that it is selectively formed in the center part excluding the end part on the side of the drain diffusion layer. (2) A first semiconductor substrate having an opening in the gate formation region.
a step of forming a second mask material film selectively on the sidewall of the opening of the first mask material film; and a step of forming the first and second mask material films with ion resistance. A step of ion-implanting impurities as an implantation mask to form a channel impurity layer of the same conductivity type as the substrate on the surface of the substrate, a step of removing the second mask material film, and an opening in the first mask material film. An insulated gate type characterized by comprising the steps of: forming a gate electrode whose dimensions are defined by , and doping impurities using the gate electrode as a mask to form source and drain diffusion layers of conductivity type opposite to that of the substrate. A method of manufacturing a field effect transistor. (3) In the step of forming the gate electrode, after forming the channel impurity layer and removing the second mask material film,
A gate insulating film is formed on the substrate surface in the opening of the first mask material film, and a polycrystalline silicon film is deposited on the entire surface, and this is buried only in the opening of the first mask material film. A method for manufacturing an insulated gate field effect transistor according to claim 2. (4) In the step of forming the gate electrode, a polycrystalline silicon film is deposited in advance on the entire surface of the substrate with a gate insulating film interposed therebetween before forming the first and second mask material films, and the polycrystalline silicon film is passed through the gate insulating film. After forming the channel impurity layer by ion-implanting impurities, the polycrystalline silicon film is patterned into a gate electrode having a size defined by the opening of the first mask material film. Second
A method for manufacturing an insulated gate field effect transistor according to section 1. (5) The method for manufacturing an insulated gate field effect transistor according to claim 2, wherein the first mask material film is a silicon nitride film, and the second mask material film is a silicon oxide film.