JP2002158349A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce on-resistance while maintaining withstand voltage. A gate oxide film is formed on a P-type semiconductor substrate.
A gate electrode 12 formed through the gate electrode 12A, an N-type high-concentration source region 13 formed adjacent to the gate electrode 12, and an N-type high-concentration source region 13 formed at a position separated from the gate electrode 12. A high-concentration drain region 14 and an N-type drift region 3 formed so as to surround the drain region 14.
A semiconductor device in which an N-type layer 6 having a concentration lower than the concentration of the drain region 14 and higher than the concentration of the drift region 3 is formed so as to surround the vicinity of.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a technique for reducing on-resistance without impairing the withstand voltage of a high withstand voltage MOS transistor.

[0002]

2. Description of the Related Art A conventional semiconductor device will be described below with reference to the drawings.

In FIG. 8, reference numeral 51 denotes a P-type semiconductor substrate, for example, in which an LN layer 52 (which constitutes a drift region) is formed. 53A and 53B are LO
A selective oxide film (constituting a first gate oxide film) and an element isolation film formed by the COS method.

Reference numeral 54 denotes a second gate oxide film, and 55 denotes a first gate oxide film 5 from the second gate oxide film 54.
A gate electrode formed so as to extend over 3A and 5A
Reference numerals 6 and 57 denote an N-type high-concentration source region formed adjacent to the gate electrode 55 and an N-type high-concentration drain region formed at a position separated from the gate electrode 55.

In the above-described conventional semiconductor device, as shown in FIG. 8, in order to increase the breakdown voltage, a drift region (LN layer 5) deeply diffused so as to surround the drain region 57 is formed.
2) A semiconductor device having a one-sided LDD structure having the above (2).

[0006]

The one-sided L as described above
In the semiconductor device having the DD structure, since this portion has a high resistance, the driving capability is reduced.

In a semiconductor device having a one-sided LDD structure to which a high voltage is applied only to the drain region side, the drain region side is provided with a high-concentration drain region 57 as described above in order to reduce concentration of an electric field. Although it was surrounded by the low concentration drift region (LN layer 52), only the high concentration source region 56 was on the source region side.

[0008] Even in the semiconductor device having such a structure, there is no need to particularly make the static withstand voltage a problem.
However, during operation, the following problem has occurred.

That is, a source region (emitter region), a substrate (base region), and a drain region (collector region)
In the bipolar structure composed of, the high concentration source region 56 is exposed in the emitter region, so that the carrier injection efficiency is high and the substrate current Isub is large, so that the bipolar transistor is easily turned on.

That is, since the current gain β of the bipolar transistor is high, the drain breakdown voltage during operation is lower than that of the semiconductor device having the double-sided LDD structure.

Here, in order to improve the drain breakdown voltage during operation, it is necessary to reduce the substrate current Isub. That is, it is necessary to further reduce the drain electric field.

However, if the impurity concentration of the entire low-concentration drift region (LN layer 52) is reduced in order to reduce the substrate current Isub, the substrate current Isu is reduced as shown by the solid line in FIG.
b has a double hump structure having two peaks ((1) and (2)) as the voltage Vgs increases.

The low concentration drift region (LN
If the layer 52) has a lower concentration, the substrate current Isub
The first peak (1) is low, and the drain breakdown voltage at low Vgs is improved, but the second peak (2) of the substrate current Isub
Becomes relatively high, so that the drain breakdown voltage at the time of high Vgs decreases.

Conversely, a low-concentration drift region (LN
When the impurity concentration of the entire layer 52) is increased, as shown by a dashed line in FIG. 9, the substrate current Isub has one peak with a certain voltage Vgs as a peak, which is effective for drain withstand voltage at a high Vgs. In addition, there is a problem that there is no drain withstand voltage at the time of low Vgs.

As described above, if the impurity concentration of the entire low-concentration drift region (LN layer 52) is uniformly changed,
The trade-off relationship between the drain withstand voltage at low Vgs and the drain withstand voltage at high Vgs cannot be escaped.

In addition, a commonly used double-sided LDD
If the structure is adopted, the current gain β decreases and the withstand voltage surely exists. However, although the source region side does not originally require a withstand voltage, the normal LDD structure is adopted also on the source side, so that the drain region side is adopted. Drift region distance (L) similar to
, The on-resistance increases and the driving ability decreases.

[0017]

SUMMARY OF THE INVENTION In view of the above-mentioned problems, a semiconductor device according to the present invention includes a first gate oxide film formed on a semiconductor layer of a first conductivity type and a second gate oxide film formed on the second gate oxide film. A gate electrode formed so as to span, a source region of the second conductivity type formed adjacent to the gate electrode, and a drain region of the second conductivity type formed at a position separated from the gate electrode. And a second conductivity type drift region formed so as to surround the drain region, wherein the concentration is lower than the concentration of the drain region so as to surround the vicinity of the high concentration drain region. A second conductivity type impurity layer having a high concentration is formed.

Further, the manufacturing method is characterized in that a second conductivity type impurity is ion-implanted into the first conductivity type semiconductor layer to form a first implantation layer, and this is diffused to form a second conductivity type impurity. After the low concentration drift region is formed, a second conductivity type impurity is ion-implanted into the drift region to form a second implantation layer. Subsequently, after forming an oxidation-resistant film in a predetermined region on the semiconductor layer and forming a resist film in a predetermined region on the semiconductor layer including the oxidation-resistant film, the oxidation-resistant film and the resist film are formed. Is used as a mask to ion-implant a first conductivity type impurity to form a third implantation layer in a predetermined region on the semiconductor layer. Next, after removing the resist film, the semiconductor layer is LOCOS-oxidized using the oxidation-resistant film as a mask to form a selective oxide film and an element isolation film.
Impurities in the third implantation layer are diffused to form a second conductivity type impurity layer, and a first conductivity type channel stopper layer is formed below the element isolation film. Further, a gate oxide film is formed by thermally oxidizing the semiconductor layer using the selective oxide film and the element isolation film as a mask, and a gate electrode is formed so as to extend from the gate oxide film to the selective oxide film. Then, using the gate electrode and the selective oxide film as a mask, a second conductivity type impurity is ion-implanted to form a second conductivity type high concentration source region adjacent to the gate electrode, and to be separated from the gate electrode. Forming a second-conductivity-type high-concentration drain region at the specified position.

Thus, a second conductivity type impurity layer having a lower concentration than the drain region and a higher concentration than the drift region is formed so as to surround the vicinity of the high concentration drain region in the low concentration drift region. Thus, instead of uniformly changing the impurity distribution in the low-concentration drift region, the low-concentration drift region is provided with a low Vgs breakdown voltage, and the second-conductivity-type impurity having a higher impurity concentration than the low-concentration drift region. The layer can have a high Vgs breakdown voltage.

Further, the second conductive type impurity layer is formed in the same step as the step of forming a second conductive type channel stopper layer under an element isolation film formed between the first and second conductive type MOS transistors. It is characterized by being.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device according to the present invention and a method for manufacturing the same will be described below with reference to the drawings.

FIGS. 1 to 7 are sectional views showing a method of manufacturing a high voltage MOS transistor of the present invention in the order of steps, and show an N-channel type high voltage MOS transistor structure as an example. Although the description of the structure of the P-channel high-voltage MOS transistor is omitted, it is well known that the structure is the same except for the conductivity type.

First, referring to FIG. 1, using a resist film 2 formed on a P-type semiconductor substrate 1 as a mask, an N-type impurity is ion-implanted into a desired region of the substrate 1 to form a first implanted layer 3A. .

Subsequently, after the resist film 2 is removed, impurities in the first injection layer 3A are diffused to form a low-concentration N-type layer 3 (hereinafter, referred to as an LN layer 3). . Here, the LN layer 3 constitutes a low concentration drift region. In this step, as an N-type impurity, for example, phosphorus ions are implanted at an acceleration voltage of about 100 KeV and under an implantation condition of about 6.5 × 10 ¹² / cm ² , and the phosphorus ions are thermally diffused at about 1100 ° C. for 4 hours. ing.

Next, referring to FIG. 3, using a pad oxide film 4 formed on the substrate 1 and a resist film 5 having an opening on the LN layer 3 as a mask, a desired region of the LN layer 3 is doped with N-type impurities. The second implantation layer 6A is formed by ion implantation. In this step, for example, phosphorus ions as N-type impurities are added at an acceleration voltage of about 160 KeV to about 5.0.
The implantation is performed under the conditions of × 10 ¹³ / cm ² . The pad oxide film 4 is for suppressing the formation of a damaged layer on the surface of the substrate during ion implantation. Further, the impurities in the second injection layer 6A formed on a predetermined region of the LN layer 3 are diffused into the substrate by a heat treatment in a process of forming the selective oxide film 10A and the element isolation film 10B as described later. The N-type layer 6 is formed. More specifically, the N-type layer 6
Is a P-channel type M transistor mixed with an N-channel type MOS transistor (the high-voltage MOS transistor of the present embodiment).
In order to isolate an element from an OS transistor (not shown), a step of forming a channel stopper layer (not shown) made of an N-type impurity layer formed on the P-channel MOS transistor side is used.

Further, in FIG. 4, after removing the resist film 2, a silicon nitride film 7 and a resist film 8 are formed by patterning on predetermined regions of the substrate 1, respectively.

Further, P-type impurities are ion-implanted using the silicon nitride film 7 and the resist film 8 as a mask to form the substrate 1.
The third injection layer 9A is formed on the predetermined region of FIG. Note that, in this step, for example, boron ions as P-type impurities are approximately 5.0 × 10 ¹³ / c at an acceleration voltage of approximately 100 KeV.
It is performed under the injection condition of m ² . Further, impurities in the third implantation layer 9A formed on a predetermined region of the substrate 1 are diffused into the substrate by heat treatment during the formation process of the selective oxide film 10A and the element isolation film 10B, as described later. A channel stopper layer (P-type layer 9) formed on the N-channel MOS transistor side to separate the channel-type MOS transistor from the P-channel MOS transistor.

After the resist film 8 is removed as shown in FIG. 5, the substrate surface is LOCOS-oxidized using the silicon nitride film 7 as a mask to form a selective oxide film 10A (about 1 nm) having a thickness of about 800 nm. And a device isolation film 10B. This LOCO
Phosphorus ions in the second implanted layer 6A are diffused by the heat treatment during the S oxidation treatment, and N
A mold layer 6 is formed, and boron ions in the third implantation layer 9A are diffused to form a P-type layer 9 as a channel stopper layer below the element isolation film 10B. That is, the N-type layer 6 is located under the element isolation film of a P-channel MOS transistor (for example, a P-channel MOS transistor having a normal withstand voltage of about 5 V) mixed with the N-channel high-voltage MOS transistor of this embodiment. Since the step of forming the channel stopper layer to be formed is diverted, the number of manufacturing steps is not newly increased for forming the N-type layer 6.

Subsequently, in FIG. 6, the selective oxidation film 10A and the element isolation film 10 are thermally oxidized on the substrate 1.
A second gate oxide film 11 having a thickness of about 45 nm is formed in a region other than B, and a gate is formed so as to extend from the second gate oxide film 11 to a selective oxide film 10A (first gate oxide film). The electrode 12 is formed with a thickness of about 400 nm. Note that the gate electrode 12 of the present embodiment is
It is made of a polysilicon film which is made conductive by phosphorus doping using Cl ₃ as a heat diffusion source. Furthermore, tungsten silicide (WSi) is formed on the polysilicon film.
x) A polycide electrode formed by laminating films or the like may be used.

Subsequently, referring to FIG.
2. N-type impurities are implanted by using the selective oxide film 10A and the element isolation film 10B as a mask to form a high-concentration N-type diffusion region 1.
3 (hereinafter, referred to as a source region 13) and a high-concentration N-type diffusion region 14 (hereinafter, referred to as a drain region 14). In this step, for example, about 7
At an acceleration voltage of 0 KeV, about 1.0 × 10 ¹⁴ / cm ²
And an arsenic ion of about 8
At an acceleration voltage of 0 KeV, about 6.0 × 10 ¹⁵ / cm ²
By so doing, source / drain regions having a so-called DDD structure are formed. Furthermore, the source / drain regions 13 and 14 are not limited to the DDD structure, but may have a so-called LDD structure.

Hereinafter, although illustration is omitted, an interlayer insulating film is formed on the entire surface of the substrate, a source electrode and a drain electrode are formed through the interlayer insulating film, and then a passivation film (not shown) is formed. Complete the device.

As described above, according to the present invention, in the drift region (LN layer 3) formed so as to surround the drain region 14, the concentration of the drain region 14 is set so as to surround the vicinity of the drain region 14. By forming the N-type layer 6 which is lower than that of the drift region (LN layer 3) and has a higher concentration, the resistance value of the drift region can be reduced without causing deterioration in breakdown voltage. Therefore, high withstand voltage MO
The on-resistance of the S transistor can be reduced.

Furthermore, since the on-resistance can be reduced as described above, the gate width (GW) size of the high breakdown voltage MOS transistor can be reduced, and the area occupied by the transistor can be reduced. it can.

In the present invention, the step of forming the N-type layer 6 is diverted from the step of forming a channel stopper layer made of an N-type impurity layer below the element isolation film of the mixed P-channel MOS transistor. Since they are formed in the same process, the number of manufacturing processes does not increase, and workability is good.

Further, as shown in FIG. 7, the N-type layer 6
It is formed so as to substantially uniformly surround the vicinity of the drain region 14 to a position adjacent to one end of the gate electrode via a first gate oxide film and adjacent to one end of the element isolation film 10B. Therefore, the vicinity of the drain region 14 has a uniform concentration distribution, and local electric field concentration due to a difference in local concentration distribution can be avoided.

[0036]

According to the present invention, an impurity layer having a lower concentration than the drain region and a higher concentration than the drift region is formed so as to surround the vicinity of the high-concentration drain region formed in the drift region. Thus, the resistance value of the drift region can be reduced without causing the withstand voltage deterioration, and the on-resistance can be reduced.

Further, since the on-resistance can be reduced as described above, the gate width (GW) of the transistor can be reduced, and the area occupied by the transistor can be reduced.

Further, in the present invention, the step of forming an impurity layer formed to surround the vicinity of the high-concentration drain region formed in the drift region is performed by using another conductive type MO that is mixedly mounted.
Since the step of forming the channel stopper layer formed under the element isolation film on the S transistor side is diverted, the problem that the number of manufacturing steps is increased does not occur.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 7 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 8 is a sectional view showing a conventional semiconductor device.

FIG. 9 is a diagram for explaining a problem of the related art.

Continued on the front page F term (reference) 5F040 DA10 DA20 DA22 DB03 DC01 EC01 EC07 EC13 EC24 ED09 EF02 EF13 EF18 EK01 EK02 FB01 FC17

Claims (7)

[Claims] A gate electrode formed on a semiconductor layer of a first conductivity type via a gate oxide film; a high-concentration source region of a second conductivity type formed adjacent to the gate electrode; A second electrode formed at a position separated from the gate electrode;
In a semiconductor device having a high-concentration drain region of a conductivity type and a drift region of a second conductivity type formed so as to surround the drain region, the concentration of the drain region is increased to surround the vicinity of the high-concentration drain region. A second conductivity type impurity layer having a lower concentration than the drift region and a higher concentration than the drift region. 2. A gate electrode formed to extend from a first gate oxide film formed on a semiconductor layer of a first conductivity type to a second gate oxide film, and to be adjacent to the gate electrode. A source region of the second conductivity type formed, a drain region of the second conductivity type formed at a position separated from the gate electrode, and a drift region of the second conductivity type formed so as to surround the drain region A second conductivity type impurity layer having a concentration lower than the concentration of the drain region and higher than the concentration of the drift region is formed so as to surround the vicinity of the high concentration drain region. Characteristic semiconductor device. 3. The device according to claim 1, wherein the second conductivity type impurity layer is formed so as to be adjacent to at least one end of the drain region from one end of the drain region. 13. The semiconductor device according to claim 1. 4. The second conductivity type impurity layer is formed substantially uniformly so as to surround the vicinity of the drain region so as to be adjacent to one end of the gate electrode via the first gate oxide film. 3. The semiconductor device according to claim 2, wherein: 5. A step of forming a gate electrode on a semiconductor layer of a first conductivity type via a gate oxide film, forming a high-concentration source region of a second conductivity type adjacent to the gate electrode, and A method of manufacturing a semiconductor device, comprising: a step of forming a second-conductivity-type high-concentration drain region at a position separated from a gate electrode; and a step of forming a second-conductivity-type drift region so as to surround the drain region. Forming a second conductivity type impurity layer having a lower concentration than the drain region and a higher concentration than the drift region so as to surround the vicinity of the high concentration drain region. Device manufacturing method. 6. A first implantation layer is formed by ion-implanting a second conductivity type impurity into a first conductivity type semiconductor layer, and the first implantation layer is diffused to form a first second conductivity type layer. A step of ion-implanting a second conductivity type impurity into the second conductivity type layer to form a second implanted layer; and a step of forming an oxidation resistant film in a predetermined region on the semiconductor layer. After a resist film is formed in a predetermined region on the semiconductor layer including the oxidation-resistant film, a first conductivity type impurity is ion-implanted using the oxidation-resistant film and the resist film as a mask, and a predetermined region on the semiconductor layer is formed. Forming a third implantation layer, and after removing the resist film, LOCOS-oxidize the semiconductor layer using the oxidation-resistant film as a mask to form a selective oxide film and an element isolation film, 3 by diffusing impurities in the injection layer. Forming a layer and a first conductivity type layer; thermally oxidizing the semiconductor layer using the selective oxide film and the element isolation film as a mask to form a gate oxide film; Forming a gate electrode so as to straddle over the gate electrode; and ion-implanting a second conductivity type impurity using the gate electrode and the selective oxide film as a mask to form a second conductivity type source region adjacent to the gate electrode. Forming a second conductivity type drain region at a position separated from the gate electrode. 7. The step of forming the second conductivity type impurity layer comprises:
7. The method according to claim 5, wherein the step is the same as the step of forming a second-conductivity-type channel stopper layer under an element isolation film formed between the first-conductivity-type MOS transistor and the first transistor. 13. The method for manufacturing a semiconductor device according to item 5.