JPH06160902A - Liquid crystal display - Google Patents
Liquid crystal displayInfo
- Publication number
- JPH06160902A JPH06160902A JP31221492A JP31221492A JPH06160902A JP H06160902 A JPH06160902 A JP H06160902A JP 31221492 A JP31221492 A JP 31221492A JP 31221492 A JP31221492 A JP 31221492A JP H06160902 A JPH06160902 A JP H06160902A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- liquid crystal
- crystal display
- display device
- pixel electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 21
- 238000003860 storage Methods 0.000 claims abstract description 18
- 239000003990 capacitor Substances 0.000 claims abstract description 13
- 239000010408 film Substances 0.000 claims description 78
- 229920001721 polyimide Polymers 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 239000011159 matrix material Substances 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 239000011229 interlayer Substances 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 13
- 238000000034 method Methods 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
Abstract
(57)【要約】
【目的】大きな開口率と、大きな保持容量を持つ、優れ
た画質の液晶表示装置を提供する。
【構成】本発明は、信号線上に絶縁膜を形成し、その上
に画素電極を設ける構造の液晶表示装置に於て、少なく
とも前記走査線上に形成された絶縁膜の一部をエッチン
グする事により、開口率の向上できるメリットを維持し
たまま、且つ製造工程を大幅に増加させる事なく充分な
保持容量の形成を可能ならしめるものである。
(57) [Abstract] [Purpose] To provide a liquid crystal display device having a large aperture ratio and a large storage capacity and excellent image quality. According to the present invention, in a liquid crystal display device having a structure in which an insulating film is formed on a signal line and a pixel electrode is provided thereon, at least a part of the insulating film formed on the scanning line is etched. It is possible to form a sufficient storage capacitor while maintaining the merit of improving the aperture ratio and without significantly increasing the manufacturing process.
Description
【０００１】[0001]
【産業上の利用分野】本発明は表示装置、特にアクティ
ブマトリクス型の液晶ディスプレイに関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to an active matrix type liquid crystal display.
【０００２】[0002]
【従来の技術】従来、２枚の基板間に液晶を挟持し、少
なくとも一方の基板上にスイッチング素子を形成したア
クティブマトリクス液晶表示装置の一画素部分は、たと
えば図１、及び図１のＸ−Ｘ’間に於ける断面図である
図２に示す様な構成となっている。ガラス、石英、サフ
ァイア等の基板１１上に不純物を添加した多結晶シリコ
ン等のＮ+ シリコン薄膜からなるソース領域１２・ドレ
イン領域１３が形成されている。これらのソース領域１
２・ドレイン領域１３の上側に接して、この両者を結ぶ
様に多結晶シリコン等のシリコン薄膜からなるチャネル
領域１４が設けられている。これら全体をシリコン酸化
膜等の絶縁膜から成るゲート絶縁膜１５が被覆してお
り、この上に金属、透明導電膜等から成るゲート電極、
兼走査線１６が形成されている。この上に、シリコン酸
化膜等の絶縁膜から成る層間絶縁膜１７が被膜してお
り、コンタクト・ホール１８を介して、金属、透明導電
膜等から成る信号線１９、同じく画素電極２０がソース
領域１２・ドレイン領域１３に各々接続されている。こ
の時、画素電極２０は前段の走査線に重なっており、保
持容量を形成している。この様に画素電極と信号線は同
一平面上に形成するのが一般的である。2. Description of the Related Art Conventionally, one pixel portion of an active matrix liquid crystal display device in which a liquid crystal is sandwiched between two substrates and a switching element is formed on at least one substrate is, for example, shown in FIGS. The structure is as shown in FIG. 2, which is a sectional view taken along the line X ′. On a substrate 11 made of glass, quartz, sapphire, or the like, a source region 12 and a drain region 13 made of N + silicon thin film made of doped polycrystalline silicon are formed. These source regions 1
2. A channel region 14 made of a silicon thin film such as polycrystalline silicon is provided so as to be in contact with the upper side of the drain region 13 and connect the two. A gate insulating film 15 made of an insulating film such as a silicon oxide film covers the entire surface of the gate insulating film 15.
Dual scanning lines 16 are formed. An interlayer insulating film 17 made of an insulating film such as a silicon oxide film is coated on this, and a signal line 19 made of a metal, a transparent conductive film, or the like and a pixel electrode 20 are also formed as source regions through a contact hole 18. 12 and the drain region 13, respectively. At this time, the pixel electrode 20 overlaps with the scanning line in the previous stage and forms a storage capacitor. In this way, the pixel electrode and the signal line are generally formed on the same plane.
【０００３】しかしこの場合、画素電極と信号線がショ
ートしない様に間隔をあけなければならず、開口率の低
下が問題となる。 その対策として、信号線を先に形成
し、その上に絶縁膜を堆積した後、画素電極を形成する
方法が提案されている。この方法を用いると、画素電極
を信号線上にまで延ばす事が出来るので、大幅な開口率
の向上が期待出来る。その一例を図３、及び図３のＸ−
Ｘ’間に於ける断面図である図４に示す。ガラス、石
英、サファイア等の基板３１上に不純物を添加した多結
晶シリコン等のＮ+ シリコン薄膜からなるソース領域３
２・ドレイン領域３３が形成されている。これらのソー
ス領域３２・ドレイン領域３３の上側に接して、この両
者を結ぶ様に多結晶シリコン等のシリコン薄膜からなる
チャネル領域３４が設けられている。これら全体をシリ
コン酸化膜等の絶縁膜から成るゲート絶縁膜３５が被覆
しており、この上に金属、透明導電膜等から成るゲート
電極、兼走査線３６が形成されている。この上に、シリ
コン酸化膜等の絶縁膜から成る層間絶縁膜３７が被膜し
ており、コンタクト・ホール３８を介して、金属、透明
導電膜等から成る信号線３９がソース領域３２と接続さ
れている。この上に、第二の層間絶縁膜４０が堆積さ
れ、第二のコンタクト・ホール４１を介して、画素電極
４２がドレイン領域３３と接続されている。この時、画
素電極２０は前段の走査線に重なって、保持容量を形成
すると共に、信号線上にも延びて開口率を向上させてい
る。信号線と画素電極を重ね合わせた場合、クロストー
クの発生が危惧されるが、信号線上に堆積する絶縁膜を
充分厚くする事で回避できる。その理由から、この絶縁
膜には、膜厚を厚くでき、また比較的誘電率の大きいポ
リイミドが用いられる。However, in this case, the pixel electrode and the signal line must be spaced apart from each other so as not to be short-circuited, and the reduction of the aperture ratio becomes a problem. As a countermeasure, there has been proposed a method of forming a signal line first, depositing an insulating film on the signal line, and then forming a pixel electrode. By using this method, the pixel electrode can be extended to above the signal line, so that a significant improvement in the aperture ratio can be expected. An example thereof is shown in FIG. 3 and X- in FIG.
It is shown in FIG. 4, which is a sectional view between X ′. Source region 3 made of N + silicon thin film such as polycrystalline silicon doped with impurities on substrate 31 such as glass, quartz, sapphire
2. A drain region 33 is formed. A channel region 34 made of a silicon thin film such as polycrystalline silicon is provided so as to be in contact with the upper side of the source region 32 and the drain region 33 so as to connect them. The whole is covered with a gate insulating film 35 made of an insulating film such as a silicon oxide film, and a gate electrode made of a metal, a transparent conductive film, etc. and a scanning line 36 are formed on the gate insulating film 35. An interlayer insulating film 37 made of an insulating film such as a silicon oxide film is coated on this, and a signal line 39 made of a metal, a transparent conductive film, or the like is connected to the source region 32 via a contact hole 38. There is. A second interlayer insulating film 40 is deposited on this, and the pixel electrode 42 is connected to the drain region 33 via the second contact hole 41. At this time, the pixel electrode 20 overlaps the scanning line in the previous stage to form a storage capacitor and also extends onto the signal line to improve the aperture ratio. When the signal line and the pixel electrode are overlapped with each other, the occurrence of crosstalk may occur, but this can be avoided by making the insulating film deposited on the signal line sufficiently thick. For that reason, a polyimide film having a relatively large dielectric constant can be used for this insulating film.
【０００４】[0004]
【発明が解決しようとする課題】しかし、従来技術には
以下に述べるような課題があった。即ち、図４に見る如
く、信号線上に絶縁膜を堆積する事で、走査線上には第
一の絶縁膜と第二の絶縁膜が形成される。従って、画素
電極と前段の走査線間で形成される保持容量は極めて小
さいものになってしまう。特に、第二の絶縁膜としてポ
リイミドを用いた場合は顕著である。これに対し、図
５、及び図５のＸ−Ｘ’間に於ける断面図である図６に
示す様に、保持容量を得る為に透明導電膜からなる電極
５１を設ける等の提案も成されているが、工程が大幅に
増加するので必ずしも良い方法とは言えない。However, the prior art has the following problems. That is, as shown in FIG. 4, by depositing an insulating film on the signal line, the first insulating film and the second insulating film are formed on the scanning line. Therefore, the storage capacitance formed between the pixel electrode and the preceding scanning line becomes extremely small. In particular, this is remarkable when polyimide is used as the second insulating film. On the other hand, as shown in FIG. 5 and FIG. 6 which is a cross-sectional view taken along line XX ′ of FIG. 5, it has been proposed to provide an electrode 51 made of a transparent conductive film in order to obtain storage capacitance. However, it is not always a good method because the number of steps is significantly increased.
【０００５】本発明は以上の様な問題点を解決するもの
であり、その目的とするところは信号線を先に形成し、
その上に絶縁膜を堆積した後、画素電極を形成する構造
を採用したとしても、製造工程を大幅に増加させる事な
く充分な保持容量を形成する方法を提案する事である。The present invention is intended to solve the above problems, and the purpose thereof is to form a signal line first,
Even if a structure in which a pixel electrode is formed after depositing an insulating film on it is adopted, a method of forming a sufficient storage capacitor without significantly increasing the manufacturing process is proposed.
【０００６】[0006]
【課題を解決するための手段】本発明は、信号線上に絶
縁膜を形成し、その上に画素電極を設ける構造の液晶表
示装置に於て、少なくとも前記走査線上に形成された絶
縁膜の一部をエッチングする事により、開口率の向上で
きるメリットを維持したまま、且つ製造工程を大幅に増
加させる事なく充分な保持容量の形成を可能ならしめる
ものである。According to the present invention, in a liquid crystal display device having a structure in which an insulating film is formed on a signal line and a pixel electrode is provided thereon, at least one of the insulating films formed on the scanning lines is provided. By etching the portion, it is possible to form a sufficient storage capacitor while maintaining the merit of improving the aperture ratio and without significantly increasing the manufacturing process.
【０００７】[0007]
【作用】走査線上に形成された絶縁膜の一部をエッチン
グする事により、前段の走査線と画素電極間で形成され
る容量を大きくできる。これにより、開口率が大きく出
来ると共に、充分大きな保持容量が得られる事で、優れ
た画質の液晶表示装置の実現が可能となった。By etching a part of the insulating film formed on the scanning line, the capacitance formed between the scanning line and the pixel electrode in the previous stage can be increased. As a result, the aperture ratio can be increased and a sufficiently large storage capacity can be obtained, so that a liquid crystal display device with excellent image quality can be realized.
【０００８】[0008]
（実施例１）図７は本発明の実施例を示す構造断面図で
ある。ガラス基板７０１上にＮ+ ポリシリコンからなる
ソース領域７０２・ドレイン領域７０３が形成され、こ
れらソース領域７０２・ドレイン領域７０３の上側に接
して、この両者を結ぶ様にポリシリコンからなるチャネ
ル領域７０４が設けられている。これら全体をシリコン
酸化膜から成るゲート絶縁膜７０５が被覆しており、こ
の上にゲート電極、兼走査線７０６が形成されている。(Embodiment 1) FIG. 7 is a structural sectional view showing an embodiment of the present invention. A source region 702 and a drain region 703 made of N + polysilicon are formed on a glass substrate 701, and a channel region 704 made of polysilicon is formed so as to be in contact with the upper side of the source region 702 and the drain region 703 and to connect them. It is provided. A gate insulating film 705 made of a silicon oxide film is entirely covered, and a gate electrode and a scanning line 706 are formed on the gate insulating film 705.
【０００９】この上に、シリコン酸化膜から成る層間絶
縁膜７０７が被膜しており、コンタクト・ホール７０８
を介して、アルミニウムから成る信号線７０９がソース
領域７０２と接続されている。この上に、ポリイミド膜
７１０が堆積されており、第二のコンタクト・ホール７
１１を介して、画素電極７１２がドレイン領域７０３と
接続されている。同時に、画素電極７１２は前段の走査
線に重なって保持容量が形成されるが、この時走査線上
に形成されたポリイミド膜は予め除去されており、保持
容量を構成しているキャパシタ絶縁膜はシリコン酸化膜
から成る層間絶縁膜７０７のみであり、これに依って充
分大きな保持容量が得られる。An interlayer insulating film 707 made of a silicon oxide film is coated on this, and a contact hole 708 is formed.
A signal line 709 made of aluminum is connected to the source region 702 via the. A polyimide film 710 is deposited on this, and the second contact hole 7 is formed.
The pixel electrode 712 is connected to the drain region 703 via 11. At the same time, the pixel electrode 712 overlaps the scanning line in the previous stage to form a storage capacitor. At this time, the polyimide film formed on the scanning line has been removed in advance, and the capacitor insulating film forming the storage capacitor is made of silicon. Only the interlayer insulating film 707 made of an oxide film is provided, and a sufficiently large storage capacity can be obtained by this.
【００１０】（実施例２）本発明は例えば図８の工程断
面図に示す方法により実現出来る。ガラス基板８０１上
に２０００Å程度のＮ+ ポリシリコンからなるソース領
域８０２・ドレイン領域８０３を形成し、これらソース
領域８０２・ドレイン領域８０３の上側に接して、この
両者を結ぶ様に２５０Å程度のポリシリコンからなるチ
ャネル領域８０４を設ける。これら全体を１２００Å程
度のシリコン酸化膜から成るゲート絶縁膜８０５で被覆
し、この上にクロム等からなるゲート電極、兼走査線８
０６を形成する（図８（ａ）参照）。(Embodiment 2) The present invention can be realized, for example, by the method shown in the process sectional view of FIG. A source region 802 and a drain region 803 made of N + polysilicon of about 2000 Å are formed on a glass substrate 801, and the source region 802 and the drain region 803 are in contact with the upper side of the source region 802 and the drain region 803, and about 250 Å polysilicon is formed so as to connect them. A channel region 804 is provided. The whole of these is covered with a gate insulating film 805 made of a silicon oxide film having a thickness of about 1200 Å, and a gate electrode made of chromium or the like and the scanning line 8 are formed on the gate insulating film 805.
06 is formed (see FIG. 8A).
【００１１】この上に、５０００Å程度のシリコン酸化
膜から成る層間絶縁膜８０７を堆積し、コンタクト・ホ
ール８０８を開口して、アルミニウムから成る信号線８
０９をソース領域８０２と接続する（図８（ｂ）参
照）。An interlayer insulating film 807 made of a silicon oxide film having a thickness of about 5000 Å is deposited thereon, a contact hole 808 is opened, and a signal line 8 made of aluminum is formed.
09 is connected to the source region 802 (see FIG. 8B).
【００１２】この上に、１μｍ程度のポリイミド膜８１
０を堆積した後、レジストパターン８１１を形成する。
このレジストパターン８１１を用いてポリイミド膜８１
０のエッチングを行なうが、実際にはレジストパターン
８１１形成時の現像工程において、ポリイミド膜８１０
もエッチングされる（図８（ｃ）参照）。On top of this, a polyimide film 81 having a thickness of about 1 μm is formed.
After 0 is deposited, a resist pattern 811 is formed.
Using this resist pattern 811, the polyimide film 81
Although the etching of 0 is performed, the polyimide film 810 is actually used in the developing process when forming the resist pattern 811.
Is also etched (see FIG. 8C).
【００１３】次に再度レジストパターン８１２を形成
し、これをマスクにシリコン酸化膜から成る層間絶縁膜
８０７をエッチングして、第二のコンタクト・ホール８
１３を開口する（図８（ｄ）参照）。Next, a resist pattern 812 is formed again, and using this as a mask, the interlayer insulating film 807 made of a silicon oxide film is etched to form the second contact hole 8
13 is opened (see FIG. 8D).
【００１４】最後に、画素電極８１４をドレイン領域８
０３と接続し、同時に、前段の走査線に重ねて保持容量
を形成する（図８（ｅ）参照）。Finally, the pixel electrode 814 is connected to the drain region 8
03, and at the same time, a storage capacitor is formed by overlapping with the previous scanning line (see FIG. 8E).
【００１５】（実施例３）本発明の他の実施例を図９の
工程断面図を用いて説明する。石英基板９０１上に１５
００Å程度のＰ+ ポリシリコンからなるソース領域９０
２・ドレイン領域９０３を形成し、これらソース領域９
０２・ドレイン領域９０３の上側に接して、この両者を
結ぶ様に５００Å程度のポリシリコンからなるチャネル
領域９０４を設ける。これら全体を１５００Å程度のシ
リコン酸化膜から成るゲート絶縁膜９０５で被覆し、こ
の上にタンタル等からなるゲート電極、兼走査線９０６
を形成する（図９（ａ）参照）。(Embodiment 3) Another embodiment of the present invention will be described with reference to process sectional views of FIGS. 15 on the quartz substrate 901
Source region 90 made of P + polysilicon of about 00Å
2. The drain region 903 is formed, and these source regions 9 are formed.
02. A channel region 904 made of polysilicon of about 500 Å is provided in contact with the upper side of the drain region 903 so as to connect them. The whole of these is covered with a gate insulating film 905 made of a silicon oxide film having a thickness of about 1500 Å, and a gate electrode made of tantalum or the like and a scanning line 906 are formed on the gate insulating film 905.
Are formed (see FIG. 9A).
【００１６】この上に、５０００Å程度のシリコン窒化
膜から成る層間絶縁膜９０７を堆積し、コンタクト・ホ
ール９０８を開口して、アルミニウムから成る信号線９
０９をソース領域９０２と接続する（図９（ｂ）参
照）。An interlayer insulating film 907 made of a silicon nitride film having a thickness of about 5000 Å is deposited thereon, a contact hole 908 is opened, and a signal line 9 made of aluminum is formed.
09 is connected to the source region 902 (see FIG. 9B).
【００１７】この上に、５０００Å程度のシリコン酸化
膜から成る第二の層間絶縁膜９１０を堆積し、レジスト
パターン９１１を形成する。このレジストパターン９１
１を用いて、例えば弗酸溶液等により第二の層間絶縁膜
９１０のエッチングを行なう（図９（ｃ）参照）。A second interlayer insulating film 910 made of a silicon oxide film having a thickness of about 5000 Å is deposited thereon, and a resist pattern 911 is formed. This resist pattern 91
1 is used to etch the second interlayer insulating film 910 with, for example, a hydrofluoric acid solution (see FIG. 9C).
【００１８】次に再度レジストパターン９１２を形成
し、これをマスクにシリコン窒化膜から成る層間絶縁膜
９０７をエッチングして、第二のコンタクト・ホール９
１３を開口する（図９（ｄ）参照）。Next, a resist pattern 912 is formed again, and the interlayer insulating film 907 made of a silicon nitride film is etched by using the resist pattern 912 as a mask, and the second contact hole 9 is formed.
13 is opened (see FIG. 9D).
【００１９】最後に、画素電極９１４をドレイン領域９
０３と接続し、同時に、前段の走査線に重ねて保持容量
を形成する（図９（ｅ）参照）。Finally, the pixel electrode 914 is connected to the drain region 9
03, and at the same time, a storage capacitor is formed by superimposing it on the preceding scanning line (see FIG. 9E).
【００２０】（実施例４）本発明の他の実施例を図１０
の工程断面図を用いて説明する。ガラス基板１００１上
に膜厚４００Å程度のＮ+ポリシリコンからなるソース
領域１００２・ドレイン領域１００３と、同様に膜厚４
００Å程度のポリシリコンからなるチャネル領域１００
４を設ける。これら全体を１０００Å程度のシリコン酸
化膜から成るゲート絶縁膜１００５で被覆し、この上に
タンタル等からなるゲート電極、兼走査線１００６を形
成する（図１０（ａ）参照）。(Embodiment 4) Another embodiment of the present invention is shown in FIG.
This will be described with reference to process sectional views. A source region 1002 and a drain region 1003 made of N + polysilicon having a film thickness of about 400 Å are formed on a glass substrate 1001, and a film thickness of 4 is similarly formed.
Channel region 100 made of polysilicon of about 00Å
4 is provided. The whole is covered with a gate insulating film 1005 made of a silicon oxide film of about 1000 liters, and a gate electrode made of tantalum or the like and a scanning line 1006 is formed on this (see FIG. 10A).
【００２１】この上に、５０００Å程度のシリコン酸化
膜から成る層間絶縁膜１００７を堆積し、コンタクト・
ホール１００８を開口して、アルミニウムから成る信号
線１００９をソース領域１００２と接続する。また同時
にドレイン電極１０１０も形成する（図１０（ｂ）参
照）。An interlayer insulating film 1007 made of a silicon oxide film having a thickness of about 5000Å is deposited on this, and a contact layer is formed.
The hole 1008 is opened to connect the signal line 1009 made of aluminum to the source region 1002. At the same time, a drain electrode 1010 is also formed (see FIG. 10B).
【００２２】この上に、１μｍ程度のポリイミド膜１０
１１を堆積した後、レジストパターン１０１２を形成す
る。このレジストパターン１０１２を用いてポリイミド
膜１０１１のエッチングを行なうが、実際にはレジスト
パターン１０１２形成時の現像工程において、ポリイミ
ド膜１０１１もエッチングされる。こうして第二のコン
タクト・ホール１０１３の開口と走査線１００６上のポ
リイミド膜１０１１のエッチングが終了する（図１０
（ｃ）参照）。On top of this, a polyimide film 10 having a thickness of about 1 μm is formed.
After depositing 11, a resist pattern 1012 is formed. The polyimide film 1011 is etched using the resist pattern 1012, but actually, the polyimide film 1011 is also etched in the developing step when the resist pattern 1012 is formed. In this way, the opening of the second contact hole 1013 and the etching of the polyimide film 1011 on the scanning line 1006 are completed (FIG. 10).
(See (c)).
【００２３】最後に、画素電極１０１４をドレイン電極
１０１０と接続し、同時に、前段の走査線に重ねて保持
容量を形成する（図１０（ｄ）参照）。Finally, the pixel electrode 1014 is connected to the drain electrode 1010, and at the same time, a storage capacitor is formed by superimposing it on the previous scanning line (see FIG. 10D).
【００２４】[0024]
【発明の効果】本発明を用いる事により、開口率が大き
く出来ると共に、充分大きな保持容量が得られる事で、
優れた画質の液晶表示装置の実現が可能となった。By using the present invention, the aperture ratio can be increased and a sufficiently large storage capacity can be obtained.
It has become possible to realize a liquid crystal display device with excellent image quality.
【図１】従来型のアクティブマトリクス液晶表示装置に
於ける一画素部分の例を表わす図。FIG. 1 is a diagram showing an example of a pixel portion in a conventional active matrix liquid crystal display device.
【図２】図１のＸ−Ｘ’間に於ける断面図。2 is a cross-sectional view taken along line X-X 'in FIG.
【図３】従来型のアクティブマトリクス液晶表示装置に
於ける一画素部分の他の例を表わす図。FIG. 3 is a diagram showing another example of a pixel portion in a conventional active matrix liquid crystal display device.
【図４】図３のＸ−Ｘ’間に於ける断面図。4 is a cross-sectional view taken along line X-X 'in FIG.
【図５】従来型のアクティブマトリクス液晶表示装置に
於ける一画素部分の他の例を表わす図。FIG. 5 is a diagram showing another example of a pixel portion in a conventional active matrix liquid crystal display device.
【図６】図５のＸ−Ｘ’間に於ける断面図。6 is a cross-sectional view taken along line X-X ′ in FIG.
【図７】本発明の実施例を示す構造断面図。FIG. 7 is a structural cross-sectional view showing an embodiment of the present invention.
【図８】本発明の実施例を実現する為の工程断面図。FIG. 8 is a process sectional view for realizing an embodiment of the present invention.
【図９】本発明を実現する為の他の実指例の工程断面
図。FIG. 9 is a process cross-sectional view of another actual example for realizing the present invention.
【図１０】本発明を実現する為の他の実施例の工程断面
図。FIG. 10 is a process sectional view of another embodiment for realizing the present invention.
１１，３１，７０１，８０１，９０１，１００１・・・
基板 １２，３２，７０２，８０２，９０２，１００２・・・
ソース領域 １３，３３，７０３，８０３，９０３，１００３・・・
ドレイン領域 １４，３４，７０４，８０４，９０４，１００４・・・
チャネル領域 １５，３５，７０５，８０５，９０５，１００５・・・
ゲート絶縁膜 １６，３６，７０６，８０６，９０６，１００６・・・
ゲート電極及び走査線 １７，３７，７０７，８０７，９０７，１００７・・・
層間絶縁膜 １８，３８，７０８，８０８，９０８，１００８・・・
コンタクト・ホール １９，３９，７０９，８０９，９０９，１００９・・・
信号線 ７１０，８１０，１０１１・・・ポリイミド膜 ２０，４２，７１２，８１４，９１４，１０１４・・・
画素電極 ４０，９１０・・・第二の層間絶縁膜 ４１，７１１，８１３，９１３，１０１３・・・第二の
コンタクト・ホール ５１・・・透明導電膜からなる保持容量形成の為の電極 ８１１，８１２，９１１，９１２，１０１２・・・レジ
ストパターン １０１０・・・ドレイン電極11, 31, 701, 801, 901, 1001 ...
Substrate 12, 32, 702, 802, 902, 1002 ...
Source regions 13, 33, 703, 803, 903, 1003 ...
Drain regions 14, 34, 704, 804, 904, 1004 ...
Channel regions 15, 35, 705, 805, 905, 1005 ...
Gate insulating film 16, 36, 706, 806, 906, 1006 ...
Gate electrode and scanning line 17,37,707,807,907,1007 ...
Interlayer insulating film 18, 38, 708, 808, 908, 1008 ...
Contact holes 19, 39, 709, 809, 909, 1009 ...
Signal lines 710, 810, 1011 ... Polyimide film 20, 42, 712, 814, 914, 1014 ...
Pixel electrodes 40,910 ... Second interlayer insulating film 41, 711, 813, 913, 1013 ... Second contact hole 51 ... Electrode 811 for forming a storage capacitor made of a transparent conductive film 811, 812, 911, 912, 1012 ... Resist pattern 1010 ... Drain electrode
Claims (8)
と、第一の絶縁膜を介して前記走査線上に形成され、且
つ前記走査線と直交して平行に配置された複数の信号線
と、前記走査線と前記信号線の各交点に、前記信号線と
接続されたソース領域、前記走査線と接続されたゲート
電極、ドレイン領域を具備した薄膜トランジスタが配置
され、また個々の前記ドレイン領域には、第二の絶縁膜
を介し前記信号線上に形成された画素電極が接続されて
いるアクティブ・マトリックス型液晶表示装置に於て、
前記画素電極と前段の走査線との間で保持容量が形成さ
れている事を特徴とする液晶表示装置。1. A plurality of scanning lines arranged in parallel on a substrate, and a plurality of signals formed on the scanning lines via a first insulating film and arranged in parallel orthogonal to the scanning lines. And a thin film transistor having a source region connected to the signal line, a gate electrode connected to the scanning line, and a drain region is arranged at each intersection of a line and the scanning line and the signal line, and each drain is provided. In an active matrix type liquid crystal display device in which a pixel electrode formed on the signal line is connected to a region through a second insulating film,
A liquid crystal display device, wherein a storage capacitor is formed between the pixel electrode and the scanning line in the preceding stage.
査線上に形成された領域の一部はエッチングされている
事を特徴とする請求項１記載の液晶表示装置。2. The liquid crystal display device according to claim 1, wherein at least a part of a region formed on the scanning line in the second insulating film is etched.
異なる材料からなる事を特徴とする請求項１記載の液晶
表示装置。3. The liquid crystal display device according to claim 1, wherein the first insulating film and the second insulating film are made of different materials.
を特徴とする請求項１記載の液晶表示装置。4. The liquid crystal display device according to claim 1, wherein the second insulating film is an organic insulating film.
事を特徴とする請求項１記載の液晶表示装置。5. The liquid crystal display device according to claim 1, wherein the second insulating film is a polyimide film.
素電極と前記ドレイン領域とを接続する為のコンタクト
・ホール開口の為のエッチングと同時になされる事を特
徴とする請求項１記載の液晶表示装置。6. The etching according to claim 1, wherein the etching of the second insulating film is performed simultaneously with the etching for opening a contact hole for connecting the pixel electrode and the drain region. Liquid crystal display device.
エッチングに用いられるエッチャントに対し充分な選択
比を持つ材料である事を特徴とする請求項１記載の液晶
表示装置。7. The liquid crystal display device according to claim 1, wherein the first insulating film is a material having a sufficient selection ratio with respect to an etchant used for etching the second insulating film.
形成された画素電極との接続は、前記第一の絶縁膜上に
形成されたドレイン電極を介して行なわれている事を特
徴とする請求項１記載の液晶表示装置。8. The connection between the drain region and the pixel electrode formed on the second insulating film is performed via the drain electrode formed on the first insulating film. The liquid crystal display device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31221492A JP3084981B2 (en) | 1992-11-20 | 1992-11-20 | Liquid crystal display device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31221492A JP3084981B2 (en) | 1992-11-20 | 1992-11-20 | Liquid crystal display device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06160902A true JPH06160902A (en) | 1994-06-07 |
| JP3084981B2 JP3084981B2 (en) | 2000-09-04 |
Family
ID=18026570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31221492A Expired - Lifetime JP3084981B2 (en) | 1992-11-20 | 1992-11-20 | Liquid crystal display device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3084981B2 (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1010583A (en) * | 1996-04-22 | 1998-01-16 | Sharp Corp | Method of manufacturing active matrix substrate and active matrix substrate thereof |
| JP2001290172A (en) * | 1995-08-11 | 2001-10-19 | Sharp Corp | Liquid crystal display |
| US6404474B1 (en) | 1998-07-24 | 2002-06-11 | Nec Corporation | Horizontal electric field LCD with increased capacitance between pixel and common electrodes |
| JP2002189232A (en) * | 1995-08-11 | 2002-07-05 | Sharp Corp | Liquid crystal display device and active matrix substrate |
| JP2007279753A (en) * | 2007-04-24 | 2007-10-25 | Semiconductor Energy Lab Co Ltd | Method for manufacturing active matrix type display device |
| JP2008275937A (en) * | 2007-04-27 | 2008-11-13 | Mitsubishi Electric Corp | Thin film transistor array substrate, manufacturing method thereof, and display device |
| JP2009192872A (en) * | 2008-02-15 | 2009-08-27 | Seiko Epson Corp | ELECTRO-OPTICAL DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE |
| US7973905B2 (en) | 1996-11-26 | 2011-07-05 | Samsung Electronics Co., Ltd. | Liquid crystal displays using organic insulating material and manufacturing methods thereof |
| JP2011158923A (en) * | 2011-05-11 | 2011-08-18 | Semiconductor Energy Lab Co Ltd | Display device |
| US8304769B2 (en) | 2006-03-15 | 2012-11-06 | Sharp Kabushiki Kaisha | Active matrix substrate having channel protection film covering transistor channel, and display apparatus and/or, television receiver including same |
| CN103299136A (en) * | 2011-01-11 | 2013-09-11 | 夏普株式会社 | Filter holding device, filter cleaning device, and air conditioner |
| WO2019186339A1 (en) * | 2018-03-30 | 2019-10-03 | 株式会社半導体エネルギー研究所 | Display device |
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1992
- 1992-11-20 JP JP31221492A patent/JP3084981B2/en not_active Expired - Lifetime
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001290172A (en) * | 1995-08-11 | 2001-10-19 | Sharp Corp | Liquid crystal display |
| JP2002189232A (en) * | 1995-08-11 | 2002-07-05 | Sharp Corp | Liquid crystal display device and active matrix substrate |
| JPH1010583A (en) * | 1996-04-22 | 1998-01-16 | Sharp Corp | Method of manufacturing active matrix substrate and active matrix substrate thereof |
| US7973905B2 (en) | 1996-11-26 | 2011-07-05 | Samsung Electronics Co., Ltd. | Liquid crystal displays using organic insulating material and manufacturing methods thereof |
| US6404474B1 (en) | 1998-07-24 | 2002-06-11 | Nec Corporation | Horizontal electric field LCD with increased capacitance between pixel and common electrodes |
| US8304769B2 (en) | 2006-03-15 | 2012-11-06 | Sharp Kabushiki Kaisha | Active matrix substrate having channel protection film covering transistor channel, and display apparatus and/or, television receiver including same |
| JP2007279753A (en) * | 2007-04-24 | 2007-10-25 | Semiconductor Energy Lab Co Ltd | Method for manufacturing active matrix type display device |
| JP2008275937A (en) * | 2007-04-27 | 2008-11-13 | Mitsubishi Electric Corp | Thin film transistor array substrate, manufacturing method thereof, and display device |
| JP2009192872A (en) * | 2008-02-15 | 2009-08-27 | Seiko Epson Corp | ELECTRO-OPTICAL DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE |
| CN103299136A (en) * | 2011-01-11 | 2013-09-11 | 夏普株式会社 | Filter holding device, filter cleaning device, and air conditioner |
| JP2011158923A (en) * | 2011-05-11 | 2011-08-18 | Semiconductor Energy Lab Co Ltd | Display device |
| WO2019186339A1 (en) * | 2018-03-30 | 2019-10-03 | 株式会社半導体エネルギー研究所 | Display device |
| US11513409B2 (en) | 2018-03-30 | 2022-11-29 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| US12461418B2 (en) | 2018-03-30 | 2025-11-04 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
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