JPH06160875A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
- Publication number
- JPH06160875A JPH06160875A JP4312205A JP31220592A JPH06160875A JP H06160875 A JPH06160875 A JP H06160875A JP 4312205 A JP4312205 A JP 4312205A JP 31220592 A JP31220592 A JP 31220592A JP H06160875 A JPH06160875 A JP H06160875A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- liquid crystal
- crystal display
- display device
- pixel electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 17
- 239000010408 film Substances 0.000 claims description 47
- 229920001721 polyimide Polymers 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- 239000010409 thin film Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
Abstract
(57)【要約】
【目的】大きな開口率を持つ、優れた画質の液晶表示装
置を提供する。
【構成】本発明は、隣合う画素電極を異なる平面上に別
々に形成する事で、画素電極間のスペースを小さく、或
は無くし、これに依って、開口率の向上を可能ならしめ
るものである。
(57) [Abstract] [Purpose] To provide a liquid crystal display device having a large aperture ratio and excellent image quality. According to the present invention, adjacent pixel electrodes are separately formed on different planes to reduce or eliminate the space between the pixel electrodes, thereby improving the aperture ratio. is there.
Description
【０００１】[0001]
【産業上の利用分野】本発明は表示装置、特にアクティ
ブマトリクス型の液晶ディスプレイに関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to an active matrix type liquid crystal display.
【０００２】[0002]
【従来の技術】従来、２枚の基板間に液晶を挟持し、少
なくとも一方の基板上にスイッチング素子を形成したア
クティブマトリクス液晶表示装置の一画素部分は、たと
えば図１、及び図１のＸ−Ｘ’間に於ける断面図である
図２に示す様な構成となっている。ガラス、石英、サフ
ァイア等の基板１１上に不純物を添加した多結晶シリコ
ン等のＮ+ シリコン薄膜からなるソース領域１２・ドレ
イン領域１３が形成されている。これらのソース領域１
２・ドレイン領域１３の上側に接して、この両者を結ぶ
様に多結晶シリコン等のシリコン薄膜からなるチャネル
領域１４が設けられている。これら全体をシリコン酸化
膜等の絶縁膜から成るゲート絶縁膜１５が被覆してお
り、この上に金属、透明導電膜等から成るゲート電極、
兼走査線１６が形成されている。この上に、シリコン酸
化膜等の絶縁膜から成る層間絶縁膜１７が被膜してお
り、コンタクト・ホール１８を介して、金属、透明導電
膜等から成る信号線１９、同じく画素電極２０がソース
領域１２・ドレイン領域１３に各々接続されている。こ
の時、画素電極２０は前段の走査線に重なっており、保
持容量を形成している。この様に画素電極と信号線は同
一平面上に形成するのが一般的である。2. Description of the Related Art Conventionally, one pixel portion of an active matrix liquid crystal display device in which a liquid crystal is sandwiched between two substrates and a switching element is formed on at least one substrate is, for example, shown in FIGS. The structure is as shown in FIG. 2, which is a sectional view taken along the line X ′. On a substrate 11 made of glass, quartz, sapphire, or the like, a source region 12 and a drain region 13 made of N + silicon thin film made of doped polycrystalline silicon are formed. These source regions 1
2. A channel region 14 made of a silicon thin film such as polycrystalline silicon is provided so as to be in contact with the upper side of the drain region 13 and connect the two. A gate insulating film 15 made of an insulating film such as a silicon oxide film covers the entire surface of the gate insulating film 15.
Dual scanning lines 16 are formed. An interlayer insulating film 17 made of an insulating film such as a silicon oxide film is coated on this, and a signal line 19 made of a metal, a transparent conductive film, or the like and a pixel electrode 20 are also formed as source regions through a contact hole 18. 12 and the drain region 13, respectively. At this time, the pixel electrode 20 overlaps with the scanning line in the previous stage and forms a storage capacitor. In this way, the pixel electrode and the signal line are generally formed on the same plane.
【０００３】しかしこの場合、画素電極と信号線がショ
ートしない様に間隔をあけなければならず、開口率の低
下が問題となる。 その対策として、信号線を先に形成
し、その上に絶縁膜を堆積した後、画素電極を形成する
方法が提案されている。この方法を用いると、画素電極
を信号線上にまで延ばす事が出来るので、大幅な開口率
の向上が期待出来る。その一例を図３、及び図３のＸ−
Ｘ’間に於ける断面図である図４に示す。ガラス、石
英、サファイア等の基板３１上に不純物を添加した多結
晶シリコン等のＮ+ シリコン薄膜からなるソース領域３
２・ドレイン領域３３が形成されている。これらのソー
ス領域３２・ドレイン領域３３の上側に接して、この両
者を結ぶ様に多結晶シリコン等のシリコン薄膜からなる
チャネル領域３４が設けられている。これら全体をシリ
コン酸化膜等の絶縁膜から成るゲート絶縁膜３５が被覆
しており、この上に金属、透明導電膜等から成るゲート
電極、兼走査線３６が形成されている。この上に、シリ
コン酸化膜等の絶縁膜から成る層間絶縁膜３７が被膜し
ており、コンタクト・ホール３８を介して、金属、透明
導電膜等から成る信号線３９がソース領域３２と接続さ
れている。この上に、第二の層間絶縁膜４０が堆積さ
れ、第二のコンタクト・ホール４１を介して、画素電極
４２がドレイン領域３３と接続されている。この時、画
素電極２０は前段の走査線に重なって、保持容量を形成
すると共に、信号線上にも延びて開口率を向上させてい
る。信号線と画素電極を重ね合わせた場合、クロストー
クの発生が危惧されるが、信号線上に堆積する絶縁膜を
充分厚くする事で回避できる。その理由から、この絶縁
膜には、膜厚を厚くでき、また比較的誘電率の小さいポ
リイミドが用いられる。However, in this case, the pixel electrode and the signal line must be spaced apart from each other so as not to be short-circuited, and the reduction of the aperture ratio becomes a problem. As a countermeasure, there has been proposed a method of forming a signal line first, depositing an insulating film on the signal line, and then forming a pixel electrode. By using this method, the pixel electrode can be extended to above the signal line, so that a significant improvement in the aperture ratio can be expected. An example thereof is shown in FIG. 3 and X- in FIG.
It is shown in FIG. 4, which is a sectional view between X ′. Source region 3 made of N + silicon thin film such as polycrystalline silicon doped with impurities on substrate 31 such as glass, quartz, sapphire
2. A drain region 33 is formed. A channel region 34 made of a silicon thin film such as polycrystalline silicon is provided so as to be in contact with the upper side of the source region 32 and the drain region 33 so as to connect them. The whole is covered with a gate insulating film 35 made of an insulating film such as a silicon oxide film, and a gate electrode made of a metal, a transparent conductive film, etc. and a scanning line 36 are formed on the gate insulating film 35. An interlayer insulating film 37 made of an insulating film such as a silicon oxide film is coated on this, and a signal line 39 made of a metal, a transparent conductive film, or the like is connected to the source region 32 via a contact hole 38. There is. A second interlayer insulating film 40 is deposited on this, and the pixel electrode 42 is connected to the drain region 33 via the second contact hole 41. At this time, the pixel electrode 20 overlaps the scanning line in the previous stage to form a storage capacitor and also extends onto the signal line to improve the aperture ratio. When the signal line and the pixel electrode are overlapped with each other, the occurrence of crosstalk may occur, but this can be avoided by making the insulating film deposited on the signal line sufficiently thick. For that reason, a polyimide film having a relatively small dielectric constant can be used for this insulating film.
【０００４】[0004]
【発明が解決しようとする課題】しかし、画素電極を信
号線や走査線上に延ばす事で開口率は向上するものの、
その効果には限界がある。即ち、従来の技術では全ての
画素電極を同時に形成する為、画素電極と、それと隣合
う画素電極の間には必然的にスペースが生じる。このス
ペースは、マスク設計の際のデザイン・ルールで決定さ
れ、このスペースが大きい程開口率が低下する。However, although the aperture ratio is improved by extending the pixel electrode on the signal line or the scanning line,
There is a limit to the effect. That is, in the conventional technique, since all pixel electrodes are formed at the same time, a space is inevitably formed between the pixel electrode and the pixel electrode adjacent to it. This space is determined by a design rule at the time of mask design, and the larger the space, the lower the aperture ratio.
【０００５】本発明は以上の様な問題点を解決するもの
であり、その目的とするところは、画素電極間のスペー
スを小さく、或は無くす方法を提案する事である。The present invention is intended to solve the above problems, and an object thereof is to propose a method for reducing or eliminating the space between pixel electrodes.
【０００６】[0006]
【課題を解決するための手段】本発明は、隣合う画素電
極を異なる平面上に別々に形成する事で、画素電極間の
スペースを小さく、或は無くし、これに依って、開口率
の向上を可能ならしめるものである。According to the present invention, by forming adjacent pixel electrodes separately on different planes, the space between the pixel electrodes is reduced or eliminated, thereby improving the aperture ratio. Is what makes it possible.
【０００７】[0007]
【作用】少なくとも隣合う画素電極を別々の工程で、且
つ別平面上に形成しする事で、画素電極間のスペースを
小さく、或は全く無くす事が出来る。これにより開口率
の増大が可能となり、優れた画質の液晶表示装置の実現
が可能となった。By at least forming adjacent pixel electrodes in separate steps and on different planes, the space between the pixel electrodes can be reduced or eliminated altogether. As a result, the aperture ratio can be increased and a liquid crystal display device with excellent image quality can be realized.
【０００８】[0008]
（実施例１）図５は本発明の実施例を示す構造断面図で
ある。ガラス基板５０１上にＮ+ ポリシリコンからなる
ソース領域５０２・ドレイン領域５０３が形成され、こ
れらソース領域５０２・ドレイン領域５０３の上側に接
して、この両者を結ぶ様にポリシリコンからなるチャネ
ル領域５０４が設けられている。これら全体をシリコン
酸化膜から成るゲート絶縁膜５０５が被覆しており、こ
の上にゲート電極、兼走査線５０６が形成されている。(Embodiment 1) FIG. 5 is a structural sectional view showing an embodiment of the present invention. A source region 502 and a drain region 503 made of N + polysilicon are formed on a glass substrate 501, and a channel region 504 made of polysilicon is formed so as to be in contact with the upper side of the source region 502 and the drain region 503 so as to connect them. It is provided. A gate insulating film 505 made of a silicon oxide film is entirely covered, and a gate electrode and a scanning line 506 are formed on the gate insulating film 505.
【０００９】この上に、シリコン酸化膜から成る層間絶
縁膜５０７が被膜しており、コンタクト・ホール５０８
を介して、アルミニウムから成る信号線５０９がソース
領域５０２と接続されている。この上に、ポリイミド膜
５１０が堆積されており、第二のコンタクト・ホール５
１１を介して、第一の画素電極５１２がドレイン領域５
０３と接続されている。同時に、この第一の画素電極５
１２は信号線５０９に重なっている。更にこの上に、第
二のポリイミド膜５１３が堆積されており、第三のコン
タクト・ホール５１４を介して、第二の画素電極５１５
がドレイン領域５０３と接続されている。同時に、この
第二の画素電極５１５は信号線５０９と、隣合う第一の
画素電極５１２に重なっている。An interlayer insulating film 507 made of a silicon oxide film is coated on this, and a contact hole 508 is formed.
A signal line 509 made of aluminum is connected to the source region 502 via the. A polyimide film 510 is deposited on the second contact hole 5
11 through the first pixel electrode 512 to the drain region 5
It is connected with 03. At the same time, this first pixel electrode 5
12 is overlapped with the signal line 509. Further thereon, a second polyimide film 513 is deposited, and a second pixel electrode 515 is formed through the third contact hole 514.
Are connected to the drain region 503. At the same time, the second pixel electrode 515 overlaps the signal line 509 and the adjacent first pixel electrode 512.
【００１０】（実施例２）図６は本発明の他の実施例を
示す構造断面図である。ガラス基板６０１上に、Ｎ+ ポ
リシリコンからなるソース領域６０２・ドレイン領域６
０３が形成され、これらソース領域６０２・ドレイン領
域６０３に接して、この両者を結ぶ様にポリシリコンか
らなるチャネル領域６０４が設けられている。これら全
体をシリコン酸化膜から成るゲート絶縁膜６０５が被覆
しており、この上にゲート電極、兼走査線６０６が形成
されている。(Embodiment 2) FIG. 6 is a structural sectional view showing another embodiment of the present invention. A source region 602 and a drain region 6 made of N + polysilicon are formed on a glass substrate 601.
03 is formed, and a channel region 604 made of polysilicon is provided so as to be in contact with the source region 602 and the drain region 603 and connect the two. A gate insulating film 605 made of a silicon oxide film is entirely covered, and a gate electrode and a scanning line 606 are formed on the gate insulating film 605.
【００１１】この上に、シリコン酸化膜から成る層間絶
縁膜６０７が被膜しており、コンタクト・ホール６０８
を介して、アルミニウムから成る信号線６０９がソース
領域６０２と接続されている。この上に、ポリイミド膜
６１０が堆積されており、第二のコンタクト・ホール６
１１を介して、第一の画素電極６１２がドレイン領域６
０３と接続されている。同時に、この第一の画素電極６
１２は信号線６０９に重なっている。更にこの上に、第
二のポリイミド膜６１３が堆積されており、第三のコン
タクト・ホール６１４を介して、第二の画素電極６１５
がドレイン領域６０３と接続されている。同時に、この
第二の画素電極６１５は信号線６０９と重なっている。
また、図示しないが、この第二の画素電極６１５は走査
線６０６とも重なっていて、信号線６０９、走査線６０
６は、遮光膜の役割も兼ねている。An interlayer insulating film 607 made of a silicon oxide film is coated on this, and a contact hole 608 is formed.
A signal line 609 made of aluminum is connected to the source region 602 via the. A polyimide film 610 is deposited on this, and the second contact hole 6
11 through the first pixel electrode 612 to the drain region 6
It is connected with 03. At the same time, this first pixel electrode 6
12 is overlapped with the signal line 609. A second polyimide film 613 is further deposited thereon, and a second pixel electrode 615 is formed through a third contact hole 614.
Are connected to the drain region 603. At the same time, the second pixel electrode 615 overlaps the signal line 609.
Although not shown, the second pixel electrode 615 also overlaps with the scanning line 606, and thus the signal line 609 and the scanning line 60.
6 also serves as a light shielding film.
【００１２】以上、本発明を実現する為の実施例の一例
を説明した。ここでは信号線上に形成する絶縁膜や、画
素電極間に形成する絶縁膜として、ポリイミド膜を用い
ているが、それ以外に例えばシリコン酸化膜等であって
も本発明の主旨を逸しない。An example of the embodiment for realizing the present invention has been described above. Here, a polyimide film is used as the insulating film formed on the signal line and the insulating film formed between the pixel electrodes, but other than that, for example, a silicon oxide film or the like does not deviate from the gist of the present invention.
【００１３】[0013]
【発明の効果】本発明を用いる事により、開口率が大き
く出来、優れた画質の液晶表示装置の実現が可能となっ
た。By using the present invention, the aperture ratio can be increased and a liquid crystal display device with excellent image quality can be realized.
【図１】従来型のアクティブマトリクス液晶表示装置に
於ける一画素部分の例を示す図である。FIG. 1 is a diagram showing an example of a pixel portion in a conventional active matrix liquid crystal display device.
【図２】図１のＸ−Ｘ’間に於ける断面図である。FIG. 2 is a cross-sectional view taken along line X-X ′ in FIG.
【図３】従来型のアクティブマトリクス液晶表示装置に
於ける一画素部分の他の例を示す図である。FIG. 3 is a diagram showing another example of one pixel portion in a conventional active matrix liquid crystal display device.
【図４】図３のＸ−Ｘ’間に於ける断面図である。FIG. 4 is a cross-sectional view taken along line X-X ′ in FIG.
【図５】本発明の実施例を示す構造断面図である。FIG. 5 is a structural sectional view showing an embodiment of the present invention.
【図６】本発明の実施例を実現する為の工程断面図であ
る。FIG. 6 is a process sectional view for realizing an embodiment of the present invention.
１１，３１，５０１，６０１・・・基板 １２，３２，５０２，６０２・・・ソース領域 １３，３３，５０３，６０３・・・ドレイン領域 １４，３４，５０４，６０４・・・チャネル領域 １５，３５，５０５，６０５・・・ゲート絶縁膜 １６，３６，５０６，６０６・・・ゲート電極及び走査
線 １７，３７，５０７，６０７・・・層間絶縁膜 １８，３８，５０８，６０８・・・コンタクト・ホール １９，３９，５０９，６０９・・・信号線 ５１０，６１０・・・ポリイミド膜 ２０，４２，５１２，６１２・・・画素電極 ４０・・・第二の層間絶縁膜 ４１，５１１，６１１・・・第二のコンタクト・ホール ５１５，６１５・・・第二の画素電極 ５１３，６１３・・・第二のポリイミド膜 ５１４，６１４・・・第三のコンタクト・ホール11, 31, 501, 601 ... Substrate 12, 32, 502, 602 ... Source region 13, 33, 503, 603 ... Drain region 14, 34, 504, 604 ... Channel region 15, 35 , 505, 605 ... Gate insulating film 16, 36, 506, 606 ... Gate electrode and scanning line 17, 37, 507, 607 ... Interlayer insulating film 18, 38, 508, 608 ... Contact Holes 19, 39, 509, 609 ... Signal lines 510, 610 ... Polyimide film 20, 42, 512, 612 ... Pixel electrode 40 ... Second interlayer insulating film 41, 511, 611 ... -Second contact holes 515, 615 ... Second pixel electrodes 513, 613 ... Second polyimide film 514, 614 ... Third contact holes
Claims (8)
と、前記走査線と直交して平行に配置された複数の信号
線と、前記走査線と前記信号線の各交点に対応して、前
記信号線と接続されたソース領域、前記走査線と接続さ
れたゲート電極、及びドレイン領域とこれに接続された
画素電極を具備した薄膜トランジスタが配置されたアク
ティブ・マトリックス型液晶表示装置に於て、前記画素
電極は隣合う前記画素電極とは、異なる平面上に形成さ
れている事を特徴とする液晶表示装置。1. Corresponding to a plurality of scanning lines arranged in parallel on a substrate, a plurality of signal lines arranged in parallel to each other at right angles to the scanning lines, and intersections of the scanning lines and the signal lines. And a thin film transistor having a source region connected to the signal line, a gate electrode connected to the scanning line, and a drain region and a pixel electrode connected to the drain region. The pixel electrode is formed on a plane different from that of the adjacent pixel electrode.
異なる平面上に形成されており、且つ第一の絶縁膜を介
して互いに重なり合っている事を特徴とする請求項１記
載の液晶表示装置。2. The pixel electrode is adjacent to the pixel electrode,
The liquid crystal display device according to claim 1, wherein the liquid crystal display devices are formed on different planes and overlap each other with a first insulating film interposed therebetween.
走査線上に形成されている事を特徴とする請求項１記載
の液晶表示装置。3. The liquid crystal display device according to claim 1, wherein the signal line is formed on the scanning line via a second insulating film.
記信号線上に形成されている事を特徴とする請求項１記
載の液晶表示装置。4. The liquid crystal display device according to claim 1, wherein the pixel electrode is formed on the signal line via a third insulating film.
を特徴とする請求項１記載の液晶表示装置。5. The liquid crystal display device according to claim 1, wherein the third insulating film is an organic insulating film.
事を特徴とする請求項１記載の液晶表示装置。6. The liquid crystal display device according to claim 1, wherein the third insulating film is a polyimide film.
を特徴とする請求項１記載の液晶表示装置。7. The liquid crystal display device according to claim 1, wherein the first insulating film is an organic insulating film.
事を特徴とする請求項１記載の液晶表示装置。8. The liquid crystal display device according to claim 1, wherein the first insulating film is a polyimide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31220592A JP3326832B2 (en) | 1992-11-20 | 1992-11-20 | Liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31220592A JP3326832B2 (en) | 1992-11-20 | 1992-11-20 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06160875A true JPH06160875A (en) | 1994-06-07 |
| JP3326832B2 JP3326832B2 (en) | 2002-09-24 |
Family
ID=18026474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31220592A Expired - Fee Related JP3326832B2 (en) | 1992-11-20 | 1992-11-20 | Liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3326832B2 (en) |
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