JP2002182245A - Active matrix substrate manufacturing method - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To increase a numerical aperture by securing a predetermined capacitance value required for an auxiliary capacitance without increasing the number of steps. SOLUTION: A step of forming a gate electrode of a TFT 52, a scanning wiring 54, and an auxiliary wiring 60 for providing an auxiliary capacitance 53 on a transparent insulating substrate 1, and an interlayer insulating film 4, a semiconductor layer 5 over the entire surface of the transparent insulating substrate 1. Forming the contact layer 6 sequentially, and the semiconductor layer 5 and the contact layer 6 in a predetermined region.
Etching the interlayer insulating film 4 on the patterned semiconductor layer 5 and the contact layer 6 using the resist pattern 11 as a mask, and forming the source and drain electrodes of the TFT 52 and the signal wiring 55 on the patterned semiconductor layer 5 and the contact layer 6. Forming,
Forming a pixel electrode 9 that is electrically connected to the drain electrode of the TFT 52.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing an active matrix substrate used for a liquid crystal display device,
In particular, in a liquid crystal display device capable of obtaining a high-quality display,
The present invention relates to a method for manufacturing an active matrix substrate using a thin film transistor as a switching element.

[0002]

2. Description of the Related Art In an active matrix type liquid crystal display device, a liquid crystal is provided between an active matrix substrate provided with pixel electrodes in a matrix and a counter substrate provided with counter electrodes facing all the pixel electrodes. The layers are arranged and configured. Switching elements such as thin film transistors (hereinafter, referred to as TFTs) are connected to the respective pixel electrodes of the active matrix substrate.

FIG. 6 (a) shows that a switching element T
FIG. 3 is a schematic plan view of one picture element in an active matrix substrate using FT. In this active matrix substrate, picture element electrodes 90 are formed in a matrix on a transparent insulating substrate. Around each pixel electrode 90, a pair of scanning wirings 54 and signal wirings 55 which are parallel to each other are formed so as to intersect with each other in an insulated state. TFTs 52 are provided, respectively. Each TFT 52 has a gate electrode connected to the scanning wiring 54, a source electrode connected to the signal wiring 55, and a drain electrode connected to the pixel electrode 90.

Under each pixel electrode 90, a scanning wiring 54 is provided.
Of the scan wiring 5 is widened to the pixel electrode 90 side.
By providing an insulating layer between the widened portion 53a of FIG. 4 and the pixel electrode 90, a capacitor portion having the auxiliary capacitance 53 is formed. FIG. 5 shows an equivalent circuit of one picture element in this case.
FIG. 6B shows an equivalent circuit of the active matrix substrate.
Shown in In the equivalent circuit of FIG. 6B, the gate electrode and the source electrode of the TFT 52 are connected to the scanning wiring 54 and the signal wiring 55, respectively. The drain electrode of the TFT 52 is connected to a pixel electrode 90 (see FIG. 6A), and a liquid crystal capacitor 51 and a pixel electrode 90 formed by a liquid crystal layer between the pixel electrode 90 and the counter electrode 56. A storage capacitor 53 formed by an insulating layer between the TFT 52 and the scanning wiring 54 is connected to the drain electrode of the TFT 52.

The TFT 52 is driven by applying a scanning voltage to a gate electrode from a scanning wiring (gate wiring) 54. If the TFT 52 is in the ON state, the signal wiring 5
5 is applied to the pixel electrode 90 via the drain electrode, and a charge is stored as a liquid crystal capacitor 51 in the liquid crystal layer between the pixel electrode 90 and the counter electrode 56. . After that, the application of the scanning voltage from the scanning wiring 54 of each row to the gate electrode of each TFT 52 is completed,
Each TFT 52 is turned off until a scanning voltage for applying a signal voltage to the next pixel electrode 90 is applied to the gate electrode.
In the F state, the charge accumulated by the signal voltage is held in the liquid crystal layer between the picture element electrode 90 and the counter electrode 56.

At this time, it is desirable that the voltage between the picture element electrode 90 and the counter electrode 56 does not fluctuate. Since the liquid crystal layer operates as a capacitor having the liquid crystal capacitance 51, the liquid crystal layer can hold the accumulated charge. However, since the capacitance value of the liquid crystal layer is small, the writing (holding) operation of the image signal is insufficient with the liquid crystal layer alone. The liquid crystal capacity 5 of the liquid crystal layer may be reduced.
In order to supplement the capacitance value of 1, a capacitor portion having an auxiliary capacitance 53 is provided in the region of the pixel electrode 90.

In the arrangement of the capacitor portion having the auxiliary capacitance 53 shown in FIG. 6A, the aperture ratio can be increased, but the widened portion 53a is provided in the scanning wiring 54 adjacent in the row direction to form the auxiliary capacitance 53. Therefore, interference between the gate signal of the scanning wiring 54 and the potential of the pixel electrode 90 or delay of the gate signal of the scanning wiring 54 occurs.

FIG. 7A is a schematic plan view of one picture element showing another example of an active matrix substrate provided with a capacitor portion having an auxiliary capacitance 53. FIG. Below the central portion of the pixel electrode 90, the auxiliary wiring 60 is provided in parallel with the scanning wiring 54.
Is formed, and an insulating layer is provided between the auxiliary wiring 60 and the picture element electrode 90 to form a capacitor section having an auxiliary capacitance 53. The configuration other than the capacitor unit having the auxiliary capacitance 53 is the same as the configuration of the active matrix substrate shown in FIG. FIG. 7B shows an equivalent circuit of each picture element on the active matrix substrate having the picture element configuration shown in FIG. In the equivalent circuit of FIG. 7B, auxiliary wirings 60 are provided in parallel with the respective scanning wirings 54, and a capacitor unit having an auxiliary capacitance 53 is connected to the picture element electrode 90 and the auxiliary wirings 60. Connections other than the auxiliary capacitance 53 are the same as the configuration of the equivalent circuit shown in FIG.

In the arrangement of the capacitor section having the auxiliary capacitance 53 shown in FIG. 7A, the auxiliary capacitance 53 is formed by providing the auxiliary wiring 60 at the center of the picture element electrode 90. Although not large, interference between the gate signal of the scanning wiring 54 and the potential of the pixel electrode 90 is reduced, and the quality of image display is improved.

Next, a method of manufacturing an active matrix substrate having an auxiliary capacitor 53 shown in FIG.
A description will be given based on (a) to (i). The left and right sides of each figure are cross-sectional views taken along the line AA ′ of FIG.
2 part) and BB ′ section (part of the auxiliary capacitance 53).

As shown in FIG. 8A, a metal such as Al, Cr, Ta, Ti or the like is formed on a transparent insulating substrate 19 such as glass by a sputtering method or the like. The gate electrode 20 having a trapezoidal cross section and the auxiliary wiring 60 having a trapezoidal cross section are formed together with the scanning wiring 54 (not shown).

Next, as shown in FIG. 8 (b), an Si film is formed so as to cover the gate electrode 20 and the auxiliary wiring 60.
N _X, an interlayer insulating film 40 such as SiO _2, TFT 52
A semiconductor layer 50 of amorphous silicon, polysilicon, or the like is formed on a part of the interlayer insulating film 40. Further, a contact layer 65 made of amorphous silicon, microcrystalline silicon, or the like doped with impurities such as phosphorus (P) is continuously formed on the semiconductor layer 50, and is patterned. After patterning, the semiconductor layer 50 and the contact layer 65 are removed by etching to form an island-shaped pattern in a predetermined region. At this time, the interlayer insulating film 40 is hardly etched.

Next, as shown in FIG.
A metal such as Al, Cr, Ta, or Ti is formed on the two portions of the contact layer 65 and the interlayer insulating film 40 by a sputtering method or the like, and the formed metal is patterned by performing photolithography and etching. Then, the source electrode 70 and the drain electrode 80 are formed separately from each other together with the signal wiring 55 (not shown).

Next, as shown in FIG.
A TO film is formed over the entire active matrix substrate 19 and patterned to form a pixel electrode 90 so as to be electrically connected to the drain electrode 80 in the TFT 52. As a result, an interlayer insulating film 40, which is a dielectric, is formed between the auxiliary wiring 60 and the pixel electrode 90.
The auxiliary capacitance 53 shown in FIG.

Next, as shown in FIG.
All of the contact layer 65 between the two portions of the source electrode 70 and the drain electrode 80 is partially removed by etching, and the channel region of the TFT 52 and the source electrode 70 and the drain electrode 80 are electrically separated. .

Next, as shown in FIG.
Passivation film 100 made of SiN _X or the like in two parts
Is formed and patterned. Thereby, an active matrix substrate used for a liquid crystal display device is obtained.

[0017]

In the active matrix substrate, it is necessary to increase the aperture ratio in order to increase the brightness and contrast of the liquid crystal display device. When the area of the pixel electrode is reduced, in order to obtain a predetermined auxiliary capacitance, the ratio of the area of the auxiliary capacitance to the area of the pixel electrode must be increased. As a result, there is a problem that the aperture ratio of the active matrix substrate is reduced, and the brightness and contrast of a displayed image are reduced.

JP-A-7-191348 and JP-A-9-325364 disclose that the ratio of the area of the auxiliary capacitor to the area of the pixel electrode is reduced by etching the interlayer insulating film to make it thinner. Thus, a method for improving the aperture ratio is disclosed. However, in this method, a special patterning is required by photolithography, etching, or the like to etch the interlayer insulating film, and there is a problem that the number of steps is increased.

An object of the present invention is to solve such a problem, and an object of the present invention is to secure a predetermined capacitance value required for an auxiliary capacitor and increase an aperture ratio without increasing the number of steps. To provide a method for manufacturing an active matrix substrate.

[0020]

According to a method of manufacturing an active matrix substrate of the present invention, a plurality of picture element electrodes arranged in a matrix on an insulating substrate and a plurality of picture element electrodes respectively arranged between adjacent picture element electrodes are provided. A first wiring, a plurality of second wirings respectively arranged between the adjacent pixel electrodes so as to intersect the first wirings, each of the pixel electrodes and predetermined first and second wirings;
A method for manufacturing an active matrix substrate having a selection switching element connected to a wiring and an auxiliary capacitance formed by stacking an auxiliary wiring via each picture element electrode and an interlayer insulating film. A gate electrode of the switching element for selection on the insulating substrate,
Forming a first wiring and an auxiliary wiring forming an auxiliary capacitor; sequentially forming the interlayer insulating film, a semiconductor layer and a contact layer on the entire surface of the insulating substrate; Patterning the contact layer with a photosensitive resin, etching the interlayer insulating film on the patterned semiconductor layer and the contact layer using the photosensitive resin as a mask, and a source electrode of the switching element for selection and A drain electrode and a second
Forming a wiring, and forming a pixel electrode electrically connected to the drain electrode of the selection switching element.

According to the method of manufacturing an active matrix substrate of the present invention, a plurality of picture element electrodes arranged in a matrix on an insulating substrate, a plurality of first wirings respectively arranged between adjacent picture element electrodes, A plurality of second wirings respectively arranged so as to intersect the first wiring between the pixel electrodes to be connected, a selection switching element connected to each of the pixel electrodes and predetermined first and second wirings, A method of manufacturing an active matrix substrate having each pixel electrode and an auxiliary capacitor formed by laminating a part of a first wiring via an interlayer insulating film, wherein the selection matrix is provided on the insulating substrate. Forming a gate electrode of the switching element and a first wiring having a portion for forming an auxiliary capacitor, and sequentially forming the interlayer insulating film, the semiconductor layer, and the contact layer on the entire surface of the insulating substrate Patterning the semiconductor layer and the contact layer in a predetermined region with a photosensitive resin, and etching the interlayer insulating film on the patterned semiconductor layer and the contact layer using the photosensitive resin as a mask; Forming a source electrode and a drain electrode of the selection switching element and a second wiring; and forming a picture element electrode electrically connected to the drain electrode of the selection switching element. It is characterized by.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1A shows a partial plan view of one picture element of the active matrix substrate.

In FIG. 1A, pixel electrodes 9 are formed on a transparent insulating substrate 1 in a matrix. Around the picture element electrode 9, a pair of scanning wirings 54 and signal wirings 55 which are parallel to each other are formed so as to intersect with each other in an insulated state, and a TFT 52 is provided at one intersection. Each is provided. Each TFT 52 has a gate electrode connected to the scanning wiring 54, a source electrode connected to the signal wiring 55, and a drain electrode connected to the pixel electrode 9.

Auxiliary wirings 60 are formed in the center between adjacent scanning wirings 54 in parallel with the respective scanning wirings 54, and an interlayer insulating film, which is a dielectric, is provided between the auxiliary wirings 60 and the pixel electrodes 9. Is provided, a capacitor portion having the auxiliary capacitance 53 is formed.

FIGS. 2 (a) to 2 (g) correspond to FIGS.
FIG. 3 is a cross-sectional view illustrating each step of the method for manufacturing the active matrix substrate illustrated in FIG. 2A, and the method for manufacturing the active matrix substrate will be described with reference to FIGS. The left and right sides of each figure are shown in FIG.
7A and 7B are a cross section taken along line AA ′ (part of the TFT 52) and a cross section taken along line BB ′ (part of the auxiliary capacitance 53).

As shown in FIG. 2A, the transparent insulating substrate 1
A metal such as Al, Cr, Ta, or Ti is formed thereon by sputtering or the like, and the formed metal is patterned by subjecting the formed metal to photolithography and etching to form a scanning wiring 54 (not shown). Also, the gate electrode 2 having a trapezoidal cross section and the auxiliary wiring 60 having a trapezoidal cross section
To form Each of the scanning wirings 54 has a TFT forming portion 54 a protruding toward the picture element electrode 9 near the intersection with the signal wiring 55.
Are provided respectively.

Next, as shown in FIG. 2 (b), the film thickness is set so as to cover the gate electrode 2 and the auxiliary wiring 60.
An interlayer insulating film 4 of 3 to 0.6 μm, such as SiN _x or SiO ₂ , is formed over the entire surface of the transparent insulating substrate 1, and the thickness of the interlayer insulating film 4 is 0.07 to 0.25 μm. −
A semiconductor layer 5 made of Si: H (amorphous silicon), p-Si: H (polysilicon) or the like is formed. Further, on the semiconductor layer 5, a-Si: H (amorphous silicon), μc-Si: H (microcrystalline silicon) or the like doped with phosphorus (P) having a thickness of 0.03 to 0.07 μm is used. The contact layer 6 is continuously formed by a CVD method or the like. In the present embodiment, for example, the interlayer insulating film 4 is formed of SiN _X having a thickness of 0.35 μm, the semiconductor layer 5 is formed of a-Si: H having a thickness of 0.15 μm, and a contact layer is formed. No. 6 was formed of μc-Si: H doped with phosphorus (P) and having a thickness of 0.06 μm.

On the contact layer 6, a photoresist is applied, exposed and developed to form a resist pattern 11, and the contact layer 6 and the semiconductor layer 5 other than those where the resist pattern 11 is formed are removed by dry etching. Then, as shown in FIG. 1B, on the TFT forming portion 54 a in the scanning wiring 54, on a portion where the signal wiring 55 intersects, and in the auxiliary wiring 60 where the signal wiring 55 intersects. On the portion, the semiconductor layer 5 and the contact layer 6 are patterned so as to form an island pattern. At this time, the interlayer insulating film 4 is hardly etched.

The dry etching conditions in this case are as follows: pressure: 150 mTorr, gas flow rate: HCl (300 sc)
cm) / SF6 (300 sccm), RF power: 500
W, distance between electrodes: 50 mm, electrode temperature: 60 ° C., overetch time: 10% of etching time, and etching of the contact layer 6 and the semiconductor layer 5 was performed while performing endpoint detection.

Here, the TFT forming portion 54a, the scanning wiring 5
4 and signal wiring 55, auxiliary wiring 60 and signal wiring 5
When the interlayer insulating film 4 is dry-etched in the next step, the pattern of the contact layer 6 and the semiconductor layer 5 provided at the intersection with the interlayer insulating film 5 is not etched. It is for. When the interlayer insulating film 4 provided at the intersection of the scanning wiring 54 and the signal wiring 55 and at the intersection of the auxiliary wiring 60 and the signal wiring 55 is etched by a process in a later step, the inter-layer insulating film 4 is formed. The capacitance between the auxiliary wiring 60 and the signal wiring 5
The capacitance of the liquid crystal display device 5 increases, causing problems such as interference between the gate signal, the source signal, and the image signal, and delay of each signal, thereby deteriorating the quality of image display in the liquid crystal display device.
For this reason, by providing the semiconductor layer 5 and the contact layer 6 at the intersections between the scanning wirings 54 and the signal wirings 55 and at the intersections between the auxiliary wirings 60 and the signal wirings 55, it is possible to reduce the capacitance at those parts. it can.

Next, as shown in FIG. 2C, the TFT forming portion 54a provided with the semiconductor layer 5 and the contact layer 6 patterned by the above-described resist pattern 11, the scanning wiring 54 and the signal wiring 55. And the portion where the interlayer insulating film 4 is exposed other than the intersection between the auxiliary wiring 60 and the signal wiring 55 is further subjected to a resist pattern 11.
Dry etching is performed continuously using the semiconductor layer 5 and the contact layer 6 covered with the mask as a mask, and the thickness of the interlayer insulating film 4 other than the portion where the resist pattern 11 is formed is 0.15.
Adjust so as to be ~ 0.45 µm. This dry etching is performed in a portion where the TFT 52 is formed by the resist pattern 11, an intersection between the scanning wiring 54 and the signal wiring 55, an auxiliary wiring 6
After dry etching at the time of forming a pattern at the intersection of 0 and the signal wiring 55, only the etching conditions are changed without taking out the active matrix substrate from the dry etching apparatus, and the operation is continuously performed.

The dry etching conditions in this case are, for example, pressure: 200 mTorr, gas flow rate: HCl (75
sccm) / SF6 (300 sccm) / He (300
sccm), RF power: 300 W, distance between electrodes: 50 m
m, electrode temperature: 60 ° C., etching time: 180 seconds, etching rate: about 650 ° / min.
Is adjusted so that the film thickness becomes 0.15 μm when the etching is completed, with respect to the initial film thickness of 0.35 μm. As a result, the interlayer insulating film 4 is dry-etched, and its thickness is reduced.

Although the etching of the interlayer insulating film 4 in this step is performed by dry etching in this embodiment,
It may be performed by a wet etching method using 1:10 buffered hydrofluoric acid or the like. The etching of the interlayer insulating film 4 is performed, for example, by etching the contact layer 6 and the semiconductor layer 5 by a dry etching method and etching the interlayer insulating film 4 by a wet etching method. A method different from the etching may be used, or the same method as in this embodiment may be used.

After the dry etching of the interlayer insulating film 4 is completed,
The photoresist of the resist pattern 11 is removed by peeling cleaning or oxygen plasma ashing.

Next, as shown in FIG. 2D, a metal such as Al, Cr, Ta, or Ti is formed on the contact layer 6 and the interlayer insulating film 4 of the TFT forming portion 54a by a sputtering method or the like. Then, the formed metal is patterned by subjecting it to photolithography and etching to form the signal electrode 55 and the source electrode 7 and the drain electrode 8 separately from each other.

Next, as shown in FIG.
An ITO film made of nO ₂ and In ₂ O _{3 is formed} and a TFT is formed.
The pixel electrode 9 is formed by patterning so as to be electrically connected to the drain electrode 8 of the formation portion 54a. As a result, the interlayer insulating film 4 which is a dielectric is formed between the auxiliary wiring 60 and the pixel electrode 9, and the auxiliary capacitance 5 shown in FIG.
3 is formed.

Next, as shown in FIG.
All of the contact layer 6 between the two portions of the source electrode 7 and the drain electrode 8 and a part of the semiconductor layer 5 are removed by dry etching or the like, and the channel region of the TFT 52 and the source electrode 7 and the drain electrode 8 are electrically connected. To separate.

Next, as shown in FIG.
The passivation film 10 made of SiN _X or the like is deposited in two parts, it is patterned. As a result, an active matrix substrate for a liquid crystal display having the configuration shown in FIG.

Here, the capacitance value Cs of the auxiliary capacitance 53 is C
s = εS / d (ε: dielectric constant of interlayer insulating film, S: electrode area on both sides of interlayer insulating film, d: film thickness of interlayer insulating film). From this equation, if the thickness d of the interlayer insulating film 4 is reduced,
Even if the electrode area S of the formation part of the auxiliary capacitance 53 becomes small, a predetermined capacitance can be secured. In the present embodiment, the auxiliary capacitance 5
The electrode area of the auxiliary wiring 3 is determined by the wiring width of the auxiliary wiring 60. Therefore, the wiring width of the auxiliary wiring 60 can be reduced by reducing the thickness of the interlayer insulating film 4, and the electrode area of the auxiliary capacitance 53 is reduced. It can be made smaller and the opening rate of each picture element can be made larger. However, if the film thickness of the interlayer insulating film 4 is too thin, the withstand voltage of the interlayer insulating film 4 may decrease. Therefore, it is necessary to secure the film thickness of the interlayer insulating film 4 to at least about 0.15 μm. is there.

FIG. 3A is a plan view of one picture element portion of another example of the active matrix substrate. In this active matrix substrate, a part of the scanning wiring 54 is
The capacitor portion having the auxiliary capacitance 53 is formed by providing the interlayer insulating film 4 as a dielectric between the widened portion 53a of the scanning wiring 54 and the pixel electrode 9 so as to widen to the side. Other configurations are the same as those of the active matrix substrate shown in FIG.

FIGS. 4A to 4G respectively show FIGS.
5A is a cross-sectional view illustrating each step in the method of manufacturing the active matrix substrate illustrated in FIG. 4A, and the method of manufacturing the active matrix substrate will be described with reference to FIGS. The left and right sides of each figure are an AA ′ section (TFT 52 portion) and a BB ′ section (auxiliary capacitance 53 portion) of FIG. 3A, respectively.

As shown in FIG. 4A, the transparent insulating substrate 1
A metal such as Al, Cr, Ta, or Ti is formed thereon by sputtering or the like, and the formed metal is patterned by subjecting the formed metal to photolithography and etching to form a scanning wiring 54 having a widened portion 53a. With
A gate electrode 2 having a trapezoidal cross section is formed. Each scanning wiring 5
4 is provided with a TFT forming portion 54 a protruding toward the picture element electrode 9 in the vicinity of the intersection with the signal wiring 55.

Next, as shown in FIG.
The pole 2 and the scanning wiring 54, the widened portion 53 a of the scanning wiring 54
So that the film thickness is 0.3 to 0.6 μm.
iN _X, SiO_TwoAnd the like on the transparent insulating substrate 1.
Is formed over the entire surface of the substrate, and the film thickness is
A-Si: H (amorph: 0.07 to 0.25 μm)
Silicon), p-Si: H (polysilicon), etc.
Is formed. Further, on the semiconductor layer 5,
Phosphorus (P) having a thickness of 0.03 to 0.07 μm is doped
A-Si: H (amorphous silicon), μc
-Si: Contact layer made of H (microcrystalline silicon) or the like
6 is continuously formed by a CVD method or the like. In this embodiment
Is, for example, an interlayer insulating film 4 having a thickness of 0.35 μm.
SiN_XAnd a semiconductor layer 5 having a thickness of 0.15
a-Si: H of μm, and a contact layer 6
Was doped with phosphorus (P) having a thickness of 0.06 μm.
It was formed by μc-Si: H.

A photoresist is applied on the contact layer 6, exposed and developed to form a resist pattern 11, and the contact layer 6 and the semiconductor layer 5 other than those where the resist pattern 11 is formed are removed by dry etching. Then, as shown in FIG. 3B, the semiconductor layer 5 and the contact layer 6 are formed in an island-like pattern on the TFT forming portion 54a of the scanning wiring 54 and on a portion where the signal wiring 55 intersects. Is patterned. At this time, the interlayer insulating film 4 is hardly etched.

The dry etching conditions in this case are as follows: pressure: 150 mTorr, gas flow rate: HCl (300 sc)
cm) / SF6 (300 sccm), RF power: 500
W, distance between electrodes: 50 mm, electrode temperature: 60 ° C., overetch time: 10% of etching time, and etching of the contact layer 6 and the semiconductor layer 5 was performed while performing endpoint detection.

Here, the TFT forming portion 54a, the scanning wiring 5
Contact layer 6 provided at the intersection of signal line 4 and signal wiring 55
The pattern of the semiconductor layer 5 is intended to prevent the interlayer insulating film 4 provided in these portions from being etched when the interlayer insulating film 4 is dry-etched in the next step. When the interlayer insulating film 4 provided at the intersection of the scanning wiring 54 and the signal wiring 55 is etched in a later process, the capacitance between the scanning wiring 54 and the signal wiring 55 increases, and the gate signal and the source signal As a result, problems such as interference of image signals and delay of each signal occur, and the quality of image display in the liquid crystal display device deteriorates. For this reason, by providing the semiconductor layer 5 and the contact layer 6 at the intersections of the scanning wirings 54 and the signal wirings 55, it is possible to reduce the capacitance at those parts.

Next, as shown in FIG. 4C, the TFT forming portion 54a in which the semiconductor layer 5 and the contact layer 6 patterned by the above-described resist pattern 11 are provided, the scanning wiring 54 and the signal wiring 55. Then, dry etching is continuously performed on a portion where the interlayer insulating film 4 is exposed other than the intersection of the semiconductor layer 5 and the contact layer 6 covered with the resist pattern 11 as a mask.
The thickness of the interlayer insulating film 4 other than the portion where the resist pattern 11 is formed is adjusted to be 0.15 to 0.45 μm. This dry etching is performed by the T
After dry etching at the time of forming a pattern at the intersection of the FT forming portion 54a and the scanning wiring 54 with the signal wiring 55, only the etching conditions are changed without taking out the active matrix substrate from inside the dry etching apparatus, and the processing is continuously performed.

The dry etching conditions in this case include, for example, a pressure of 200 mTorr and a gas flow rate of HCl (75
sccm) / SF6 (300 sccm) / He (300
sccm), RF power: 300 W, distance between electrodes: 50 m
m, electrode temperature: 60 ° C., etching time: 180 seconds, etching rate: about 650 ° / min.
Is adjusted so that the film thickness becomes 0.15 μm when the etching is completed, with respect to the initial film thickness of 0.35 μm. As a result, the interlayer insulating film 4 is dry-etched, and its thickness is reduced.

In this embodiment, dry etching is used for etching the interlayer insulating film 4 in this step.
It may be performed by a wet etching method using 1:10 buffered hydrofluoric acid or the like. The etching of the interlayer insulating film 4 is performed, for example, by etching the contact layer 6 and the semiconductor layer 5 by a dry etching method and etching the interlayer insulating film 4 by a wet etching method. A method different from the etching may be used, or the same method as in this embodiment may be used.

After the dry etching of the interlayer insulating film 4 is completed,
The photoresist of the resist pattern 11 is removed by peeling cleaning or oxygen plasma ashing.

Next, as shown in FIG. 4D, a metal such as Al, Cr, Ta, or Ti is formed on the contact layer 6 and the interlayer insulating film 4 of the TFT forming portion 54a by a sputtering method or the like. Then, the formed metal is patterned by subjecting it to photolithography and etching to form the signal electrode 55 and the source electrode 7 and the drain electrode 8 separately from each other.

Next, as shown in FIG.
An ITO film made of nO ₂ and In ₂ O _{3 is formed} and a TFT is formed.
The pixel electrode 9 is formed by patterning so as to be electrically connected to the drain electrode 8 of the formation portion 54a. As a result, the interlayer insulating film 4 as a dielectric is formed between the widened portion 53a of the scanning wiring 54 and the picture element electrode 9, and the auxiliary capacitance 53 shown in FIG.

Next, as shown in FIG.
All of the contact layer 6 between the two portions of the source electrode 7 and the drain electrode 8 is partially removed by dry etching or the like, and the channel region of the TFT 52 and the source electrode 7 and the drain electrode 8 are electrically connected. To separate.

Next, as shown in FIG.
The passivation film 10 made of SiN _X or the like is deposited in two parts, it is patterned. Thus, an active matrix substrate for a liquid crystal display having the configuration shown in FIG.

As described above, when the thickness d of the interlayer insulating film 4 is reduced, the storage capacitance
Even if the electrode area S of the formation portion 3 becomes small, a predetermined capacitance can be secured. In the present embodiment, the electrode area of the auxiliary capacitance 53 is determined by the widened portion 54a of the scanning wiring 54. Therefore, the widened portion 54a of the scanning wiring 54 can be narrowed by reducing the thickness of the interlayer insulating film 4. At the same time, the electrode area of the auxiliary capacitance 53 can be reduced, and the opening ratio of each picture element can be increased. However, if the film thickness of the interlayer insulating film 4 is too thin, the withstand voltage of the interlayer insulating film 4 may decrease.
It is necessary to secure at least about 0.15 μm.

[0057]

According to the method of manufacturing an active matrix substrate of the present invention, an interlayer insulating film, a semiconductor layer, and a contact layer are sequentially formed on the entire surface of an insulating substrate, and a predetermined region of the semiconductor layer and the contact layer are formed of a photosensitive resin. By using a photosensitive resin as a mask on the patterned semiconductor layer and contact layer, the interlayer insulating film is etched and thinned, so that the capacitance value required for the auxiliary capacitance can be increased without increasing the number of steps. It is possible to achieve a high aperture ratio while sufficiently securing, and obtain an image with high brightness and high contrast.

[Brief description of the drawings]

FIG. 1A is a plan view of one picture element of an active matrix substrate. (B) is a schematic plan view in the manufacturing process.

FIGS. 2A to 2G are cross-sectional views illustrating respective steps in a method for manufacturing an active matrix substrate according to an embodiment of the present invention.

FIG. 3A is a plan view of one picture element showing another example of an active matrix substrate, and FIG. 3B is a schematic plan view in a manufacturing process thereof.

FIGS. 4A to 4G are cross-sectional views illustrating respective steps in a method for manufacturing an active matrix substrate according to another embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of one picture element in a conventional active matrix substrate.

6A is a plan view of one picture element of an active matrix substrate, and FIG. 6B is an equivalent circuit diagram of each picture element on the active matrix substrate.

FIG. 7A is a plan view of one picture element of an active matrix substrate, and FIG. 7B is an equivalent circuit diagram of each picture element on the active matrix substrate.

FIGS. 8A to 8F are cross-sectional views illustrating respective steps in a conventional method for manufacturing an active matrix substrate.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 transparent insulating substrate 2 gate electrode 4 interlayer insulating film 5 semiconductor layer 6 contact layer 7 source electrode 8 drain electrode 9 picture element electrode 10 passivation film 11 resist pattern 19 transparent insulating substrate 20 gate electrode 40 interlayer insulating film 50 semiconductor layer 51 liquid crystal capacitance 52 TFT 53 Auxiliary capacitance 53a Widened portion 54 Scanning wiring 54a TFT forming portion 55 Signal wiring 56 Counter electrode 60 Auxiliary wiring 65 Contact layer 70 Source electrode 80 Drain electrode 90 Pixel electrode 100 Passivation film

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 2H092 JA28 JA37 JA45 JB56 JB69 KB25 MA17 NA07 NA27 5C094 AA02 AA06 AA10 AA43 AA60 BA03 BA43 CA19 EA04 EA05 EB02 5F110 AA16 AA30 BB01 CC07 DD01 DD02 EE03 EE04 GG0223 GG24 HK03 HK04 HK07 HK09 HK15 HK16 HK22 HK25 HK33 NN02 NN04 NN23 NN24 NN72 NN73 QQ04

Claims (2)

[Claims] 1. A plurality of picture element electrodes arranged in a matrix on an insulating substrate; a plurality of first wirings respectively arranged between adjacent picture element electrodes; and a first wiring between adjacent picture element electrodes. A plurality of second wirings arranged so as to intersect with each other, a selection switching element connected to each picture element electrode and a predetermined first wiring and a second wiring, respectively, each picture element electrode and an interlayer insulating film A method of manufacturing an active matrix substrate having an auxiliary capacitance formed by laminating auxiliary wirings via: a gate electrode of the selection switching element on the insulating substrate; a first wiring; Forming an auxiliary wiring for forming an auxiliary capacitance; sequentially forming the interlayer insulating film, a semiconductor layer and a contact layer on the entire surface of the insulating substrate; and forming the semiconductor layer and the contact in a predetermined region Patterning a layer with a photosensitive resin, etching the interlayer insulating film on the patterned semiconductor layer and the contact layer using the photosensitive resin as a mask, and a source electrode and a drain electrode of the selection switching element. Forming a second wiring, and forming a pixel electrode electrically connected to the drain electrode of the selection switching element. A method for manufacturing an active matrix substrate, comprising: . 2. A plurality of picture element electrodes arranged in a matrix on an insulating substrate; a plurality of first wirings respectively arranged between adjacent picture element electrodes; and a first wiring between adjacent picture element electrodes. A plurality of second wirings respectively arranged so as to intersect with each other, a switching element for selection connected to each picture element electrode and predetermined first and second wirings, and each picture element electrode and an interlayer insulating film. A method of manufacturing an active matrix substrate having an auxiliary capacitance formed by laminating a part of a first wiring via an insulating substrate, comprising: a gate electrode of the selection switching element on the insulating substrate; Forming a first wiring having a portion for forming a first wiring, a step of sequentially forming the interlayer insulating film, a semiconductor layer, and a contact layer on the entire surface of the insulating substrate; and forming the semiconductor layer and the contact layer in a predetermined region Patterning with a photosensitive resin, etching the interlayer insulating film on the patterned semiconductor layer and the contact layer using the photosensitive resin as a mask, and a source electrode and a drain electrode of the selection switching element. Forming a pixel electrode electrically connected to the drain electrode of the selection switching element. 2. A method for manufacturing an active matrix substrate, comprising: