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JPH0590017A - Manufacture of insulating substrate for chip-shaped variable resistance - Google Patents

Manufacture of insulating substrate for chip-shaped variable resistance

Info

Publication number
JPH0590017A
JPH0590017A JP3247743A JP24774391A JPH0590017A JP H0590017 A JPH0590017 A JP H0590017A JP 3247743 A JP3247743 A JP 3247743A JP 24774391 A JP24774391 A JP 24774391A JP H0590017 A JPH0590017 A JP H0590017A
Authority
JP
Japan
Prior art keywords
ceramic material
electrode film
material plate
insulating substrate
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3247743A
Other languages
Japanese (ja)
Inventor
Tamotsu Yoshimura
保 吉村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP3247743A priority Critical patent/JPH0590017A/en
Publication of JPH0590017A publication Critical patent/JPH0590017A/en
Pending legal-status Critical Current

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  • Adjustable Resistors (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

PURPOSE:To prevent the degradation of dimensional accuracy of an insulating substrate due to a conductive paste for electrode film, with which the surface and the rear surface of a ceramic blank sheet are coated and that the transfer operation of the ceramic blank sheet is distributed when a plurality of insulating substrates for chip-shaped variable resistance, which are provided with an electrode film are manufactured simultaneously by using one ceramic blank sheet. CONSTITUTION:Blank parts A4, A5 having a proper width are connected to and brought into contact with both the right and left faces of a ceramic blank sheet A integrally via stripe lines B2 for breaking use. The blank parts A4, A5 are cut and removed after a surface electrode film 5a and a rear-surface electrode film 5c out of electrode films 5 have been formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、抵抗値を可変にしたチ
ップ型の可変抵抗器において、抵抗膜と、該抵抗膜の両
端に対する電極膜とを備えたセラミック製絶縁基板の製
造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type variable resistor having a variable resistance value, and a method of manufacturing a ceramic insulating substrate having a resistance film and electrode films on both ends of the resistance film. Is.

【0002】[0002]

【従来の技術】一般に、この種のチップ型可変抵抗器
は、図1〜図3に示すように、セラミック製のチップ型
絶縁基板1の上面に中心孔2と同芯円状に抵抗膜3を形
成する一方、前記絶縁基板1の側面に突出するように造
形した一対の電極用突起4に、該抵抗膜3の両端の各々
に対する電極膜5を形成し、前記抵抗膜3に摺接する摺
動子6を、前記中心孔2に挿通した軸7に対して回転自
在に取付けた構成にしている。
2. Description of the Related Art Generally, as shown in FIGS. 1 to 3, a chip type variable resistor of this type has a resistance film 3 concentric with a central hole 2 on an upper surface of a ceramic chip type insulating substrate 1. On the other hand, a pair of electrode projections 4 formed so as to project from the side surface of the insulating substrate 1 are formed with electrode films 5 for both ends of the resistance film 3, and a sliding contact with the resistance film 3 is made. The moving element 6 is rotatably attached to the shaft 7 inserted through the center hole 2.

【0003】なお、前記両電極用突起4における各電極
膜5は、絶縁基板1の上面に前記抵抗膜3に接触するよ
うに形成した上面電極膜5aと、両突起4の側面に形成
した側面電極膜5bと、絶縁基板1の下面に形成した下
面電極膜5cとによって構成され、また、前記軸7に
は、摺動子6に電気的に導通する中心電極8が、絶縁基
板1の下面に形成した凹所9内に位置するように一体的
に造形されている。
The electrode films 5 of the projections 4 for both electrodes are the upper surface electrode film 5a formed on the upper surface of the insulating substrate 1 so as to contact the resistance film 3 and the side surfaces formed on the side surfaces of the projections 4. The lower electrode film 5b formed on the lower surface of the insulating substrate 1 and the lower electrode film 5c formed on the lower surface of the insulating substrate 1 have a central electrode 8 electrically connected to the slider 6 on the shaft 7. It is integrally molded so as to be located in the recess 9 formed in the.

【0004】そして、このチップ型可変抵抗器におい
て、抵抗膜3及び両電極膜5を備えた絶縁基板1を製造
するに際して、本発明者は、先の特許出願(特願昭63
−292096号、特開平2−137201号)におい
て、以下に述べるような方法を提案した。すなわち、図
9に示すように、先づ、セラミック素材板Aを、多数個
の絶縁基板1を当該各絶縁基板1における電極用突起4
が外向きとなるように二列に並べて成る二列セラミック
素材板A1 の三枚を、これら三枚の各二列セラミック素
材板A1の各絶縁基板1における電極用突起4の箇所に
おいて一体的に連結するようにして構成し、その両端部
には、余白耳片A2 ,A3 を一体的に連接し、且つ、前
記各絶縁基板1の相互間、及び各絶縁基板1と両余白耳
片A2 ,A3 との間に、ブレーク用の筋目線Bを設け
て、長さ寸法がLで、幅寸法がSの矩形状に構成する。
When manufacturing the insulating substrate 1 having the resistance film 3 and the electrode films 5 in this chip type variable resistor, the inventor of the present invention filed a prior patent application (Japanese Patent Application No. 63-63).
No. 2,920,961 and JP-A No. 2-137201) proposed the following method. That is, as shown in FIG. 9, first, the ceramic material plate A and the plurality of insulating substrates 1 are attached to the electrode projections 4 on each insulating substrate 1.
Of the two-row ceramic material plates A 1 which are arranged in two rows so as to face outward, are integrally formed at the electrode projections 4 in each insulating substrate 1 of each of these three two-row ceramic material plates A 1. And the margin tabs A 2 and A 3 are integrally connected to both ends of the margins, and the margins between the insulation boards 1 and between the insulation board 1 and the margins of both margins. A score line B for break is provided between the pieces A 2 and A 3 to form a rectangular shape having a length dimension L and a width dimension S.

【0005】前記セラミック素材板Aを、その下面を上
向きにして、各絶縁基板1における電極用突起4の箇所
に、図10に示すように、導電性ペーストをスクリーン
印刷によって塗着し、乾燥・焼成することにより、電極
膜5における下面電極膜5cを形成し、次いで、前記セ
ラミック素材板Aを、図11に示すように、その上面を
上向きにして、各絶縁基板1における電極用突起4の箇
所に、導電性ペーストをスクリーン印刷によって塗着し
て乾燥・焼成することにより、電極膜5における上電極
極膜5aを形成したのち、各絶縁基板1の箇所に、抵抗
膜3を構成するペーストを円弧状にスクリーン印刷によ
って塗着したのち乾燥・焼成することによって、抵抗膜
3を形成する。
With the lower surface of the ceramic material plate A facing upward, a conductive paste is applied by screen printing to the electrode projections 4 of each insulating substrate 1 as shown in FIG. By firing, the lower surface electrode film 5c of the electrode film 5 is formed, and then the ceramic material plate A is placed with the upper surface thereof facing upward as shown in FIG. A conductive paste is applied to the places by screen printing, dried and baked to form the upper electrode pole film 5a in the electrode film 5, and then the paste forming the resistance film 3 at the places of each insulating substrate 1. Is applied in an arc shape by screen printing, and then dried and baked to form the resistance film 3.

【0006】そして、前記セラミック素材板Aを、図1
2に示すように、三枚の各二列セラミック素材板A1
とに、筋目線Bに沿ってブレークしたのち、この各二列
セラミック素材板A1 の各絶縁基板1における突起4の
先端部側面に、導電性ペーストを塗着して乾燥・焼成す
ることにより、電極膜5における側面電極膜5bを形成
し、最後に、各二列セラミック素材板A1 を、各筋目線
Bに沿って、各絶縁基板1ごとにブレークする順序で製
造する。 〔発明が解決しようとする課題〕そして、この先願発明
の製造方法は、一枚のセラミック素材板によって製造す
ることのできる絶縁基板の数は、一つの列に並べた数
に、互いに一体的に連結した二列セラミック素材の数及
び二倍を掛算した値になるから、一枚のセラミック素材
板によって製造することのできる絶縁基板の数を、一つ
の列に並べる数を多くすることなく、換言すると、列方
向の長さ寸法を増大することなく、飛躍的に増大できる
のであり、その結果、絶縁基板の製造に要するコストを
大幅に低減できると言う利点を有する。
Then, the ceramic material plate A is shown in FIG.
As shown in FIG. 2, after breaking each of the three double-row ceramic material plates A 1 along the score line B, the tip end portion of the protrusion 4 in each insulating substrate 1 of each two-row ceramic material plate A 1 The side surface electrode film 5b in the electrode film 5 is formed by applying a conductive paste on the side surface and drying and baking, and finally, each two-row ceramic material plate A 1 is arranged along each score line B. , Each insulating substrate 1 is manufactured in the order of breaking. [Problems to be Solved by the Invention] And, in the manufacturing method of the invention of the prior application, the number of insulating substrates that can be manufactured by one ceramic material plate is the number arranged in one row, integrally with each other. Since the number of connected two-row ceramic materials and the value multiplied by double the number, the number of insulating substrates that can be manufactured by one ceramic material plate can be expressed in other words without increasing the number of rows arranged in one row. Then, the length in the column direction can be dramatically increased without increasing, and as a result, the cost required for manufacturing the insulating substrate can be significantly reduced.

【0007】しかし、その反面、各絶縁基板1における
電極膜5のうち上面電極膜5a及び下面電極膜5cを形
成するに際して、前記セラミック素材板Aの上面及び下
面に対して導電性ペーストを印刷にて塗着したとき、こ
れら上面電極膜5a用の導電性ペースト及び下面電極膜
5c用の導電性ペーストのうち前記セラミック素材板A
の左右両側面Aa,Abに隣接する部分における導電性
ペーストが、当該導電性ペーストがその乾燥にて固まる
までの間に、前記セラミック素材板Aの左右両側面A
a,Abに向かって垂れ落ちることになるから、前記先
願発明の方法のままでは、 .セラミック素材板Aを、これに前記上面電極膜5a
用の導電性ペーストを塗着したのち次の乾燥工程等に移
送するとき、及びこれに前記下面電極膜5c用の導電性
ペースト塗着したのち次の乾燥工程等に移送するときに
おいて、前記のようにセラミック素材板Aの左右両側面
Aa,Abに垂れ落ちたペーストが、当該セラミック素
材板Aを移送するための移送手段に付着して、その移送
を著しく妨げるから、前記セラミック素材板Aの移送不
能が発生したり、前記セラミック素材板Aに割れが発生
する。 .前記のようにセラミック素材板Aの左右両側面A
a,Abに垂れ落ちたペーストが、各絶縁基板1の電極
膜5における側面電極膜5bの一部になり、各絶縁基板
1の電極膜5における側面電極膜5bの厚さ寸法が、多
数個の絶縁基板1の各々について不揃いになるから、製
品の寸法精度が大幅に低下する。と言う問題があった。
However, on the other hand, when forming the upper surface electrode film 5a and the lower surface electrode film 5c of the electrode film 5 on each insulating substrate 1, a conductive paste is printed on the upper surface and the lower surface of the ceramic material plate A. Of the conductive paste for the upper surface electrode film 5a and the conductive paste for the lower surface electrode film 5c, the ceramic material plate A
The left and right side surfaces A of the ceramic material plate A are covered by the conductive paste in the portions adjacent to the left and right side surfaces Aa, Ab until the conductive paste solidifies by drying.
Since it will droop toward a and Ab, if the method of the above-mentioned prior invention is used ,. The ceramic material plate A is provided with the upper electrode film 5a.
When the conductive paste for coating is transferred to the next drying step or the like, and when the conductive paste for the lower surface electrode film 5c is applied thereto and then transferred to the next drying step or the like, The paste dripped on the left and right side surfaces Aa and Ab of the ceramic material plate A adheres to the transfer means for transferring the ceramic material plate A and significantly hinders the transfer. Inability to transfer occurs, or the ceramic material plate A is cracked. . As described above, the left and right side surfaces A of the ceramic material plate A
The paste dripped on a and Ab becomes a part of the side surface electrode film 5b in the electrode film 5 of each insulating substrate 1, and the thickness dimension of the side surface electrode film 5b in the electrode film 5 of each insulating substrate 1 is large. Since the insulating substrates 1 are uneven, the dimensional accuracy of the product is significantly reduced. There was a problem to say.

【0008】本発明は、先願発明における前記の問題を
解消するようにした絶縁基板の製造方法を提供すること
を技術的課題とするものである。
An object of the present invention is to provide a method for manufacturing an insulating substrate that solves the above problems in the prior invention.

【0009】[0009]

【課題を解決するための手段】この技術的課題を達成す
るため本発明は、多数個の絶縁基板を当該各絶縁基板に
おける電極用突起が外向きとなるように二列に並べて成
る二列セラミック素材板の複数枚を、これら二列セラミ
ック素材板の各絶縁基板における電極用突起の箇所にお
いて一体的に連結するようにして一枚のセラミック素材
板を形成し、このセラミック素材板における各絶縁基板
の箇所に、上面電極膜、下面電極膜及び抵抗膜を形成
し、次いで、このセラミック素材板を、前記二列セラミ
ック素材板にブレークしたのち、この二列セラミック素
材板における各絶縁基板の箇所に側面電極膜を形成する
において、前記セラミック素材基板として、その各絶縁
基板の列方向の左右両側面に、予め、適宜幅の余白部を
ブレーク用筋目線を介して一体的に連接したものを使用
し、この両余白部を、前記上面電極膜及び下面電極膜を
形成したあとでブレークすることにした。
In order to achieve this technical object, the present invention provides a two-row ceramic in which a large number of insulating substrates are arranged in two rows so that the electrode projections on each insulating substrate face outward. A plurality of material plates are integrally connected at the electrode projections of each insulating substrate of these two-row ceramic material plates to form one ceramic material plate, and each insulating substrate of the ceramic material plates is formed. After forming the upper surface electrode film, the lower surface electrode film and the resistance film at the location of, and then breaking the ceramic material plate into the double row ceramic material plate, at the location of each insulating substrate in the double row ceramic material plate. In forming the side surface electrode film, as the ceramic material substrate, the left and right side surfaces in the column direction of each insulating substrate are preliminarily provided with a blank portion having an appropriate width and a break line for break. And using those connected integrally with, the two margin portions, decided to break after the formation of the upper electrode film and the lower electrode film.

【0010】[0010]

【作 用】このように構成すると、セラミック素材板
の上面及び下面の各々に対して、上面電極用の導電性ペ
ースト及び下面電極用の導電性ペーストを印刷等により
塗着する場合において、これら各導電性ペースのうちセ
ラミック素材板の左右両側面に隣接するものが、セラミ
ック素材板の左右両側面に向かって垂れ落ちることを、
前記セラミック素材板の左右両側面に一体的に連接した
余白部によって確実に阻止することができるのである。
[Operation] With this structure, when the upper surface and the lower surface of the ceramic material plate are coated with the conductive paste for the upper surface electrode and the conductive paste for the lower surface electrode by printing or the like, respectively. Of the conductive pace, those that are adjacent to the left and right side surfaces of the ceramic material plate should drop toward the left and right side surfaces of the ceramic material plate.
It is possible to surely prevent it by the blank portions integrally connected to the left and right side surfaces of the ceramic material plate.

【0011】[0011]

【発明の効果】従って、本発明によると、セラミック素
材板を、これに上面電極膜用の導電性ペーストを塗着し
たのち次の乾燥工程等に移送するとき、及びこれに下面
電極膜用の導電性ペースト塗着したのち次の乾燥工程等
に移送するときにおいて、移送不能が発生したり、前記
セラミック素材板に割れが発生したりすることを確実に
防止できる一方、各絶縁基板の電極膜における側面電極
膜の厚さ寸法が、多数個の絶縁基板の各々について不揃
いになることを防止できて、製品の寸法精度を向上でき
る効果を有する。
Therefore, according to the present invention, when the ceramic material plate is coated with the conductive paste for the upper surface electrode film and then transferred to the next drying step or the like, and also for the lower surface electrode film. When the conductive paste is applied and then transferred to the next drying step or the like, it is possible to reliably prevent the transfer failure or the occurrence of cracks in the ceramic material plate, on the other hand, the electrode film of each insulating substrate. The thickness dimension of the side surface electrode film can be prevented from becoming uneven in each of the plurality of insulating substrates, and the dimensional accuracy of the product can be improved.

【0012】[0012]

【実施例】以下、本発明の実施例を図4〜図8について
説明する。図において符号Aは、一枚のセラミック素材
板を示し、該セラミック素材板Aを、図4に示すよう
に、前記先願発明の場合と同様に、多数個の絶縁基板1
を当該各絶縁基板1における電極用突起4が外向きとな
るように二列に並べて成る二列セラミック素材板A1の
三枚を、これら三枚の各二列セラミック素材板A1の各
絶縁基板1における電極用突起4の箇所において一体的
に連結するようにして構成し、その両端部に、余白耳片
2 ,A3 を一体的に連接し、且つ、前記各絶縁基板1
の相互間、及び各絶縁基板1と両余白耳片A2 ,A3
の間に、各々ブレーク用の筋目線B1 を設けたものに構
成すると共に、その左右両側面に、適宜幅寸法Wの余白
部A4 ,A5 を、ブレーク用の筋目線B2 を介して一体
的に連接することによって、長さ寸法がLで、幅寸法が
0 の矩形状に構成する。
Embodiments of the present invention will be described below with reference to FIGS. In the figure, reference numeral A indicates one ceramic material plate, and as shown in FIG. 4, the ceramic material plate A is provided with a large number of insulating substrates 1 as in the case of the prior invention.
Three of the two-row ceramic material plates A1 which are arranged in two rows so that the electrode projections 4 on each of the insulating substrates 1 face outward. Of the electrode projection 4 are integrally connected to each other, and the marginal ear pieces A 2 and A 3 are integrally connected to both ends thereof, and the insulating substrate 1
And the margin lines B 1 for break are provided between each other and between each insulating substrate 1 and both margin tabs A 2 and A 3, and the width dimension is appropriately set on the left and right side surfaces thereof. The blank portions A 4 and A 5 of W are integrally connected to each other through the break line B 2 to form a rectangular shape having a length dimension L and a width dimension S 0 .

【0013】前記セラミック素材板Aを、その下面を上
向きにして、各絶縁基板1における電極用突起4の箇所
に、図5に示すように、下面電極膜5cを構成する導電
性ペーストをスクリーン印刷等によって塗着して乾燥し
たのち焼成することにより、電極膜5における下面電極
膜5cを形成する。次いで、前記セラミック素材板A
を、その上面を上向きにして、各絶縁基板1における電
極用突起4の箇所に、図6に示すように、上面電極膜5
aを構成する導電性ペーストをスクリーン印刷等によっ
て塗着して乾燥したのち焼成することにより、電極膜5
における上電極極膜5aを形成する。
With the lower surface of the ceramic material plate A facing upward, a conductive paste forming a lower surface electrode film 5c is screen-printed on the electrode projections 4 of each insulating substrate 1 as shown in FIG. The lower surface electrode film 5c of the electrode film 5 is formed by applying the film by means such as a coating method, drying it, and then baking it. Then, the ceramic material plate A
With the upper surface thereof facing upward, at the location of the electrode projection 4 on each insulating substrate 1, as shown in FIG.
The conductive film forming a is applied by screen printing or the like, dried, and then baked to form the electrode film 5.
To form the upper electrode electrode film 5a.

【0014】これらが終わると、前記セラミック素材板
Aの上面のうち各絶縁基板1の箇所に、図7に示すよう
に、抵抗膜3を構成するペーストを円弧状にスクリーン
印刷等によって塗着して乾燥したのち焼成することによ
って、円弧状の抵抗膜3を形成する。そして、前記セラ
ミック素材板Aを、図8に示すように、三枚の各二列セ
ラミック素材板A1 ごとに、筋目線B1 に沿ってブレー
クすると共に、前記セラミック素材板Aの左右両側にお
ける両余白部A4 ,A5 を、筋目線B2 に沿ってグレー
クすることによって切除する。
After these steps are completed, the paste forming the resistance film 3 is applied in an arc shape by screen printing or the like on the upper surface of the ceramic material plate A on each insulating substrate 1 as shown in FIG. The arc-shaped resistance film 3 is formed by baking after drying, drying and baking. Then, as shown in FIG. 8, the ceramic material plate A is broken along the score lines B 1 for each of the three double-row ceramic material plates A 1 , and the ceramic material plate A is formed on both left and right sides of the ceramic material plate A. Both margins A 4 and A 5 are excised by graying along the crease line B 2 .

【0015】次いで、前記各二列セラミック素材板A1
の各絶縁基板1における突起4の先端部側面に、側面電
極膜5bを構成する導電性ペーストを塗着して乾燥した
のち焼成することにより、電極膜5における側面電極膜
5bを形成し、最後に、各二列セラミック素材板A
1 を、各筋目線B1に沿って、図9に示すような、各絶
縁基板1ごとにブレークするのである。
Next, each of the two-row ceramic material plate A 1
The side surface electrode film 5b in the electrode film 5 is formed by applying the conductive paste forming the side surface electrode film 5b to the side surface of the tip end portion of the protrusion 4 in each insulating substrate 1, drying and baking. , Each two-row ceramic material plate A
1 is broken along each line B 1 for each insulating substrate 1 as shown in FIG.

【0016】なお、前記した製造方法においては、セラ
ミック素材板Aの下面を上向きにした状態で下面電極膜
5cを導電性ペーストの塗着、乾燥及び焼成にて形成す
る一方、セラミック素材板Aの上面を上向きにして、上
面電極膜5aを、導電性ペーストの塗着・乾燥及び焼成
によって形成し、次いで、セラミック素材板Aの上面
に、抵抗膜3用のペーストを塗着、乾燥し、各二列セラ
ミック素材板A1 及び両余白部A4 ,A5 のグレークを
行い、側面電極膜5b用の導電性ペーストを塗着、乾燥
したのち、抵抗膜3及び側面電極膜5bを同時に焼成す
るように構成しても良く、このようにすることにより、
焼成の工程を一回だけ少なくすることができるのであ
る。
In the above-mentioned manufacturing method, the lower surface electrode film 5c is formed by applying a conductive paste, drying and firing with the lower surface of the ceramic material plate A facing upward, while the lower surface of the ceramic material plate A is formed. With the upper surface facing upward, the upper surface electrode film 5a is formed by applying, drying and firing a conductive paste, and then the paste for the resistance film 3 is applied and dried on the upper surface of the ceramic material plate A. The two-row ceramic material plate A 1 and both margins A 4 and A 5 are grayed, a conductive paste for the side surface electrode film 5b is applied and dried, and then the resistance film 3 and the side surface electrode film 5b are simultaneously fired. It may be configured as follows. By doing this,
The firing process can be reduced only once.

【図面の簡単な説明】[Brief description of drawings]

【図1】チップ型可変抵抗器の平面図である。FIG. 1 is a plan view of a chip variable resistor.

【図2】図1のII−II視断面図である。FIG. 2 is a sectional view taken along line II-II of FIG.

【図3】チップ型可変抵抗器に使用する絶縁基板の拡大
斜視図である。
FIG. 3 is an enlarged perspective view of an insulating substrate used for a chip type variable resistor.

【図4】本発明の実施例におけるセラミック素材板の平
面図である。
FIG. 4 is a plan view of a ceramic material plate according to an embodiment of the present invention.

【図5】図4のセラミック素材板の下面に下面電極膜を
形成したときの平面図である。
5 is a plan view of a lower surface electrode film formed on the lower surface of the ceramic material plate of FIG. 4. FIG.

【図6】図4のセラミック素材板の上面に上面電極膜を
形成したときの平面図である。
FIG. 6 is a plan view when an upper surface electrode film is formed on the upper surface of the ceramic material plate of FIG.

【図7】図4のセラミック素材板の上面に抵抗膜を形成
したときの平面図である。
FIG. 7 is a plan view when a resistance film is formed on the upper surface of the ceramic material plate of FIG.

【図8】図4のセラミック素材板をブレークしたときの
平面図である。
FIG. 8 is a plan view when the ceramic material plate of FIG. 4 is broken.

【図9】従来の方法に使用するセラミック素材板の平面
図である。
FIG. 9 is a plan view of a ceramic material plate used in a conventional method.

【図10】図9のセラミック素材板の下面に下面電極膜
を形成したときの平面図である。
FIG. 10 is a plan view when a lower surface electrode film is formed on the lower surface of the ceramic material plate of FIG.

【図11】図9のセラミック素材板の上面に上面電極膜
及び抵抗膜を形成したときの平面図である。
11 is a plan view of the ceramic material plate of FIG. 9 with an upper surface electrode film and a resistance film formed on the upper surface thereof.

【図12】図9のセラミック素材板をブレークしたとき
の平面図である。
FIG. 12 is a plan view when the ceramic material plate of FIG. 9 is broken.

【符号の説明】[Explanation of symbols]

A セラミック素材板 A1 二列セラミック素材板 A4 ,A5 余白部 B1 ,B2 ブレーク用筋目線 1 絶縁基板 2 中心孔 3 抵抗膜 4 電極用突起 5 電極膜 5a 上面電極膜 5c 下面電極膜 5b 側面電極膜A Ceramic material plate A 1 Double-row ceramic material plate A 4 , A 5 Margins B 1 , B 2 Break line 1 Insulating substrate 2 Center hole 3 Resistive film 4 Electrode protrusion 5 Electrode film 5a Top electrode film 5c Bottom electrode Membrane 5b Side electrode membrane

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】多数個の絶縁基板を当該各絶縁基板におけ
る電極用突起が外向きとなるように二列に並べて成る二
列セラミック素材板の複数枚を、これら二列セラミック
素材板の各絶縁基板における電極用突起の箇所において
一体的に連結するようにして一枚のセラミック素材板を
形成し、このセラミック素材板における各絶縁基板の箇
所に、上面電極膜、下面電極膜及び抵抗膜を形成し、次
いで、このセラミック素材板を、前記二列セラミック素
材板にブレークしたのち、この二列セラミック素材板に
おける各絶縁基板の箇所に側面電極膜を形成するにおい
て、前記セラミック素材板として、その各絶縁基板の列
方向の左右両側面に、予め、適宜幅の余白部をブレーク
用筋目線を介して一体的に連接したものを使用し、この
両余白部を、前記上面電極膜及び下面電極膜を形成した
あとでブレークすることを特徴とするチップ型可変抵抗
器用絶縁基板の製造方法。
1. A plurality of two-row ceramic material plates, which are formed by arranging a large number of insulating substrates in two rows so that the electrode projections on each of the insulating substrates face outward, and insulating the two-row ceramic material plates from each other. One ceramic material plate is formed so as to be integrally connected at the electrode projections on the substrate, and an upper surface electrode film, a lower surface electrode film, and a resistance film are formed on the insulating substrate parts of this ceramic material plate. Then, after breaking this ceramic material plate into the two-row ceramic material plate, and forming a side surface electrode film at the location of each insulating substrate in this two-row ceramic material plate, On both the left and right side surfaces of the insulating substrate in the row direction, blanks of an appropriate width are integrally connected in advance through a break line, and both blanks are Chip variable resistor dexterity insulating substrate manufacturing method characterized by break after the formation of the surface electrode film and the lower electrode film.
JP3247743A 1991-09-26 1991-09-26 Manufacture of insulating substrate for chip-shaped variable resistance Pending JPH0590017A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3247743A JPH0590017A (en) 1991-09-26 1991-09-26 Manufacture of insulating substrate for chip-shaped variable resistance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3247743A JPH0590017A (en) 1991-09-26 1991-09-26 Manufacture of insulating substrate for chip-shaped variable resistance

Publications (1)

Publication Number Publication Date
JPH0590017A true JPH0590017A (en) 1993-04-09

Family

ID=17168012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3247743A Pending JPH0590017A (en) 1991-09-26 1991-09-26 Manufacture of insulating substrate for chip-shaped variable resistance

Country Status (1)

Country Link
JP (1) JPH0590017A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100423138C (en) * 2003-06-12 2008-10-01 阿尔卑斯电气株式会社 Variable resistor and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100423138C (en) * 2003-06-12 2008-10-01 阿尔卑斯电气株式会社 Variable resistor and its manufacturing method

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