JPH04160816A - Output circuit - Google Patents

Abstract

PURPOSE:To reduce the current consumption by driving 1st and 4th MOS transistors(TRs) in response to a signal fed as output information and driving 2nd and 3rd MOS TRs in response to a signal resulting from delaying the former signal. CONSTITUTION:When an input signal phi1 changes from a low level to a high level, a TR 1 is turned on, Since an inverting signal inverse of phi1 of an inverter I4 and a delayed inverting signal inverse of phi12 of a NOR gate change respectively from an H level to an L level, TRs 3, 4 are turned off. That is, no through- current flows between a power supply VDD and ground GND at this time. A delayed inverting signal inverse of phi11 of an inverter I3 changes from an H level to an L level, resulting that the delay signal phi12 of a NOR gate NOR1 changes from an L level to an H level. Thus, a through-current between the power supply VDD and ground GND at the final output stage is prevented and power consumption is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit composed of MOS transistors.

[Conventional technology] ・Figure 3 is a circuit diagram showing a conventional output circuit.

Inverter I21 receives input signal φ1 supplied through input terminal 21, inverts it, and outputs it. Inverter ■2□ inputs the output signal of inverter l1al,
This is inverted and a delayed signal φ11 is output. NOR2□ has input signal φ1 at one input terminal.
is input, the delayed signal φ□1 is input to the other input terminal, and the non-OR of both is taken to output an inverted signal φ□.

The N-channel MO8 transistor Tr, □ is connected between the power supply vDD and the output terminal 22, and the delay signal φ11 is input to its gate. The N-channel MO8 transistor Tr2□ is connected between the output terminal 22 and the ground GND, and has an inverted signal φ8. is entered.

Next, the operation of the output circuit configured as described above will be explained.

Input signal φ1, which is output information, changes from Low level to High level.
When it changes to the h level, the delay signal φ□1 becomes the input signal φ1
It changes to High level with a delay. Inverted signal φ,
□ changes to Low level at the same time as the input signal φ1 changes to High level.

As a result, the transistors Tr, , are turned on,
Since the transistor Tr2° is turned off, the output signal φ2 outputted from the output terminal 22 becomes High level.

Next, the input signal φ becomes high level.

When it changes to W level, the delay signal φ11 becomes the input signal φ1.
It changes to the Low level with a further delay. Inverted signal φ1□
becomes H at the same time as the delay signal φ1□ changes to Low level.
Changes to 3gh level. As a result, the transistor T
Since r2t is turned off and transistor Tr2□ is turned on, the output signal φ2 becomes Low level.

Note that in such an output circuit, the inverter I2
□ and the non-OR gate NORws are configured in a ratio configuration to cause the delay signal φ□ and the inverted signal φ1□ to cross low, thereby preventing the power supply vDD and the ground GND from being turned on, and outputting the final output. It reduces the through current of the stage.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional output circuit,
If the inverter I2° and the non-OR gate NOR, □ are configured in a ratio configuration to reduce the through current by taking into consideration manufacturing variations, it is difficult to increase the speed of the output circuit. Conversely, if an attempt is made to speed up the output circuit, there is a problem in that the through current increases and the power consumption increases.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide an output circuit that can reduce power consumption and increase speed.

[Means for Solving the Problems] An output circuit according to the present invention includes first and second MOS transistors connected in series between a power supply terminal and an output terminal, and between the output terminal and a ground terminal. and third and fourth MOS transistors connected in series, the first and fourth MOS transistors are driven in accordance with a signal supplied as output information, and the second and third MOS transistors are driven in accordance with a signal supplied as output information. M of
The OS transistor is characterized in that it is driven in accordance with a delayed signal obtained by delaying the signal.

[Function] In the present invention, the first to fourth MOS transistors are connected in series between the power supply terminal and the ground terminal,
An output terminal is provided between the second and third MOS transistors. The first and fourth MOS transistors are driven according to a signal supplied as output information, and the second and third MOS transistors are driven according to a delayed signal obtained by delaying the signal. . Therefore, the second and third MOS transistors operate later than the first and fourth MOS transistors, thereby preventing a through current from flowing between the power supply terminal and the ground terminal. It is possible to reduce power consumption. Also, unlike an output circuit with a ratio configuration,
Since there is no need to consider ringing or the like when output information changes, the output circuit according to the present invention can be made even faster than conventional circuits.

As the first to fourth MOS transistors, N-channel type or P-channel type can be used as appropriate. In this case, the final output stage N-channel or P-channel MOS
It is sufficient to supply each MO8 transistor with a signal that causes the transistor to properly operate as an output circuit. for example,
When N-channel MOS transistors are used as the first to fourth MOS transistors, a signal serving as output information is input to the gate of the first MOS transistor, and the inverted signal is input to the gate of the fourth MOS transistor. A signal may be input, a delayed signal obtained by delaying the signal may be input to the gate of the second MOS transistor, and a delayed inverted signal obtained by delaying the inverted signal may be input to the gate of the third MOS transistor. Thereby, an appropriate output signal can be obtained at the output terminal according to the signal.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an output circuit according to a first embodiment of the present invention.

Inverter 11 receives input signal φ1 supplied through input terminal 1, inverts it, and outputs it. Inverter 2 receives the output signal of inverter 11, inverts it, and outputs it. Inverter I3 receives the output signal of inverter I2, inverts it, and outputs it. That is, the inverters 11 to 3 are connected in cascade with each other, and invert and delay the input signal φ input to the inverter I□, and output a delayed inverted signal φ11 from the inverter I3. Inverter I4 receives input signal φ1, inverts it, and outputs inverted signal φ1.

Inverters I5 to I7 are interconnected in cascade,
The inverted signal φ1 is inputted to the inverter I5, the inverted signal T is inverted and delayed, and the delayed signal φ11 is outputted from the inverter I7. The non-OR gate NOR receives the delayed inverted signal φ11 of the inverter I3 at one input terminal, and receives the inverted signal φ11 of the inverter I4 at the other input terminal.
1 is input, the non-OR of both is taken, and the delayed signal φ1□ is output.

NOR2 inputs the input signal φ1 to one input terminal, and the inverter I7 to the other input terminal.
It inputs the delayed signal φ□1, takes the non-OR of both, and outputs the delayed inverted signal φ,2.

The N-channel O8 transistor TrzTr2 is connected to the power supply vD.
It is connected in series between D and output terminal 2. The input signal φ1 is input to the gate of the N-channel O8 transistor Tr□. The delay signal φ1□ is input to the gate of the N-channel O8 transistor T r 2. The N-channel O8 transistor TrasTr4 is connected in series between the output terminal 2 and the ground GND. The delayed inverted signal φ1□ is input to the gate of the N-channel O8 transistor T r 3. The N-channel O8 transistor Tr4 has an inverted signal φ1 at its gate.
is entered.

Next, the operation of the output circuit configured as described above will be explained.

When the input signal φ, which is output information, is at a low level, the inverted signal φ1, the delayed inverted signal φ11, and the delayed inverted signal φ1
□ is at High level, and delay signal φ□1 and delay signal φ1□ are at Low level. At this time, transistor Trt*Tr2 is in an off state, and transistor Tr
Since the 3+Tr4 is in the on state, the output signal φ2 at the output terminal 2 is at a low level.

When the input signal φ1 changes from Low level to High level, transistor Tr1 is turned on. After that, the inverted signal φ of inverter ■4.

and non-OR game) N OR2 delayed inverted signal φ12
change from High level to Low level, so that transistors Tr3sTr4 are turned off. That is, at this point, no through current flows between the power supply vDD and the ground GND. After that, the delayed inverted signal φ11 of the inverter I3 goes from High level to Low level.
By changing the level, the non-or game) NO
The delay signal φ1° of Rt changes from Low level to High level. As a result, the transistor T r 2 is turned on, so that the output signal φ2 changes from the Low level to the H1gh level. Also, inverter.

The delayed signal φ□1 changes from Low level to High level.

Next, when the input signal changes from High level to Low level, transistor Tr□ is turned off. That is, at this point, a state is reached in which no through current flows between the power supply vf, D and the ground GND. Thereafter, as the inverted signal φ1 of the inverter I4 changes from Low level to High level, transistor Tr4 turns on, and the delayed signal φ□2 of NOR1 changes from High level to LOW level. do. This turns the transistor Tr2 off.

After that, the delayed inverted signal φ1□ of the inverter I3 becomes 50W.
level to High level, and then the inverter I? The delayed signal φ1. changes from H1gh level to Low level, resulting in a non-logical sum game) N OR2
The delayed inverted signal φ1□ changes from Low level to High level. As a result, the transistor T r 3 is turned on, so that the output signal φ2 changes from High level to Low level.

According to this embodiment, it is not necessary to configure the output circuit with a ratio configuration, and the power supply VDD and ground GN in the final output stage
It is possible to prevent a through current between the capacitor and D, and it is possible to reduce power consumption. Further, unlike the ratio configuration, the output circuit according to this embodiment does not need to take into account ringing when output information changes, so it can be made even faster than the conventional circuit. .

FIG. 2 is a circuit diagram showing an output circuit according to a second embodiment of the present invention.

Inverter ■4 inputs input signal φ1 supplied via input terminal 1, inverts it and outputs an inverted signal T''. Inverters 11 to ■3 are connected in cascade with each other, and inverter Input the inverted signal φ1 into the inverter, invert it and delay it, and output the delayed signal φ from the inverter.
Outputs 13.

The non-AND gate NAND1 inputs the delayed signal φ13 to one input terminal, inputs the input signal φ1 to the other input terminal, takes the non-AND of both, and outputs a delayed inverted signal φ14. The inverters A and I are connected in cascade with each other, and an inverted signal T is inputted to an inverter I6, which is inverted and delayed, and a delayed signal φ is sent from an inverter I7.

Output. NOR2 receives the input signal φ1 at one input terminal, and receives the delayed signal φ1. is input, the non-OR of both is taken, and the delayed inverted signal φ12 is output.

P-channel MO8 transistor T rlSI T r8
are connected in series between the power supply VDD and the output terminal 2. The inverted signal φ1 is input to the gate of the P-channel MO8 transistor T r a . P channel MO
The delayed inverted signal φ14 is input to the gate of the 8 transistor T r e . N-channel MO8 transistors Tr3j to Tr4 are connected in series between the output terminal 2 and the ground GND.

The delayed inverted signal φ1□ is input to the gate of the N-channel MO8 transistor Tr3. N channel MO8
The inverted signal φ1 is input to the gate of the transistor Tr4.

In this embodiment, unlike the first embodiment, a P channel M
O8 transistors TreyTre are connected in series. And P channel MOS transistor TrasTr
6 has an inverted signal T' and a delayed inverted signal T' at their gates, respectively.
π is input. Thereby, the final output stage properly operates as an output circuit similarly to the first embodiment. Therefore, it is possible to prevent a through current between the power supply VDD and the ground GND, and it is possible to reduce poor power consumption.
The speed can be further increased compared to conventional output circuits.

In addition, in the present invention, as in the above embodiment, an N-channel MO8 transistor or a P-channel MO8 transistor is used in the final output stage.
8 transistors can be used as appropriate. for example,
In FIG. 1, N-channel MO8 transistor T r
t can be changed to a P-channel MOS transistor. In such a case, it is sufficient to supply each MO5 transistor with a signal that causes the MOS transistor in the final output stage to operate appropriately.

[Effects of the Invention] As explained above, according to the present invention, the first to fourth MOS transistors are connected in series between the power supply terminal and the ground terminal, and the first and fourth MOS transistors are connected in series. The second and third MOS transistors are controlled by a signal that is output information, and the second and third MOS transistors are controlled by a delayed signal obtained by delaying the input signal.
The OS transistor can be operated with a delay from the first and fourth MOS transistors.

Thereby, it is possible to prevent a through current from flowing between the power supply terminal and the ground terminal, and it is possible to reduce power consumption. Further, unlike the ratio configuration, the output circuit according to the present invention does not need to take into account ringing or the like when output information changes, so it can operate even faster than the conventional circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an output circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram showing an output circuit according to a second embodiment of the present invention, and FIG. 3 is a conventional output circuit. FIG. 1.21; Input terminal, 2, 22; Output terminal, ■ to I
71 I211 L2; Inverter, N0Rs -
N0R2-N0RQ□; Non-OR gate, NANDl
; non-and gate, T r to Tr; T rzt* T r2□; N-channel MO8 transistor, Tra+ Tre; p-channel MO8 transistor 1 N input type l@1l-) 2- Output 7] T#-壬■1~I7-Impari N0RI, N0R2i Jpia! ! 2D'T-Tn~Tr4; Nbuyakil MO5)-Hunnosuf Figure 1

Claims (2)

[Claims] (1) First and second MOS transistors connected in series between the power supply terminal and the output terminal, and third and fourth MOS transistors connected in series between the output terminal and the ground terminal.
transistor, the first and fourth MOS
An output circuit characterized in that the transistor is driven according to a signal supplied as output information, and the second and third MOS transistors are driven according to a delayed signal obtained by delaying the signal. (2) The first to fourth MOS transistors are of N-channel type, the first MOS transistor inputs the signal to its gate, and the fourth MOS transistor inputs the signal to its gate. An inverted signal is input to the second MOS transistor, a delayed signal obtained by delaying the signal is input to the gate of the second MOS transistor, and a delayed inversion signal obtained by delaying the signal is input to the third MOS transistor. The output circuit according to claim 1, wherein a signal is inputted to the output circuit.