JPH06120803A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To increase the working speed and also to reduce the through current by using a 3-state buffer as the output buffer circuit of a CMOS structure. CONSTITUTION:In an output circuit, a 3-state buffer circuit 6a working in a signal changing state is connected in parallel to a buffer circuit 7 which can improve the driving ability of a data flip-flop DFF 4. The circuit 6a works only in a signal changing state and has high impedance in a holding state. Therefore a PMOS transistor TR P4 and an NMOS TR N4 never conduct at one time and meanwhile no through current flows. Thus the driving ability is secured when an output signal changes and also the working speed of the circuit 6a is increased when the sizes of both TR P4 and N4 of the circuit 6a are increased. Therefore the circuit 7 does not require the large driving ability so that the TR sizes can be reduced and the through current can also be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit, and more particularly to a CMOS output buffer circuit.

[0002]

2. Description of the Related Art In a conventional output buffer circuit 1C, as shown in FIG. 4, input data DI input from a data signal input terminal 2 is taken in and held in synchronization with a clock signal CK input from a clock signal input terminal. A flip-flop (hereinafter referred to as DFF4), inverters 5 and 9 for delaying the output inversion Q of the DFF4 by t time, and delayed signal inversion QD and inversion Q are used to form a P-channel type insulated gate field effect transistor (hereinafter, P-type MOS transistor). NAND gate 101, NOR for preventing simultaneous conduction of P9 and N-channel type insulated gate field effect transistor (hereinafter referred to as N-type MOS transistor) N9.
It has a three-state buffer 10 including a gate 102 and an output terminal 8.

Next, the operation will be described. FIG. 5 is an operation waveform diagram for explaining the operation of output buffer circuit 1C in FIG.

According to FIG. 5, when the clock signal CK and the data input DI are input to the data signal input terminal 2 and the clock signal input terminal 3 of the output buffer circuit 1C, respectively, D
The inverted Q waveform is output by the FF4. The inverted QD is the inverted Q delayed by the inverter for t time.
The inverted Q and the inverted QD are input to the NAND gate 101 and the NOR gate 102, respectively, and output signals QA and QO thereof are output.
Is obtained.

The change position of the signal QA and the change position of the signal QO have an interval of t time. By inputting the signal QA to the P-type MOS transistor P9 and the signal QO to the N-type MOS transistor N9, the signals QA and QO are changed. Since the time difference is t, the transistors P9 and N9 do not turn on at the same time, and the data DI does not output the output signal D without lengthening the through current.
It is output as O from the output terminal 8.

[0006]

In this conventional output buffer circuit, the input signals of the P-type MOS transistor and the N-type MOS transistor of the output transistor are delayed to prevent both transistors from conducting at the same time. However, there was a problem that the delay time until output was long.

An object of the present invention is to provide an output buffer circuit having a CMOS structure by eliminating the above-mentioned drawbacks.
By using the state buffer, it is intended to operate at high speed and reduce the through current.

[0008]

The features of the present invention are: a data flip-flop for reading and holding input data in synchronization with a rising edge of a clock signal; and output data of the data flip-flop for output to an output terminal. A buffer, and a first three-state buffer in which the output potential is at a high level or a low level when the clock signal is at a high level, and the output potential is at a high impedance when the clock signal is at a low level. Have
The first three-state buffer and the buffer are connected in parallel between the output terminal of the data flip-flop and the output terminal.

Another feature of the present invention is a data flip-flop that reads and holds input data in synchronization with the rising edge of a clock signal, and the output potential is at a high level or a low level when the clock signal is at a high level. A first three-state buffer in which the state of the output potential is high impedance when the clock signal is low level; and a state of the output potential is high level or low level when the clock signal is low level, A second 3-state buffer in which the state of the output potential becomes high impedance when the clock signal is at a high level, and the first 3-state buffer is provided between the output terminal and the output terminal of the data flip-flop. And the second three-state buffer are connected in parallel.

Still another feature of the present invention is a data flip-flop that reads and holds input data in synchronization with a falling edge of a clock signal, and a buffer that drives output data of the data flip-flop and outputs it to an output terminal. ,
A first three-state buffer in which the state of the output potential becomes high level or low level when the clock signal is low level, and becomes high impedance when the clock signal is high level. The first three-state buffer and the buffer are connected in parallel between the output terminal of the data flip-flop and the output terminal.

Still another feature of the present invention is a data flip-flop that reads and holds input data in synchronization with a falling edge of a clock signal, and a state of output potential is high level or high when the clock signal is low level. A first three-state buffer which is low level and has a high impedance state of the output potential when the clock signal is a high level; and a high or low level state of the output potential when the clock signal is a high level. And a second three-state buffer in which the state of the output potential becomes high impedance when the clock signal is at a low level, and the first three-state buffer is provided between the output terminal and the output terminal of the data flip-flop. A three-state buffer and the second three-state buffer are connected in parallel.

Further, the first, the second and the third
Each of the three-state buffers includes a first P-type MOS transistor, a first N-type MOS transistor, and a second N-type MOS transistor connected in series between a power supply potential and a ground potential. A transistor and the second N
-Type MOS transistor is connected to each gate as a first clock input terminal, and a second clock is provided between the power supply potential and the ground potential.
P-type MOS transistor, third P-type MOS transistor and third N-type MOS transistor are connected in series,
The second P-type MOS transistor and the third N-type M
The gates of the OS transistors are connected to form a second clock input terminal, and the gates of the first N-type MOS transistor and the third P-type MOS transistor are connected to form a data input terminal, and the first clock input terminal is connected to the first clock input terminal. The drains of the P-type MOS transistor and the first N-type MOS transistor are connected to the gate of the fourth P-type MOS transistor whose source is connected to the power supply potential, and the third P-type MOS transistor and the third P-type MOS transistor are connected. The drain of each of the N-type MOS transistors 3 is a fourth N-type MO transistor whose source is connected to the ground potential.
The fourth P-type MO is connected to the gate of the S-transistor.
The drain of the fourth N-type MOS transistor is connected to the S transistor to serve as an output terminal, and the output signal of the data flip-flop is connected to the first input terminal of the data input terminal.
The clock input terminal may be configured to input the normal or inverted signal of the clock, and the second clock input terminal may be configured to input the inverted signal or the normal signal.

[0013]

Next, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the output buffer circuit of the present invention.

The output buffer circuit 1a of this embodiment is shown in FIG.
, The DFF4 that reads and holds the input data DI in synchronization with the rising edge of the clock signal CK, and the DFF4.
A buffer 7 for driving the output data of No. 4 and outputting it to the output terminal 8, and an output terminal B when the clock signal CK is at a high level.
When the output potential of OH becomes high level or low level and the clock signal CK is low level, the output terminal BOH
The state of the output potential becomes high impedance (first
No.) 3-state buffer 6a.

The 3-state buffer 6a has a data input terminal B.
I1, a clock input terminal C1, an inverting C1, an output terminal BOH, a buffer 7 has an input terminal VI and an output terminal VO, and a 3-state buffer 6a and a buffer are provided between the output terminal Q of the DFF 4 and the output terminal 8. 7 and 7 are connected in parallel.

At this time, the output end Q of the DFF4 is connected to the data input end BI1, the output end inversion Q is connected to the input end VI of the buffer 7, and the clock signal input terminal 3 is connected to the DFF.
4 is connected to the clock terminal CK and the clock input terminal C1 of the 3-state buffer, and the output terminal of the inverter 5 for inverting the clock signal is connected to the clock input terminal inverting C1 and the output terminal VO of the buffer 7 and the output of the 3-state buffer. Edge B
OH is connected to the output terminal 8.

Further, the 3-state buffer 6a includes a (first) P-type MOS transistor P1 and a (first) N-type MOS transistor N1 between the power supply potential (VDD) and the ground potential.
And (second) N-type MOS transistor N2 are connected in series, and the gates of P-type MOS transistor P1 and N-type MOS transistor N2 are connected to form a (first) clock input terminal C1.

Further, between the power supply potential and the ground potential (second)
P-type MOS transistor P2, (third) P-type MOS transistor P3, and (third) N-type MOS transistor N
3 are connected in series and the gates of the P-type MOS transistor P2 and the N-type MOS transistor N3 are connected (second
The clock input terminal is inverted C1.

N-type MOS transistor N1 and P-type MOS
Data input terminal B by connecting each gate of the transistor P3
I1.

P-type MOS transistor P1 and N-type MOS
The drains of the transistors N1 are commonly connected (connection point BP1), and the sources are connected to the gates of the (fourth) P-type MOS transistors P4 connected to the power supply potential.
The drains of the transistor P3 and the N-type MOS transistor N3 are commonly connected (connection point BN1), and the source is connected to the ground potential (fourth) N-type MOS transistor N4.
Connect with the gate of.

P-type MOS transistor P4 and N-type MOS
Connect each drain of the transistor N4 to the output terminal BOH
And The data input terminal BI1 is supplied with the output signal of the output terminal Q of the DFF4, the clock input terminal C1 is supplied with the normal or inverted signal of the clock CK, and the clock input terminal C1 is supplied with the inverted signal or normal signal. Enter and configure.

Next, the operation of this embodiment will be described.

FIG. 3 is an operation waveform diagram for explaining the operation of the circuit in FIG.

When the clock signal CK and the data input DI shown in FIG. 3 are input to the circuit, the DFF 4 obtains the normal output signal Q from the output end Q and the output signal inversion Q from the output end inversion Q.

The input terminal VI of the buffer 7 is connected to the inversion Q, and the output signal VO shown in FIG. 3 is obtained from the output terminal VO shown in FIG. The output signal CK and the inverted CK of the DFF 4 are input to the data input terminal BI1, the clock input C1, and the inverted C1 of the 3-state buffer 6a, respectively.

When the clock signal CK is at the low level, the clock input terminal C1 is at the low level, the clock input terminal inversion C1 is at the high level, and the P-type MOS transistors P1 and N-type MO are provided.
Since the S-transistor N3 becomes conductive, the N-type MOS transistor N2 and the P-type MOS transistor P2 become non-conductive, the input terminal BP1 becomes high level, and the input terminal BN1 becomes low level, the output terminal BOH of the 3-state buffer 6a becomes The high impedance state Z is set.

When the clock signal CK is at high level, the input terminal C1 is at high level and the input terminal inversion C1 is at low level,
The P-type MOS transistors P1 and N-type MOS transistors N3 become non-conductive, and the N-type MOS transistors N2 and P
The type MOS transistor P2 becomes conductive.

At this time, if the output signal of the output terminal Q of the DFF 4 is at high level, the data input terminal BI1 becomes high level, the N-type MOS transistor N1 becomes conductive, and the P-type MOS transistor becomes conductive.
Transistor P3 becomes non-conductive. The connection point BP1 holds the low level, and the connection point BN1 holds the low level which is the potential when the clock signal CK is at the low level.
Only the S transistor P4 becomes conductive, and the potential of the output terminal BOH becomes high level.

When the output signal of the output terminal Q of the DFF4 is low level, the potential of the data input terminal BI1 becomes low level, the N-type MOS transistor N1 is non-conducting, and the P-type MOS transistor N1 is non-conductive.
The transistor P3 becomes conductive.

Then, the connection point BP1 holds the high level which is the potential when the clock signal CK is at the low level, and the connection point BN1 becomes the high level, so that only the N-type MOS transistor N4 becomes conductive and the output terminal BOH of the output terminal BOH. The potential goes low.

Therefore, the potential of the output terminal BOH becomes as shown in FIG. 3, and operates only when the potential of the clock signal input terminal C1 is high level and the clock level of the clock signal input terminal inversion C is low level.

The output terminal 8 of the output buffer circuit 1 has 3
Since the output end BOH of the state buffer 6a and the output end VO of the buffer 7 are commonly connected, the output signal D
O1 has the output waveform shown in FIG.

From the above results, in the first embodiment, the buffer 7 and the 3-state buffer 6a are connected in parallel, so that the P-type MOS transistor P4 and the N-type MOS transistor N4 of the 3-state buffer 6a are penetrated. Before changing output data, P-type MOS is used to prevent current from flowing.
The transistors P4 and N-type MOS transistor N4 are turned off. Therefore, there is an effect of reducing the shoot-through current while maintaining the driving ability when the output data changes.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a circuit diagram showing a second embodiment of the output buffer circuit of the present invention.

The output buffer circuit 1b of this embodiment is shown in FIG.
As shown in, the DFF 4 that reads and holds the input data DI in synchronization with the rising of the clock signal CK, and the state of the output potential becomes the high level or the low level when the clock signal CK is at the high level, and the clock signal is at the low level. And the three-state buffer 6a whose output potential becomes high impedance when, and the output potential becomes high level or low level when the clock signal CK is at low level,
It has a 3-state buffer 6b in which the state of the output potential becomes high impedance when the clock signal CK is at a high level.

The 3-state buffer 6a has a data input terminal B
I1, a clock input terminal C1, an inverting C1, and an output terminal BOH are provided, and the 3-state buffer 6b has a data input terminal BI2.
The clock input terminal C2, the inverting C2, and the output terminal BOL are provided, and the 3-state buffer 6a and the 3-state buffer 6b are connected in parallel between the output terminal Q of the DFF 4 and the output terminal DO.

At this time, the output terminal Q of the DFF4 is connected to the data input terminal BI1 and the data input terminal BI2, and the clock signal input terminal 3 is connected to the clock terminal CK of the DFF4 and the clock input terminals C1 and C2 of the 3-state buffer. The output terminal of the inverter 5 for inverting the clock signal is connected to the clock input terminals C1 and C2, and the output terminals BOH and BOL are commonly connected to the output terminal 8.

Since the internal structure of the 3-state buffer 6b is the same as that of the 3-state buffer 6a described in the first embodiment, the description thereof will be omitted.

Next, the operation of the second embodiment will be described.

In FIG. 2, the portion of the buffer 7 of FIG. 1 is replaced with a 3-state buffer 6b, and the inverted clock signal CK2 and the inverted clock signal CK2 are applied to the clock input terminal C2 and the inverting input terminal C2 so as to operate only when holding data. You are typing. The 3-state buffer 10 is a 3-state buffer 6a.
Since the clock input is connected in reverse when compared to
When the clock signal CK is at a high level, the potential of the output terminal BOL becomes high impedance and has a waveform as shown in FIG. Since the three-state buffers 6a and 6b are connected in parallel, the output of the output buffer circuit 1b has an output waveform DO2. In the second embodiment, when the output signal changes in the buffer 7 of the first embodiment, the P-type MOS transistor P5 and the N-type MOS transistor N5 are used.
It is possible to eliminate the penetrating current that has flowed during the period.

[0043]

As described above, in the output buffer circuit of the present invention, the buffer circuit for outputting the output signal of the data flip-flop which receives and holds the data by the clock signal and the 3-state buffer circuit are connected in parallel, The 3-state buffer circuit operates when the data changes, and becomes high impedance when the data is held.

By connecting two three-state buffer circuits that output the output signal of the data flip-flop to the output terminals in parallel, one of the three-state buffer circuits operates when the data changes and is high when the data is held. The other three-state buffer circuit operates so as to hold data, and has a high impedance when data changes. Therefore, since a through current does not flow between the P-type MOS transistor and the N-type MOS transistor, which are the output transistors of the 3-state buffer, the current consumption can be reduced, and the use of a large-sized transistor enables high-speed operation with a short delay time. Has the effect of being

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output buffer circuit showing a first embodiment.

FIG. 2 is a circuit diagram of an output buffer circuit showing a second embodiment.

FIG. 3 is an operation waveform diagram for explaining the first and second embodiments.

FIG. 4 is a circuit diagram of a conventional output buffer circuit.

FIG. 5 is an operation waveform diagram for explaining a conventional output buffer circuit.

[Explanation of symbols]

1a, 1b Output buffer circuit 2 Data signal input terminal 3 Clock signal input terminal 4 Data flip-flop 5 Inverter 22, 24, 31, 32, 37, 38 N-type MOS transistor 6a, 6b, 10 3 State buffer 7 Buffer 8 Output terminal P1 to P5 P-type MOS transistor N1 to N5 N-type MOS transistor C1, inversion C1, C2, inversion C2 clock signal input end BI1, BI2 data signal input end DI input data CK, inversion CK clock signal BOH, BOL output end VI buffer 7 input terminal VO buffer 7 output terminal

Claims (5)

[Claims] 1. A data flip-flop for reading and holding input data in synchronization with a rising edge of a clock signal,
A buffer for driving the output data of the data flip-flop and outputting it to the output terminal; and a state of the output potential becomes a high level or a low level when the clock signal is at a high level, and a buffer when the clock signal is at a low level. A first three-state buffer whose output potential is in a high impedance state, and the first three-state buffer and the buffer are connected in parallel between the output terminal of the data flip-flop and the output terminal. An output buffer circuit characterized by being configured as follows. 2. A data flip-flop for reading and holding input data in synchronization with a rising edge of a clock signal,
A first three-state buffer in which the output potential is at a high level or a low level when the clock signal is at a high level, and the output potential is at a high impedance when the clock signal is at a low level; A second three-state buffer in which the state of the output potential is high level or low level when the signal is low level, and the state of the output potential is high impedance when the clock signal is high level; An output buffer circuit, characterized in that the first three-state buffer and the second three-state buffer are connected in parallel between an output terminal and an output terminal of a data flip-flop. 3. A data flip-flop for reading and holding input data in synchronization with a rising edge of a clock signal,
A buffer for driving the output data of the data flip-flop and outputting it to the output terminal; and a state of the output potential becomes a high level or a low level when the clock signal is at a low level, and a buffer when the clock signal is at a high level. A first three-state buffer whose output potential is in a high impedance state, and the first three-state buffer and the buffer are connected in parallel between the output terminal of the data flip-flop and the output terminal. An output buffer circuit characterized by being configured as follows. 4. A data flip-flop for reading and holding input data in synchronization with a falling edge of a clock signal,
A first three-state buffer in which the state of the output potential is high level or low level when the clock signal is low level, and the state of the output potential is high impedance when the clock signal is high level; A second three-state buffer in which the state of the output potential becomes a high level or a low level when the signal is at a high level, and the output potential state becomes a high impedance when the clock signal is at a low level; An output buffer circuit, characterized in that the first three-state buffer and the second three-state buffer are connected in parallel between an output terminal and an output terminal of a data flip-flop. 5. The first, second, and third three-state buffers each include a first P-channel type insulated gate field effect transistor and a first N-channel type insulated gate between a power supply potential and a ground potential. A field effect transistor and a second N-channel type insulated gate field effect transistor are connected in series, and each gate of the first P-channel type insulated gate field effect transistor and the second N-channel type insulated gate field effect transistor is connected. A second P-channel type insulated gate field effect transistor, a third P-channel type insulated gate field effect transistor, and a third N-channel type between the power supply potential and the ground potential. An insulated gate field effect transistor connected in series, and the second P-channel type insulated gate field effect transistor and the third Each gate of the N-channel type insulated gate field effect transistor is connected to serve as a second clock input terminal, and each of the first N-channel type insulated gate field effect transistor and the third P-channel type insulated gate field effect transistor is connected. Connect the gate to the data input terminal,
The drain of each of the first P-channel type insulated gate field effect transistor and the first N-channel type insulated gate field effect transistor has a source connected to the power supply potential of a fourth P-channel type insulated gate field effect transistor. A fourth N-channel type isolation having a source connected to the ground potential and connected to a gate, and the drains of the third P-channel type insulated gate field effect transistor and the third N-channel type insulated gate field effect transistor are connected to the ground potential. The data input terminal is connected to the gate of the gate field effect transistor, and the drains of the fourth P-channel type insulated gate field effect transistor and the fourth N-channel type insulated gate field effect transistor are connected to form an output terminal. The output signal of the data flip-flop to the first clock input terminal 4. A normal rotation signal or a reverse rotation signal of a clock, and the second clock input terminal is configured to input the reverse rotation signal or the normal rotation signal, respectively. Alternatively, the output buffer circuit according to claim 4.