JPH08307237A - Bus connection circuit - Google Patents

Abstract

PURPOSE: To decrease the scale of an output buffer and to reduce the current consumption. CONSTITUTION: A input signal IN is given to each bus buffer 20 of a bus connection circuit 10. Two inverters 21, 22 of the bus buffer 20 provide an output of a noninverting input signal IN. An output signal OUT is given to a SW. The SW is closed when a clock ϕ is at 'H' and open when the clock ϕ is at 'L'. When the logic level of the output signal OUT is not stable and the clock ϕ is at 'L', the output signal OUT is not received by the SW, but when the clock $ is at 'H', the output signal OUT is received by the SW. The received signal is latched at the leading of the clock ϕ and provided to a block 40 via a D-F/F30 as an output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus connecting circuit for connecting internal blocks in a semiconductor integrated circuit (hereinafter referred to as IC).

[0002]

2. Description of the Related Art Generally, blocks of ICs are connected through bus lines. This bus line is connected between blocks through a bus buffer having an inverter composed of one or more CMOSs. This bus buffer has a large W / L (W: channel width, L: channel length, hereinafter referred to as dimension), and increases the output current to prevent the waveform from blunting on the bus line. The time for the through current to flow is shortened.

[0003]

However, the conventional bus connection circuit has the following problems. (A) When the dimension of the bus buffer is increased, the current flowing through the bus buffer increases, the power consumed by the bus buffer increases, and as a result, the power consumption of the entire chip also increases. (B) When the dimension of the bus buffer is increased, there is also a problem that the chip area occupied by the bus buffer also increases.

[0004]

In order to solve the above-mentioned problems, a first aspect of the present invention is to provide a block between blocks in a semiconductor integrated circuit.
A bus connection circuit having one or a plurality of inverters and outputting an output signal output from the block in response to a clock to the block following the block through the bus buffer, A circuit is provided. That is, it is turned on or off based on a clock, turned off when the logic level of the output signal of the bus buffer is in the undetermined state, and turned on when the logic level of the output signal of the bus buffer is in the confirmed state. A switch circuit that outputs the output signal of the bus buffer and a signal capturing circuit that captures the output signal from the switch circuit based on the clock are provided.

[0005]

According to the first aspect of the present invention, since the bus connection circuit is configured as described above, the switch circuit turns on when the logical level of the output signal of the bus buffer is determined, and the output signal of the bus buffer is turned on. Is output. The signal capturing circuit captures the signal output from the switch circuit in synchronization with the clock. Since the logic level of the signal taken in by this signal taking-in circuit is fixed, when it is constituted by CMOS in the taking-in circuit, PMOS, NMO
S does not turn on at the same time and a through current does not flow. Therefore, the above problem can be solved.

[0006]

First Embodiment FIG. 1 is a block diagram of a bus connection circuit according to a first embodiment of the present invention. The bus connecting circuit of the first embodiment differs from the conventional bus connecting circuit in that it is a bus buffer having a small first dimension. Secondly, since the bus buffer having a small dimension is used, in order to suppress the flow of the through current due to the larger dullness than the conventional one,
That is, the switch circuit which is turned on for the first time when the logic level of the output signal of the bus buffer is fixed and the signal fetch circuit which fetches the output of this switch circuit are constituted by the data flip-flops. As shown in FIG. 1, the bus connection circuit 10 is connected to the output side of the block 1 of the IC and receives the input signal IN. The bus connection circuit 10 has a bus buffer 20 for each bus line. A data flip-flop (hereinafter referred to as DF / F) 30 is connected to the output side of the bus connection circuit 10. D
The output signal OUT of the bus connection circuit 10 and the clock φ are input to the D terminal and the clock terminal of the −F / F 30, respectively. The block 4 of the IC is provided on the output side of the D-F / F 30.
0 is connected. In the block 40, DF / F3
The output signal S30 from the 0 terminal is input.

FIG. 2 is a block diagram of the bus buffer 20 shown in FIG. As shown in FIG. 2, the bus buffer 20 is composed of inverters 21 and 22. The inverter 21 is a P-channel MOS transistor (hereinafter referred to as PMO
21-1 and an N-channel MOS transistor (hereinafter referred to as NMOS) 21-2. The inverter 22 includes an NMOS 22-1, a PMOS
22-2. PMOS 21-1, 2
The dimensions of the elements 2-1 and NMOSs 21-2 and 22-2 are made smaller from the viewpoint of reducing power consumption and chip occupying area. This dimension is a DF that satisfies the standard of the propagation delay time of the bus buffer 20 and further receives the output of the bus buffer 20.
The minimum size that can drive the first-stage gate of / F30 is sufficient. The input signal IN is connected to the gates of the PMOS 21-1 and the NMOS 21-2. PMOS 21
A power source potential (hereinafter, referred to as V _DD ) and a drain of the NMOS 21-1 are connected to the source and drain of −1, respectively. A ground potential (hereinafter, referred to as GND) is connected to the source of the NMOS 21-2. PMOS2
2-1 and the gate of the NMOS 22-2 have the PMOS 21
-1 and the drains of the NMOS 21-2 are connected. The source and drain of the PMOS 22-1 have V _DD ,
The drains of the NMOS 22-2 are connected to each other. GND is connected to the source of the NMOS 22-2. An output signal OUT is output from the drains of the PMOS 22-1 and the NMOS 22-2.

FIG. 3 is a block diagram of the D-F / F 30 shown in FIG. This D-F / F30 is a switch (hereinafter, SW
31-1 and 31-2, inverters 32-1 and 3
2-2, SW33-1, 33-2, inverter 34-
1 and 34-2. SW31-1, 3
Reference numerals 1-2, 33-1 and 33-2 are bidirectional switches in which PMOS and NMOS are connected in parallel, and the inverter 3
2-1, 32-2, 34-1, 34-2 are composed of CMOS. SW31-1 is a switch circuit, SW31-2 is a circuit that captures the signal of the inverter 32-2, SW33-1 is a circuit that captures the signal of the inverter 32-1, and SW33-2 is a circuit that captures the signal of the inverter 34-2. Is. SW31-1 PMOS, NM
The clock φ _B and the clock φ are input to the gate of the OS. Data D is input to one terminal of SW31-1, and inverter 32-1 and SW31-2 are connected to the other terminal. SW31-2 PMO
Clock φ and clock φ _B are provided to the gates of S and NMOS.
Is entered. The output side of the inverter 32-2 is connected to one terminal of the SW 31-2, and the other terminal has an S terminal.
The input side of W31-1 and the inverter 32-1 are connected. SW31- is provided on the input side of the inverter 32-1.
1 and SW 31-2 are connected, and their inverter 32-
SW33-1 and the inverter 32-
2 is connected.

A clock φ and a clock φ _B are input to the gates of the PMOS and NMOS of SW33-1. SW
The output side of the inverter 32-1 and the input side of the inverter 32-2 are connected to one terminal of 33-1, and the input sides of the SW 33-2 and the inverter 34-1 are connected to the other terminal. SW33-2 PMOS and NMO
The clock φ _B and the clock φ are input to the gate of S. The inverter 34-is connected to one terminal of the SW 33-2.
The input side of 1 and SW33-1 are connected, and the output side of the inverter 34-2 is connected to the other terminal. SW33-1 and SW are provided on the input side of the inverter 34-1.
33-2 is connected to the output side of the inverter 34
-2 is connected. The SW 33-2 is connected to the output side of the inverter 34-2. SW31-1, 3
3-2 turns on when the clock φ is “H”, and turns off when the clock φ is “L”. SW31-2, 33-1
Turns on when the clock φ is “L”, and turns off when the clock φ is “H”.

FIG. 4 is a time chart of FIG. The operation of the bus connection circuit of FIG. 1 will be described below with reference to FIG. The input signal IN is input from the block 1 to the bus buffer 20 in synchronization with the clock φ. here,
It is assumed that the input signal IN changes to "L", "H", "L". At this time, when the input signal IN changes from "H" to "L", the period of "H" is T0 period (clock φ is "L"), T1 period (clock φ is "H"), and "L". The period "" is a T2 period (clock φ is "L") and a T3 period (clock φ is "H"). The input signal IN is input to each bus buffer 20 of the bus connection circuit 10. In the bus buffer 20, the two inverters 21 and 22 output the input signal IN in a positive phase. Here, the inverter 21,
Since the dimension of the transistor constituting 22 is made small, the rising or falling of the input signal IN is delayed, and the output signal OUT thereof is dulled.
As shown in, the output signal OUT has its logic level fixed to "H" during the period T1 and has its logic level fixed to "L" during the period T3. Therefore, the intermediate point T _A of the period T0,
At the intermediate time point T _C of the period T2, the logic level of the output signal OUT is in an undetermined state, and the PMO forming the CMOS is formed.
Both S and NMOS are turned on, and V _DD to G
A through current flows through ND through PMOS and NMOS. However, it will be described below that the shoot-through current does not flow because the input gate of the output signal OUT is the D-F / F 30 shown in FIG.

The output signal OUT is SW31-1 in FIG.
Input to the source. The SW 31-1 is turned on in a period T1 in which the clock φ is “H”, and is turned off in a period T0 in which the clock φ is “L”. That is, in the period T0, the gate of the inverter 32-1 is "L".
Is still input, only the PMOS constituting the inverter 32-1 is in the ON state, and the NMOS is in the OFF state, so that the through current does not flow. In the period T1, SW31-
1 is turned on, the SW 31-1 inputs “H” to the gate of the inverter 32-1 through the output signal OUT, the NMOS forming the inverter 32-1 is turned on, and “L” is output to the inverter 32-1. Will be output.
Since the SW 33-1 is off in the period T1, the output of the inverter 34-1 does not change and its output S30 remains "L". In the period T2, SW31-2 and SW
33-1 are both turned on, and "L" output from the inverter 32-1 in the period T1 is changed to the inverter 32-
1. Feedback from the inverter 32-2, SW33-
The output of "L" is maintained at 1. Then, the "L" signal input to the SW 33-1 is inverted by the inverter 34-1, and the output signal S30 becomes "H". Also, the period T
In No. 2, the SW 31-1 is in the off state, so that no through current flows through the inverter 32-1 at the time T _C. In the period T3, the SWs 31-1 and 33-2 are both turned on. In the SW 33-2, the signal of “H” output from the inverter 34-1 in the period T2 is the inverter 3
Return to the inverter 34-1 through 4-2,
The output of "H" is maintained. Further, the SW 31-1 outputs "L" to the gate of the inverter 32-1 through "L" of the output signal OUT.

As described above, the first embodiment has the following advantages. (A) Since the dimension of the bus buffer 20 of the bus connection circuit 10 is made small, the current flowing through the bus buffer 20 becomes small, the power consumption becomes small, and the chip area occupied by the bus buffer 20 can be made small. it can. (B) Since the dimension of the bus buffer 20 is made small, the output signal OUT of the bus buffer 20 is blunted. However, after the output signal OUT rises to "H" by the D-F / F 30, it is latched or "L". While the output signal OUT is latched after falling to "" and the SW31-1 is in the OFF state while the waveform of the output signal OUT is blunt, a through current does not flow, and power consumption is reduced.

Second Embodiment FIG. 5 is a configuration diagram of a bus connection circuit according to a second embodiment of the present invention. The bus connecting circuit according to the second embodiment differs from the bus connecting circuit according to the first embodiment in the first place.
That is, the dimension of the bus buffer 20 of 0 is made smaller than the dimension of the bus buffer of the first embodiment. Secondly, since the dimension of the bus buffer 20 is further reduced, the output signal OUT of the bus buffer 20 is further dulled. Therefore, the duty variable circuit 50 that varies the duty of the clock DI in order to delay the timing of latching the output signal OUT. Is provided. As shown in FIG. 5, the bus connection circuit 10 is provided between the block 1 and the block 40. The bus connection circuit 10 has a bus buffer 20 for each bus line. The bus buffer 20 has the same structure as that of FIG. 2, but is made smaller than the dimension of the transistors forming the bus buffer of the first embodiment.
The output side of the bus connection circuit 10 is connected to a D-F / F 30 having the same configuration as in FIG. The output signal OUT of the bus connection circuit 10 and the output signal DO of the duty variable circuit 50 are input to the D terminal and the clock terminal of the D-F / F 30, respectively. The clock DI is input to the duty variable circuit 50. In the block 40, DF / F
The output signal S30 from the Q terminal of 30 is input.

FIG. 6 is a time chart of FIG. The operation of the bus connection circuit of FIG. 5 will be described below with reference to FIG. The input signal IN is input from the block 1 to the bus buffer 20 in synchronization with the clock DI. The input signal IN is “L” during the period T ₁₀ , “H” during the period T ₁₁ , and the period T
"H" at _12, "L" in the period T _13, and changed to "L" in the period T _14. The input signal IN is input to each bus buffer 20 of the bus connection circuit 10. In the bus buffer 20, the input signal IN is generated by the two inverters 21 and 22.
Is output in the normal phase. Here, since the dimensions of the transistors forming the inverters 21 and 22 are made smaller than in the first embodiment, the rise or fall of the input signal IN is delayed compared to that in the first embodiment, and the output signal O
UT is, as shown in FIG. 6, "L" and from the "H" is determined to "H" in the period of the second half of the period T _12, the "H" to "L", the latter half of the period T ₁₄ Is determined to be "L" during the period. Therefore, in the first half of the periods T ₁₂ and T ₁₄ , the output signal OUT is blunted, its logic level is in an undetermined state, and when such a signal is input to an inverter or the like,
A through current flows. For example, at times T _A and T _C in FIG. 6, when this signal is input to the gate of the inverter, a through current flows. However, the input gate of the output signal OUT is the D-F / F30 shown in FIG.
It will be described below that the through current does not flow because the duty variable circuit 50 uses the clock input of 0.

The clock DI is a variable duty circuit 50.
As a result, the "H" period is shortened by T _P , and the "L" period is lengthened accordingly, and as shown in FIG. 6, each of the periods T ₁₀ , T ₁₂ , and T ₁₄ is "H". Is shortened by T _P, and the timing of changing to “H” is delayed by T _P (the timing of changing to “L” does not change). Therefore, in the first half of each of the periods T ₁₂ and T _{14 in which} the output signal OUT is blunted and its logic level is in the undetermined state, the output signal DO of the tutue variable circuit 50 remains “L”,
SW31-1 is off. Therefore, during that period, since the level of the input signal of the input gate of the inverter 32-1 does not change, a through current does not flow. In the latter half of the period T _{12 in which} the output signal OUT is “H”, the SW 31-1 is in the ON state, the output signal OUT is passed through the SW 31-1, and DF is generated at the falling timing of the clock DO. The output signal S30 of / F30 becomes "H". This "H" is maintained until the timing when the clock DI falls. Further, during the first half of the period T ₁₄ , the clock DO is “L”, so SW31
-1 remains in the off state, and the through current does not flow in the inverter 32-1. As described above, the second embodiment has the following advantages.

(A) Since the dimension of the bus buffer 20 of the bus connection circuit 10 is further larger than that of the first embodiment, the area of the bus buffer 20 can be reduced. (B) Since the dimension of the bus buffer 20 is smaller than that of the first embodiment, the output signal OUT of the bus buffer 20 is further rounded.
Since the period of "H" is shortened by 0, a through current does not flow, so the power consumption becomes small. The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) In the first and second embodiments, the input signal IN has been described as changing in synchronization with the falling edge of the clock, but it may be changed in synchronization with the rising edge of the clock. At this time, SW31- of DF / F30
1, 33-2 is turned on by "L" and turned off by "H", and SW31-2, 33-1 are turned on by "H",
It shall be turned off at "L". (2) In the first and second embodiments, the bus buffer in which two stages of inverters are connected has been described, but if the logic as a whole matches, only one stage of the inverter or the NAND gate,
It may be a NOR gate. (3) In the first and second embodiments, the D-F / F shown in FIG. 3 has been described as an example. However, in both the D-F / F and the latch, the D input is connected to the analog switch D-.
Anything can be used as long as it has a function of F / F and latch. For example, SW31-1, inverters 32-1, 3 in FIG.
It may be a latch circuit composed of 2-2. (4) Duty variable circuit 50 in the second embodiment
The pulse width to be shortened in 1 may be appropriately changed according to the rounding of the output signal OUT. Further, the variable duty circuit 50 does not require any particular precision, and thus may be of any type.

[0017]

As described in detail above, the first and second
According to the invention, since the switch circuit and the fetch circuit are provided, the shoot-through current can be suppressed even if the waveform of the output signal of the bus buffer is blunt. Further, the dimension of the bus buffer can be reduced, power consumption can be reduced, and the occupied area of the bus buffer can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a bus connection circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a bus buffer in FIG.

FIG. 3 is a configuration diagram of a D-F / F in FIG.

FIG. 4 is a time chart of FIG.

FIG. 5 is a configuration diagram of a bus connection circuit according to a second embodiment of the present invention.

FIG. 6 is a time chart of FIG.

[Explanation of symbols]

 1,40 block 10 bus connection circuit 20 bus buffer 30 DF / F 50 duty variable circuit

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor, Hisashi Nakamura 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (2)

[Claims] 1. A bus buffer having one or a plurality of inverters is disposed between blocks in a semiconductor integrated circuit, and an output signal output from the block in response to a clock is passed through the bus buffer. In the bus connection circuit for outputting to the block in the subsequent stage, it is turned on or off based on the clock, and is turned off when the logic level of the output signal of the bus buffer is in an undetermined state, and the logic of the output signal of the bus buffer is output. A switch circuit that outputs an output signal of the bus buffer when the level is in a definite state and outputs a signal output from the bus buffer; and a signal capturing circuit that captures an output signal from the switch circuit based on the clock. And bus connection circuit. 2. A bus buffer having one or a plurality of inverters is arranged between blocks in a semiconductor integrated circuit, and an output signal output from the block in response to a clock is passed through the bus buffer. In a bus connection circuit for outputting to a subsequent block, when the logical level of the output signal of the bus buffer becomes a definite state, the duty variable for changing the pulse width of the clock to "H" or "L" A circuit, a switch circuit that is turned on or off based on the pulse width-changed clock, and a signal acquisition circuit that acquires an output signal from the switch circuit based on the pulse-width changed clock, Bus connection circuit characterized by