JP5023165B2 - セラミックス回路基板 - Google Patents
セラミックス回路基板 Download PDFInfo
- Publication number
- JP5023165B2 JP5023165B2 JP2010024694A JP2010024694A JP5023165B2 JP 5023165 B2 JP5023165 B2 JP 5023165B2 JP 2010024694 A JP2010024694 A JP 2010024694A JP 2010024694 A JP2010024694 A JP 2010024694A JP 5023165 B2 JP5023165 B2 JP 5023165B2
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- Prior art keywords
- circuit board
- ceramic
- metal
- substrate
- bonding
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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- C04B37/023—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles characterised by the interlayer used
- C04B37/026—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles characterised by the interlayer used consisting of metals or metal salts
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
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- C04B2235/786—Micrometer sized grains, i.e. from 1 to 100 micron
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- Organic Chemistry (AREA)
- Structural Engineering (AREA)
- Materials Engineering (AREA)
- Structure Of Printed Boards (AREA)
- Ceramic Products (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
Description
参考例1は、表1に示すNo.1ないしNo.15の試料に基づいて説明する。試料No.1ないし試料No.9は、AlN基板(熱伝導率k=170W/mK)をセラミックス基板とし、試料No.10ないし試料No.15は、Si3N4基板(k=70W/mK)をセラミックス基板として用いた。
本比較例1では、表1に示すNo.16ないしNo.20の試料に基づいて説明する。試料No.16,18,20]はAlN基板(k=170W/mK)、試料No.17,19はSi3N4基板(k=70W/mK)をセラミックス基板として用いた。
本実施例2は、表2に示すNo.21ないし試料No.29およびNo.31の試料に基づいて説明する。試料No.21ないし試料No.25、試料No.28ないし試料No.29および試料No.31は、AlN基板(k=170W/mK)をセラミックス基板として用いた。また、試料No.26は、Si3N4基板(k=70W/mK)を用い、参考例の試料No.27は、Al2O3基板をセラミックス基板として用いた。これらのセラミックス基板の上下面に、表2に示すAlを主成分とし、Siを0.1〜2wt%添加したAl−Siろう材ペーストをスクリーン印刷した。
本比較例2では、表2に示すNo.32およびNo.33の試料に基づいて説明する。試料No.32はAlN基板(k=170W/mK)を用い、試料No.33はSi3N4基板(k=70W/mK)をセラミックス基板として用いた。
本実施例3は、表3に示すNo.34ないしNo.39の試料に基づいて説明する。
比較例3は、表3に示すNo.40およびNo.41の試料に基づいて説明する。そして、実施例3の第1接合層の形成のみを行い、第2接合層の形成は行わず、以下のように製造した。
図4は、単層構造のセラミックス回路基板の構成を示す断面図である。この図4に示すように、参考形態のセラミックス回路基板1aは、窒化珪素基板2の両面にアルミニウム回路板3,4を接合した単層基板構成とされている。
板とした場合に比し、熱サイクルが付加された際に窒化珪素基板に発生するクラックの抑制効果を大幅に向上でき、それにより特に耐用性の面での有用性を高めることができる。
厚さ0.5mm、純度99%以上のアルミニウム板を用意し、エッチングによりこのアルミニウム板の外周縁部より1mmまでの部分の厚さを0.25mmとして、図18に示すように薄肉部3bを形成した。その後、このアルミニウム板を厚さ0.7mmの窒化アルミニウム基板に直接接合してセラミックス回路基板を作製した。
厚さ0.5mm、純度99%以上のアルミニウム板を用意し、図19に示すように、エッチングによりこのアルミニウム板の外周縁部内側に複数の孔6aを設けた。孔の直径は0.5mm、各孔の間隔は、0.5mm、かつ孔の縁部が外周縁部より0.5mmとなるようにした。このアルミニウム板を厚さ0.7mmの窒化アルミニウム基板に直接接合してセラミックス回路基板を作製した。
厚さ0.5mm、純度99%以上のアルミニウム板を用意し、図20に示すように、エッチングによりこのアルミニウム板の外周縁部内側に複数の溝7を設けた。溝の深さは0.25mm、溝の幅は、0.05mm、かつ溝の縁部が外周縁部より0.5mmとなるようにした。このアルミニウム板を厚さ0.7mmの窒化アルミニウム基板に直接接合してセラミックス回路基板を作製した。
厚さ0.5mm、純度99%以上のアルミニウム板を用意し、このアルミニウム板には薄肉部,孔,溝は形成しなかった。このアルミニウム板を厚さ0.7mmの窒化アルミニウム基板に直接接合してセラミックス回路基板を作製した。
2 セラミックス基板(AlN基板,Si3N4基板,Al2O3基板)
3,4,5 金属回路板(Al回路板,Cu回路板)
3a 金属回路板の外周縁部
3b 金属回路板の薄肉部
6 孔
6a 非貫通孔
6b 貫通孔
7 溝
7a U字状溝
7b V字状溝
Claims (7)
- セラミックス基板に金属回路板を接合して成るセラミックス回路基板において、窒化アルミニウムおよび窒化けい素の少なくとも1種からなるセラミックス基板と、このセラミックス基板に一体に形成されたAlを主成分とし、Siを0.05〜2重量%含有するろう材からなる接合層と、この接合層に一体に形成され、上記ろう材と金属回路板との合金化を防止する隔離層と、この隔離層を介して接合される金属回路板とを備え、上記隔離層がNi,Sn,In,Ag,Znの1種から成り、この隔離層の厚さが10μm以上であることを特徴とするセラミックス回路基板。
- 請求項1記載のセラミックス回路基板において、前記隔離層は、粒径が10μm以下の金属粉末を含む金属ペーストまたは金属箔からなることを特徴とするセラミックス回路基板。
- 請求項1記載のセラミックス回路基板において、前記隔離層の金属ペーストまたは金属箔を構成する金属がNi,SnおよびInのいずれかの金属であることを特徴とするセラミックス回路基板。
- セラミックス基板に金属回路板を接合して成るセラミックス回路基板において、窒化アルミニウムおよび窒化けい素の少なくとも1種からなるセラミックス基板と、このセラミックス基板に一体に形成されAlを主成分とし、Siを含有するろう材または合金からなる第1接合層と、この第1接合層に一体に接合され、第1接合層と金属回路板との合金化を防止する隔離層と、この隔離層表面に形成されAlを主成分とし、Siを0.1〜12重量%含有するろう材または合金からなる第2接合層と、この第2接合層を介して接合される金属回路板とを備え、上記隔離層がNi,Sn,Inの1種から成り、上記接合層および隔離層の厚さがそれぞれ10μm以上であることを特徴とするセラミックス回路基板。
- 請求項1,4のいずれかに記載のセラミックス回路基板において、前記金属回路板は外周縁部内側に薄肉部を有することを特徴とするセラミックス回路基板。
- 請求項1,4のいずれかに記載のセラミックス回路基板において、前記金属回路板は、前記セラミックス基板との接合面の反対側の面の外周縁部内側に設けられる複数の孔を有することを特徴とするセラミックス回路基板。
- 請求項1,4のいずれかに記載のセラミックス回路基板において、前記金属回路板は、前記セラミックス基板との接合面の反対側の面の外周縁部内側に設けられ、外周縁部に沿って複数の不連続な溝を有することを特徴とするセラミックス回路基板。
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| JPH11330283A (ja) * | 1998-05-15 | 1999-11-30 | Toshiba Corp | 半導体モジュール及び大型半導体モジュール |
| DK1056321T3 (da) * | 1999-05-28 | 2008-03-03 | Denki Kagaku Kogyo Kk | Keramisk substratkredslöb og dets fremstillingsproces |
-
2000
- 2000-09-13 JP JP2000277578A patent/JP4649027B2/ja not_active Expired - Lifetime
- 2000-09-25 US US09/668,747 patent/US6426154B1/en not_active Expired - Lifetime
- 2000-09-27 EP EP06013119.0A patent/EP1701381B1/en not_active Expired - Lifetime
- 2000-09-27 EP EP06013121A patent/EP1722411A3/en not_active Withdrawn
- 2000-09-27 EP EP00120263A patent/EP1089334B8/en not_active Expired - Lifetime
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2010
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Also Published As
| Publication number | Publication date |
|---|---|
| EP1701381B1 (en) | 2016-06-15 |
| EP1089334B1 (en) | 2011-06-22 |
| EP1722411A2 (en) | 2006-11-15 |
| EP1089334A3 (en) | 2005-11-09 |
| EP1089334A2 (en) | 2001-04-04 |
| EP1089334B8 (en) | 2011-09-21 |
| JP2001168482A (ja) | 2001-06-22 |
| JP4649027B2 (ja) | 2011-03-09 |
| EP1701381A2 (en) | 2006-09-13 |
| US6426154B1 (en) | 2002-07-30 |
| JP2010103570A (ja) | 2010-05-06 |
| EP1722411A3 (en) | 2007-01-24 |
| EP1701381A3 (en) | 2006-11-22 |
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