JP5070656B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device having a plurality of ports.
[0002]
[Prior art]
There are several types of multi-port memories, which are semiconductor storage devices having a plurality of ports. In the following, the term “multi-port memory” refers to a memory that has a plurality of ports and can independently access a common memory array from each port. In such a memory, for example, an A port and a B port are provided, and a CPU connected to the A port and a CPU connected to the B port can independently read and write to a common memory array.
[0003]
The multi-port memory includes an arbitration circuit called an arbiter. This arbiter determines the priority order of access requests received from a plurality of ports, and the control circuit of the memory array sequentially executes access according to this priority order. For example, the input to each port is executed preferentially in order from the earlier access.
[0004]
In such a case, since the memory array is randomly accessed from a plurality of ports, it is necessary to reset immediately after performing a read or write operation for one access to prepare for the next access. That is, for an access from a certain port, for example, when an operation of holding a word line in a selected state and sequentially reading and moving a column address as in a general column access operation in a DRAM, Access from will continue to wait. Therefore, it is necessary to reset immediately after one read or write operation.
[0005]
Conventionally, SRAM has generally been used as a memory array of a multi-port memory. This is because the SRAM has a high random access speed and can perform nondestructive reading.
[0006]
For example, in a 2-port multiport memory, two sets of word lines and bit line pairs are provided for one SRAM memory cell. One port performs a read / write operation using a set of one word line and bit line pair, and the other port executes a read / write operation using a set of the other word line and bit line pair. As a result, reading and writing can be performed independently from the two ports. However, when there is a write instruction from the two ports at the same time in the same cell, it is impossible to carry out simultaneously, so one port is given priority and a BUSY signal is generated at the other port. This is called a BUSY state.
[0007]
[Problems to be solved by the invention]
As the performance of the system increases, the amount of data handled increases, and a large capacity is required for the multiport memory. However, the SRAM type multi-port memory as described above has a problem that the area of the memory cell is large.
[0008]
In order to solve this problem, it is conceivable to employ a DRAM array for a multi-port memory. In order to achieve a large degree of integration for a multi-port SRAM, as in the case of a general DRAM cell, one memory cell of a DRAM used for a multi-port memory has one word line and one It is necessary to be connected only to the bit line. When a memory block is configured using DRAM cells as described above, when a read or write operation is executed from a certain port to a memory cell of a certain block, the block is accessed from another port during the operation. I can't. This is because the DRAM cell is destructive read. That is, once the information is read, it is not possible to select another word line in the same block without amplifying this information and writing it back to the cell and precharging the word lines and bit lines.
[0009]
For this reason, if a memory block being accessed from a certain port is accessed from another port, the state becomes BUSY. In the SRAM type multi-port memory, the BUSY state occurs only when there is a write request simultaneously from a plurality of ports to the same memory cell. However, in the DRAM type multi-port memory, the same memory block is simultaneously input from a plurality of ports. The BUSY state occurs when there is any access request. Therefore, the probability of occurrence of DRAM-type BUSY is considerably higher than the probability of occurrence of SRAM-type BUSY. In the BUSY state, there is a problem that a desired operation cannot be executed or a waiting time occurs, so that the processing becomes slow.
[0010]
Further, unlike the SRAM type multi-port memory, the DRAM type multi-port memory needs to be periodically refreshed in order to retain information, and therefore, it is necessary to take measures for the refresh timing and the like.
[0011]
In view of the above, an object of the present invention is to provide a DRAM type multi-port memory that solves the problems peculiar to DRAMs.
[0012]
[Means for Solving the Problems]
According to the present invention, a semiconductor memory device sequentially performs at least N access operations between a plurality of N external ports each receiving a command and a minimum interval between a plurality of commands input to one of the external ports. An internal circuit that executes automatically, an arbitration circuit that determines a command execution order for causing the internal circuit to execute a plurality of commands respectively input from the plurality of N external ports, and an input from each of the plurality of N external ports An address comparison circuit that determines whether or not there are a plurality of commands that access the same address among a plurality of commands to be executed , Ma Including a mode register designating a star operation mode or a slave operation mode, and each of the plurality of N external ports includes: A signal output circuit for outputting a predetermined signal to the outside of the apparatus when there are a plurality of commands for accessing the same address; a signal input circuit for receiving the predetermined signal from the outside of the apparatus; A circuit for supplying serially received data to the internal circuit as parallel data; and a circuit for outputting the data supplied in parallel from the internal circuit to the outside as serial data. The internal circuit is composed of dynamic memory cells. The signal output circuit is activated when the mode register designates the master operation mode, and the signal input circuit is activated when the mode register designates the slave operation mode. It is characterized by.
[0013]
The invention further includes an arbitration circuit that determines a command execution order for causing the internal circuit to execute a plurality of commands respectively input from a plurality of N external ports.
[0014]
In the above invention, when a command is input from a plurality of N ports, N commands corresponding to the N ports are sequentially executed during a minimum command cycle when attention is paid to a certain port. As a result, externally, for any port, it appears to perform an access operation for the command input of that port during the minimum command cycle. In this case, there is a possibility of entering the BUSY state only when there are simultaneous access requests from a plurality of ports to the same address. Therefore, the BUSY occurrence probability of the SRAM type multi-port memory and the equivalent low BUSY occurrence probability can be realized.
[0015]
Furthermore, in the semiconductor memory device of the present invention, the internal circuit includes a cell array composed of dynamic memory cells and a refresh circuit that defines a timing for refreshing the memory cells. In the first mode, a plurality of N external circuits are provided. The memory cell is refreshed in response to a refresh command input to at least one of the ports, and in the second mode, the memory cell is refreshed at a timing specified by the refresh circuit.
[0016]
In the above invention, by preparing an operation mode in which a refresh operation is performed by designating from an external port and an operation mode in which a refresh operation is performed in accordance with an instruction of the built-in refresh circuit, for example, a predetermined external port is used for refresh management. Depending on the system configuration, it is possible to operate so that a refresh command is periodically input as a port, or when the refresh management port is in an inactive state, a refresh operation can be executed by a built-in refresh circuit. Refresh management can be performed flexibly.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0018]
First, the operation principle of the present invention will be described.
[0019]
FIG. 1 is a diagram for explaining the operating principle of the present invention. FIG. 1 shows a principle diagram in the case of two ports, but the same operation is possible even in the case of two or more N ports.
[0020]
The time required for the internal (DRAM core) to rotate two cycles is set as one cycle of the external command cycle. That is, the internal operation cycle rotates at a double speed with respect to the external command cycle. Commands entered from both the A port and the B port are processed at a double speed in the internal memory in order from the one with the fastest command reception, and the output data is passed to each port. That is, in one internal operation cycle, a series of operations of word line selection, data amplification, column selection, read or write operation, and precharge are executed, and the access operation to the memory block is completed.
[0021]
For example, at timing C1 of the external command cycle for the A port in FIG. 1, a read command is input from the A port. At the timing C1 ′ of the external command cycle for the B port, a read command is input from the B port. Since the timing of the read command from the A port is slightly earlier, it is executed internally before the read command from the B port. Here, the external command cycle is 4 clock cycles. As shown in FIG. 1, each read command is executed and completed in two clock cycles that are internal operation cycles. Therefore, even if the read access from the A port and the read access from the B port are for the same block, by completing the execution of each access in 2 clock cycles, the external command cycle is input in 4 clock cycles. In response to the read command from the A port and the B port, the read operation can be executed without generating a BUSY state.
[0022]
In this way, even if the same memory block is accessed from a plurality of ports at the same time, the internal memory can be processed continuously at double speed, so it does not enter the BUSY state. .
[0023]
Also, as shown in FIG. 1, when a refresh command is given from the outside (for example, given from the A port), it does not affect the access of other ports (B port in this example) and is internally A refresh operation can be performed. In this case, for example, one of a plurality of ports (A port in the example of FIG. 1) may be set as a port for refresh management, and a refresh command may be always input from this port.
[0024]
Data output is a burst type that reads data from multiple column addresses in parallel and changes the data serially at the time of output to output the data, thereby improving the data transfer rate and allowing continuous data to be read in response to a continuous Read command. Can be output.
[0025]
FIG. 2 is a diagram showing a refresh operation when only one of the plurality of ports is operated.
[0026]
As shown in FIG. 2, for example, when two ports, an A port and a B port, are provided, it is not always necessary to operate both ports. By incorporating a refresh timer, a refresh command can be generated internally. For example, as shown in FIG. 2, when one port (for example, B port) is stopped, a refresh command is generated internally, and refresh is performed internally without affecting the access of A port. Is possible.
[0027]
For example, consider a case where the controller A controls the A port, the controller B controls the B port, and the controller B performs refresh management. In such a case, if there is an internal refresh function as described above, the B port can be completely stopped and only the A port can be used, so that it is possible to reduce the power corresponding to the operation of the system.
[0028]
FIG. 3 is a diagram for explaining the principle of the present invention in the case of 2 ports, 3 ports, and N ports.
[0029]
As described above, the present invention can be applied to a multiport memory having three or more ports. FIG. 3A shows an operation for one port in the case of two ports as shown in FIGS. Further, (b) shows the operation for one port in the case of 3 ports, and (c) shows the case of N port memory. As shown in FIG. 3C, in the case of an N-port memory, the length of the internal operation cycle may be set to 1 / N with respect to the external command cycle.
[0030]
A semiconductor memory device according to an embodiment of the present invention will be described below.
[0031]
FIG. 4 is a block diagram showing a first embodiment of a multi-port memory according to the present invention. In this example, there are two ports, A port and B port.
[0032]
4 includes an A port 11, a B port 12, a self-refresh circuit 13, a DRAM core 14, an arbiter 15, a refresh command register 16, a command register A17, a command register B18, a refresh address register 19, and an address register A20. Address register B21, write data register A22, write data register B23, transfer gate A24, and transfer gate B25.
[0033]
The A port 11 includes a mode register 31, a CLK buffer 32, a data input / output circuit 33, an address buffer 34, and a command decoder 35. The B port 12 includes a mode register 41, a CLK buffer 42, a data input / output circuit 43, an address buffer 44, and a command decoder 45. In the A port 11 and the B port 12, access to the external bus is established independently in synchronization with the clocks CLKA and CLKB. In the mode registers 31 and 41, modes such as data latency and burst length can be set for each port. In this embodiment, mode registers are arranged in both the A port 11 and the B port 12, and the mode can be set in each port. However, for example, a mode register may be arranged only on one port, and settings for both ports may be performed on one port.
[0034]
The self-refresh circuit 13 includes a refresh timer 46 and a refresh command generator 47. The self-refresh circuit 13 is a circuit that internally generates a refresh command, and receives signals CKEA 1 and CKEB 1 from the A port 11 and the B port 12. Signals CKEA1 and CKEB1 are signals obtained by buffering external signals CKEA and CKEB with CLK buffers 32 and 42, respectively. External signals CKEA and CKEB are used to stop the clock buffer of each port and deactivate the port. When one of the A port 11 and the B port 12 becomes inactive, the self-refresh circuit 13 operates. If it is set in the mode registers 31 and 41 which port is responsible for refresh management, the self-refresh circuit 13 may be operated when the refresh management port becomes inactive.
[0035]
The DRAM core 14 includes a memory array 51, a decoder 52, a control circuit 53, a Write Amp 54, and a sense buffer 55. The memory array 51 includes DRAM memory cells, cell gate transistors, word lines, bit lines, sense amplifiers, column lines, column gates, and the like, and stores data to be read and written. The decoder 52 decodes an address to be accessed. The control circuit 53 controls the operation of the DRAM core 14. The Write Amp 54 amplifies data to be written in the memory array 51. The sense buffer 55 amplifies data read from the memory array 51.
[0036]
The input to the A port 11 is transferred to the address register A20, the refresh command register 16, the command register A17, and the write data register A22. The input to the B port 12 is supplied to the address register B21, the refresh command register 16, the command register B18, and the write data register B23. The arbiter (arbiter circuit) 15 determines the command input order in order to determine which command is to be processed with priority between the A port 11 and the B port 12. The arbiter 15 transfers commands, addresses, and data (in the case of a write operation) from each register to the DRAM core 14 in the order according to the determination result. Based on the transferred data, the DRAM core 14 operates. In the case of a read command, the data read from the DRAM core 14 is transferred to the port to which the corresponding command is input, subjected to parallel / serial conversion, and output in synchronization with the clock of the port.
[0037]
FIG. 5 is a configuration diagram of a circuit related to command input to the arbiter 15.
[0038]
The command decoder 35 includes an input buffer 61, a command decoder 62, and an (n−1) clock delay circuit 63. The command decoder 45 includes an input buffer 71, a command decoder 72, and an (n−1) clock delay circuit 73. The command register A17 includes a Read command register 17-1 and a Write command register 17-2. The command register B18 includes a Read command register 18-1 and a Write command register 18-2.
[0039]
In the case of a Read command, the command input to the input buffer 61 or 71 is transferred to the Read command register 17-1 or 18-1 at the same timing via the command decoder 62 or 72. In the case of the write command, the write command register is delayed at the timing when the nth final data of a series of burst data to be written is input by being delayed by (n-1) clock delay circuit 63 or 73. It is transferred to 17-2 or 18-2.
[0040]
As for the refresh command, the refresh commands from the A port 11, the B port 12 and the refresh command generator 47 are transferred to the refresh command register 16. Since the occurrence frequency of the refresh command is low, it is not necessary to prepare a plurality of refresh command registers. The self-refresh setting information input to the refresh command generator 47 is information supplied from the mode registers 31 and 41, and is information indicating which port is performing refresh management.
[0041]
The arbiter 15 detects the order in which commands are transferred to each command register, and transfers the commands to the DRAM control circuit 53 one by one in order.
[0042]
When the DRAM control circuit 53 receives a command (or when the command execution is nearing the end), it generates a RESET1 signal and causes the arbiter 15 to prepare the next command. In this embodiment, when the RESET1 signal is disconnected, the DRAM control circuit 53 receives the next command.
[0043]
When the arbiter 15 receives the RESET1 signal, the arbiter 15 supplies any one of the reset signals ResetRA, ResetWA, ResetRB, ResetWB, and ResetREF to the command register corresponding to the command register A17, the command register B18, and the refresh command register 16. As a result, the command register storing the command that has been transferred to the DRAM core 14 is reset, and the next command is prepared in this command register.
[0044]
FIG. 6 is a circuit diagram showing a configuration of the arbiter 15.
[0045]
As shown in FIG. 6A, the arbiter 15 includes comparators 80-1 to 80-10, AND circuits 81-1 to 81-5, AND circuits 82-1 to 82-5, and AND circuit 83-1. Through 83-5, delay circuits 84-1 through 84-5, inverters 85 through 87, NAND circuit 88, and inverters 89 and 90. Each of the comparators 80-1 to 80-10 has the same circuit configuration, and includes NAND circuits 91 and 92 and inverters 93 and 94 as shown in FIG.
[0046]
A read command signal RA2 and a write command signal WA2 from the command register A17, a read command signal RB2 and a write command signal WB2 from the command register B18, and a refresh command REF2 from the refresh command register 16 are supplied to the arbiter 15. . For all ten combinations that select two of these five command signals, ten comparators 80-1 to 80-10 determine the context of command arrival timing.
[0047]
Each comparator compares the timings of the two commands, and sets the output on the side to which HIGH is previously input as HIGH. For example, the comparators 80-1 to 80-4 determine the context of the read command signal RA2 for the A port 11 and the other four commands. When the read command signal RA2 is earlier than any of the other four commands, the read command signal RA31 that is the output of the AND circuit 81-1 becomes HIGH. When the RESET1 signal is LOW, the read command signal RA31 is output from the arbiter 15 to the DRAM core 14 as the read command signal RA3.
[0048]
When the DRAM core 14 receives the command, the RESET1 signal is generated at the DRAM core and becomes HIGH. The RESET1 signal is converted into a pulse signal by the inverters 85 to 87, the NAND circuit 88, and the inverter 89, and is supplied to the AND circuits 83-1 to 83-5. For example, when the read command signal RA31 is HIGH, a signal (ResetRA) for resetting the command register storing the received command is generated via the delay circuit 84-1.
[0049]
FIG. 7 is a timing chart showing the operation of the arbiter 15.
[0050]
The signal names shown in FIG. 7 are shown in each part of FIG. FIG. 7 shows the operation of the arbiter 15 when a read command is supplied to the A port 11 and the B port 12. As shown in FIG. 7, first, RA2, which is a read command corresponding to the A port 11, is preferentially selected to generate RA31, and the core circuit executes the read operation READ-A. In response to the generated reset signal RESET1, the read command signal RA2 is reset. In response to this, RB2, which is a read command corresponding to the B port 12, is selected and RB31 is generated. When the reset signal RESET1 becomes LOW, the read command RB3 is supplied to the core circuit, and the read operation READ-B is executed.
[0051]
FIG. 8 is a configuration diagram of a circuit related to address input to the DRAM core 14.
[0052]
The address buffer 34 of the A port 11 includes an input buffer 34-1, a transfer gate 34-2, and an OR circuit 34-3. In response to the read command signal RA1 which is the output of the command decoder 62 shown in FIG. 5, a pulse signal whose rising edge is pulsed is supplied as RA1P to one input of the OR circuit 34-3. A pulse signal whose rising edge is pulsed is supplied as WA1P to the other input of the OR circuit 34-3 with respect to the write command signal WA1 which is the other output of the command decoder 62 shown in FIG. . Similarly, the signal having P at the end of the signal name represents a signal created by pulsing the rising edge of the corresponding signal name.
[0053]
The address buffer 44 of the B port 12 includes an input buffer 44-1, a transfer gate 44-2, and an OR circuit 44-3.
[0054]
The address register A20 includes an address latch 101, a transfer gate 102, an address latch 103, a transfer gate 104, a transfer gate 105, an address latch 106, and a transfer gate 107. The address register B 21 includes an address latch 111, a transfer gate 112, an address latch 113, a transfer gate 114, a transfer gate 115, an address latch 116, and a transfer gate 117.
[0055]
The refresh address register 19 includes a refresh address counter / register 19-1, an inverter 19-2, and a transfer gate 19-3. The refresh address is generated and held in the refresh address counter / register 19-1.
[0056]
With the above circuit configuration, when a Read command or a Write command is input from the outside, the address input at the same time is transferred to the address latch 101 or 111. When the command is a Read command, it is transferred to the address latch 106 or 116 at the same timing. When the command is a write command, it is transferred to the address latch 103 or 113 at the timing of fetching the final data of a series of write data.
[0057]
As shown in the circuit configuration of FIG. 8, the pulse signals RA3P, WA3P, RB3P, WB3P, and REF3P corresponding to RA3, WA3, RB3, WB3, and REF3, which are command signals transferred from the arbiter 15 to the DRAM core 14, In response, an address signal is transferred from the address latch to the DRAM core 14.
[0058]
FIG. 9 is a configuration diagram of a circuit related to data output.
[0059]
A portion related to data output of the data input / output circuit 33 includes a data latch 121, a transfer gate 122, a data latch 123, a parallel / serial converter 124, an output buffer 125, and a transfer signal generation circuit 126. The data input / output circuit 43 related to data output includes a data latch 131, a transfer gate 132, a data latch 133, a parallel / serial converter 134, an output buffer 135, and a transfer signal generation circuit 136.
[0060]
Data read from the memory array 51 is amplified by the sense buffer 55 and supplied to the data input / output circuit 33 or the data input / output circuit 43 via the transfer gate A24 or the transfer gate B25. At this time, if the executed command is reading on the A port 11 side, the transfer gate A24 is opened, and if the executed command is reading on the B port 12 side, the transfer gate B25 is opened. The supplied data is latched and held in the data latch 121 or 131.
[0061]
The transfer gate 122 or 132 is opened after a predetermined latency from the reception of the Read command at each port by the transfer signal from the transfer signal generation circuit 126 or 136. As a result, the data in the data latch 121 or 131 is transferred to the data latch 123 or 133. Thereafter, the parallel / serial converter 124 or 134 converts the parallel data into serial data, which is transferred to the output buffer 125 or 135 for output.
[0062]
FIG. 10 is a circuit diagram showing a configuration of the transfer signal generation circuit 126 or 136.
[0063]
The transfer signal generation circuit 126 or 136 includes flip-flops 141 to 144 and a multiplexer 145. The read command signal RA1 or RB1 is supplied to the flip-flop 141, and the command signal is propagated to the flip-flop at the next stage in synchronization with the clock signal CLKA1 or CLKB1. The multiplexer 145 is supplied with latency information A or B. This latency information is information that specifies, for example, how many clock cycles the latency is. Based on this latency information, the multiplexer 145 selects the Q output of the corresponding flip-flop and outputs it as a data transfer signal.
[0064]
FIG. 11 is a configuration diagram of a circuit related to data input.
[0065]
A portion related to data input of the data input / output circuit 33 includes a data input buffer 151, a serial / parallel converter 152, and a data transfer unit 153. The portion related to data input of the data input / output circuit 43 includes a data input buffer 154, a serial / parallel converter 155, and a data transfer unit 156.
[0066]
Data serially input to the data input buffer 151 or 154 is converted into parallel data by the serial / parallel converter 152 or 155. When the last data is input, the parallel data is transferred to the write data register A22 or the write data register B23. When a write command is transferred from the arbiter 15 to the DRAM core 14, the data in the write data register A22 or the write data register B23 is transferred to the DRAM core 14 by a signal WA3P or WB3P indicating the corresponding timing.
[0067]
FIG. 12 is a timing chart showing the operation when the Read command is continuously input.
[0068]
The A port 11 and the B port 12 operate in synchronization with clocks CLKA and CLKB having different frequencies. In this example, A port 11 operates at the highest clock frequency and B port 12 operates at a slower clock frequency.
[0069]
The A port 11 has Read command cycle = 4 (CLKA), data latency = 4, and burst length = 4, and the B port 12 has Read command cycle = 2 (CLKB), data latency = 2, and burst length = 2. Data latency and burst length are set in the mode register of each port.
[0070]
Commands received by both ports are held in command registers, respectively. The refresh command is held in the refresh command register. The arbiter monitors these command registers, and transfers them to the DRAM core in order from the command generated earlier. After processing of the previously transferred command is completed, the next command is transferred.
[0071]
The data read from the DRAM core is transferred from the sense buffer to the data latch of each port (see FIG. 9). Thereafter, the parallel data is converted into serial data, and burst output is performed in synchronization with the external clock.
[0072]
As shown in FIG. 12, the refresh command is input once from the A port, but it does not affect the operation of the B port.
[0073]
FIG. 13 is a timing chart showing the operation when the Write command is continuously input.
[0074]
Data input from the outside during the write operation is a burst input. At this time, the write command is held in the write command register at the timing when the last data of the burst input is input.
[0075]
As shown in FIG. 13, the refresh command given from the A port does not affect the operation of the B port.
[0076]
FIG. 14 is a timing diagram showing a case where both the A and B ports operate at the maximum clock frequency.
[0077]
As shown in FIG. 14, there may be a difference in the phase of the clocks of both ports. In both ports, Read command cycle = 4, data latency = 4, and burst length = 4. It can be seen that even when both ports are operated at the maximum clock frequency and the Read command is continuously input, the ports are operating without any problem.
[0078]
FIG. 15 is a timing diagram showing a case where both the A and B ports operate at the maximum clock frequency. In FIG. 15, write commands are continuously input to both ports.
[0079]
As shown in FIG. 15, there may be a difference in the phase of the clocks of both ports. For both ports, the Write command cycle = 4, the data latency = 4, and the burst length = 4. It can be seen that even when both ports are operated at the maximum clock frequency and the Write command is continuously input, the ports are operating without any problem.
[0080]
FIG. 16 is a timing chart showing an operation when a command is switched from Read to Write.
[0081]
As shown in FIG. 16, Write → Read needs to have an extra command interval with respect to the Write → Write or Read → Read command interval. This is because the timing at which the write command is transferred to the command register and processed is the timing at which the last data of the burst input is input. On the other hand, since the read command is transferred to the command register for processing at the timing when the read command is input, if a command of Write → Read continues, it is necessary to provide an extra command interval. However, this is caused by the operation of converting the data into parallel data by burst input. For example, if only one data is input instead of burst input of four data, Write → Read. Even if commands continue, there is no need to leave a command interval.
[0082]
In other words, if only one data is input for one write command, even if the command continues from Write → Read, it can operate at the same command interval as Write → Write or Read → Read. Is possible.
[0083]
FIG. 17 is a diagram illustrating the timing of inputting a refresh command when the command is switched from Read to Write.
[0084]
The timing for inputting the refresh command is shown in the upper part of FIG. A refresh command may be input at some timing in the period shown here. For example, even if the refresh command is input at the timing shown in FIG. 17, the refresh operation is actually started after the execution of the preceding write command is completed. Waiting on register. Therefore, it can be seen that the refresh command may be input at an arbitrary timing within the period corresponding to this standby state.
[0085]
FIG. 18 is a timing chart showing the operation when one of the ports is deactivated.
[0086]
As shown in FIG. 18, when one of the ports (A port 11 in the figure) is deactivated, a refresh command is generated internally based on the refresh timer, and the refresh operation is executed in response to this. .
[0087]
FIG. 19 is a timing chart showing the operation when both ports are deactivated.
[0088]
As shown in FIG. 19, even when both ports are deactivated, a refresh command is generated internally based on the refresh timer, and a refresh operation is executed accordingly.
[0089]
FIG. 20 is a timing chart showing the operation of the DRAM core. FIG. 20A shows the case of the read operation, and FIG. 20B shows the case of the write operation. At the operation timing as shown in FIGS. 20A and 20B, word line selection, data amplification, write back, and precharge are sequentially executed for one command to complete the operation.
[0090]
FIG. 21 is a timing chart showing the double speed operation when only one port is operated.
[0091]
By stopping one of the two ports, the interval between commands input from the other port can be halved. At this time, the highest cycle of the external command coincides with the highest cycle of the internal operation. In the example of FIG. 21, the command interval is shortened without changing the clock frequency. In this case, since the burst length is also shortened, the data transfer rate is the same as when both ports are used.
[0092]
FIG. 22 is a timing chart showing the double speed operation in which the clock frequency is doubled and the data transfer rate is doubled.
[0093]
In FIG. 22, when one of the two ports is stopped, the clock signal input from the other port is set to double the frequency. Along with this, the command input time interval is halved. In this case, since the burst length is the same as when both ports are used, the data transfer rate is doubled when both ports are used.
[0094]
Since the external clock signal is input only to the input / output circuit section, if the portion is designed for high-speed operation, the double speed operation can be easily realized.
[0095]
FIG. 23 is a diagram for explaining a second embodiment of the present invention.
[0096]
Memory is generally expanded depending on the application. The same applies to a multi-port memory. In addition to using a single memory, there is a case where a memory is expanded by mounting a plurality of memories.
[0097]
The multi-port memory has a built-in arbiter that detects which port's command is earlier and executes the commands in that order. Even when commands for both ports are input almost simultaneously, the order is determined and executed sequentially. As shown in FIG. 23, a plurality of multi-port memories 200-1 to 200-n are mounted, and the same commands are sent to these multi-port memories 200-1 to 200-n from the A port controller 201 and the B port controller 202. Suppose you give it. Even if the A port and B port commands are issued at the same time, the relative timing of the commands reaching each multi-port memory may be slightly different due to the influence of the signal line length and power supply noise. In this case, there is a possibility that each multiport memory arbiter executes commands in a different order.
[0098]
If the commands for the A port and the B port are commands for different addresses, there is no problem even if the order is different between the memory devices. However, if the commands are for the same address, a problem occurs.
[0099]
For example, when data is read after being written to the same cell and when data is read after being read, the read data is different. Further, for example, when the data of the B port is written after the data of the A port is written, it is the data of the B port that remains in the memory, but when executed in the reverse order, the data of the A port is stored in the memory. Will remain.
[0100]
Thus, if the order of command execution differs between memory devices, a serious problem occurs in data reliability.
[0101]
Therefore, when a plurality of multiport memories are used, it is necessary to match the determination of the arbiter between the multiport memories. In order to solve this, in the second embodiment of the present invention, one of a plurality of multi-port memories is a master device 200-1, and the rest are slave devices 200-2 to 200-n. The slave device matches the judgment of the arbiter.
[0102]
FIG. 24 is a block diagram showing a second embodiment of the multi-port memory according to the present invention. In this example, there are two ports, A port and B port.
[0103]
The difference from the first embodiment shown in FIG. 4 is that the BUSY signal I / O units 36 and 46 are provided in the A port 11A and the B port 12A, and the address comparison for comparing the addresses of the A port and the B port. For example. The arbiter 15A operates to switch the operation mode of the DRAM core to the continuous mode when the address comparator 26 matches the address and generates a coincidence signal.
[0104]
FIG. 25 is a timing chart for explaining the continuous mode.
[0105]
As shown in the operation diagram of the first embodiment (FIG. 20), the DRAM core operation is divided into a ROW operation and a COLUMN operation. In the present invention, the ROW operation, the COLUMN operation, and the precharge operation are set as one internal operation cycle executed in a series of flows.
[0106]
The continuous mode in the second embodiment is the same as a normal DRAM column access operation, and is an operation in which commands are continuously executed on the same cell. That is, in this mode, the COLUMN system operation is executed a plurality of times after the ROW system operation and then precharged. However, when the Write command of the same cell is duplicated, the one input later is executed and the one input before is not executed. This is because even if the write is executed continuously, the data written before is overwritten with the data written later and does not remain later.
[0107]
As shown in FIG. 25A, in the continuous mode, the operation can be shortened more than two normal internal operation cycles, and time can be afforded. As shown in FIG. 25B, this time margin is provided between the ROW operation and the COLUMN operation (hereinafter referred to as a wait period). During this Wait period, the command execution order is matched between the master and the slave.
[0108]
The procedure for matching the operations of the master and the slave with the BUSY signal will be described below.
[0109]
The BUSY signal is used to match the command execution order between the master and the slave. The BUSY signal I / O units 36 and 46 become a BUSY output circuit that outputs a BUSY signal in the master device 200-1, and a BUSY input circuit that receives the BUSY signal in the slave devices 200-2 to 200-n. Information indicating whether the device is a master device or a slave device is set in the mode register 31 or 41.
[0110]
First, the memory device receives a command from one port and starts the operation shown in FIG.
[0111]
If a command is input from another port to the same address during the ROW system operation period, a coincidence signal is generated from the address comparator 26. Upon receiving this coincidence signal, the arbiter 15A supplies a continuous mode signal to the control circuit 53 of the DRAM core 14. In response to the continuous mode signal, the DRAM core 14 shifts to the continuous mode as shown in FIG.
[0112]
During the Wait period, the master device 200-1 generates BUSY-A or BUSY-B based on the determination result of the arbiter 15A. In this example, a BUSY signal is generated for the port that is determined to be received first by the arbiter 15A.
[0113]
Similarly, during the Wait period, the slave device detects the BUSY signal generated by the master device, and if it is different from the determination of its own arbiter 15A, the determination of its own arbiter 15A is changed in accordance with the master. The COLUMN system operation is executed in accordance with the changed order.
[0114]
FIG. 26 is a timing chart showing an operation when BUSY occurs in Read of A port and Write of B port.
[0115]
In this embodiment, the BUSY signal is set to the logic of selection “L”. The BUSY signal is preferably a signal that is transmitted / received asynchronously. This is for promptly transmitting BUSY within a limited Wait period.
[0116]
In the example of FIG. 26, since the Read A2 of the A port is earlier than the Write B2 of the B port, the master generates the BUSY signal of the A port during the Wait period. The slave receives this BUSY signal and knows that ReadA2 of the A port is earlier than WriteB2 of the B port. After that, the column operation is executed in the continuous mode in the order of ReadA2 → WriteB2 in the master and the slave.
[0117]
FIG. 27 is a timing chart showing an operation when BUSY occurs in Read of A port and Write of B port. FIG. 26 shows the case where the Read of the A port is early, but FIG. 27 shows the case where the Write of the B port is early.
[0118]
FIG. 28 is a timing chart showing an operation when BUSY occurs at the write of the A port and the write of the B port.
[0119]
The operation example shown in FIG. 28 is when the A port write command is earlier than the B port write command. That is, since the Write A2 of the A port is earlier than the Write B2 of the B port, the BUSY signal of the A port is generated and supplied to the slave. In this case, even if the A port write command is executed, it is immediately rewritten. Therefore, only the B port write command WriteB2 inputted later is executed.
[0120]
FIG. 29 is a timing chart showing the operation when BUSY occurs at the write of the A port and the write of the B port.
[0121]
The operation example shown in FIG. 29 is when the B port write command is earlier than the A port write command. In this case, even if the B port write command is executed, it is immediately rewritten, so only the A port write command Write A2 is executed. In this example, the clock frequency of the A port is set slightly lower than the clock frequency of the B port. For the commands of Write A2 and Write B2, the command input is faster in the A port, but the final data input is faster in the B port. Therefore, the write command for the B port is earlier than the write command for the A port.
[0122]
In the above description, the cases of A port Read and B port Read are not described. In this case, no matter which is first, there is no effect on the reliability of the data, so it is not necessary to use BUSY.
[0123]
FIG. 30 is a timing chart showing an operation when the controller is configured to be able to insert an interrupt.
[0124]
“Interrupt” refers to issuing an instruction to change the determination from the controller to the determination of the arbiter of the master device in the case of BUSY. The following is an interrupt instruction method.
a) Entering with commands
b) How to provide a dedicated terminal
c) Method by special address combination
d) Method using BUSY signal
The above d) is, for example, a method in which the BUSY signal of the port where no BUSY has occurred is given from the controller, and the master and slave memories detect it.
[0125]
In the example of FIG. 30, an interrupt is generated when BUSY occurs at the write of the A port and the write of the B port. As described with reference to FIG. 28 and FIG. 29, when the write-write state becomes BUSY, only the write of either A or B is executed, so that the data that has been input first is lost.
[0126]
In FIG. 30, the A port's Write A2 is earlier than the B port's Write B2, and therefore the A port BUSY signal is generated. The controller that has received the BUSY signal generated by the master generates an interrupt instruction in order to prevent the write data of the A port from being lost.
[0127]
The master and the slave receive the interrupt instruction from the controller, change the determination of the arbiter, and perform the write operation according to the interrupt instruction after the wait. That is, the arbiter changes the determination that the A port command Write A2 is slower than the B port command, and executes the write operation of Write A2. As a result, it is possible to prevent the write data of the A port from being erased. In the write-to-write operation, the write operation need only be executed once, so that the wait time can be made longer than the read-to-write or write-to-read continuous mode. Therefore, using this time, an interrupt instruction based on the BUSY signal can be executed.
[0128]
The configuration of the address comparator, BUSY input / output system, and interrupt system for achieving the above operation will be described below.
[0129]
FIG. 31 is a diagram showing the configuration of the address comparator, BUSY input / output system, and interrupt system in the multiport memory according to the second embodiment of the present invention.
[0130]
The address comparator 26 compares the addresses held in the address register and outputs a match signal when the address of the A port 11 and the address of the B port 12 match. Also, ARA, AWA, ARB, and AWB signals are generated to indicate which two addresses match. For example, when the addresses of the A port Write and the B port Write match, AWA and AWB are set to “H”. The NAND circuits 208 to 210 take NAND of these signals, and any one of N1, N2, and N3 becomes “L”.
[0131]
Arranged on the left side of FIG. 31 (below the address comparator 26) are BUSY signal I / O units 36 and 46 and an interrupt circuit. Upon detecting the coincidence signal, the BUSY / I / O control unit 211 generates an activation signal (master) in the case of a master device and an activation signal in the case of a slave device based on the setting of the mode register 31 or 41. (Slave) is generated. The activation signal (master) activates the BUSY output circuits 212 and 213, and the activation signal (slave) activates the BUSY input circuits 214 and 215.
[0132]
At this time, in the arbiter, the command selected in the first rank is output to any one of the arbiter outputs RA3, WA3, RB3, and WB3 (any one is “H”). . In the case of the master device, RA3 to WB3 are latched in the latches 216 and 217 by the signal N4 obtained by pulsing the rising edge of the coincidence signal. Based on the latched data, BUSY-A or BUSY-B is output.
[0133]
In the case of a slave device, for example, when BUSY-A = “L” is received, the signal N10 that is the output of the interrupt circuit 218 becomes “L”. When BUSY-B = "L" is received, the signal N11 that is the output of the interrupt circuit 219 becomes "L". N10 and N11 are “H” when inactive, and become “L” when BUSY reception or interrupt is received.
[0134]
The interrupt detection unit 220 detects an interrupt instruction from the controller and outputs interrupt A or B. These interrupt signals are transmitted to the signals N10 and N11 with priority over the BUSY input signal.
[0135]
The three comparators 80-3, 80-5, and 80-6 shown at the bottom of FIG. 31 are part of the comparator of the arbiter 15A (see FIGS. 6 and 24). These are comparators that compare command combinations that require BUSY determination.
[0136]
FIG. 32 is a timing chart showing the operation of the master device. FIG. 33 is a timing chart showing the operation of the slave device.
[0137]
As shown in these operation timing diagrams, it is assumed that the Read of the A port matches the Write address of the B port. The master in FIG. 32 determines that the A port is early, and the slave in FIG. 33 determines that the B port is early. In this case, the outputs of the master comparator 80-3 are N21 = "L" and N22 = "H". The outputs of the slave comparator 80-3 are N21 = "H" and N22 = "L". The master generates BUSY-A, and the slave that receives it generates N10 = "L". Since N1 = “L” at this time, the LOW signal of N10 is supplied to the slave comparator 80-3 via the NOR circuit 221 and the inverter 222. As a result, the output of the slave comparator 80-3 is switched to N21 = "L" and N22 = "H". This changes the determination of the slave arbiter.
[0138]
In contrast to the above operation, it is assumed that the Write address of the A port and the Read address of the B port match. In this case, the determination of the slave arbiter is changed by switching the output of the slave comparator 80-5.
[0139]
Comparator 80-6 is a comparator for WA2 and WB2. However, when BUSY occurs between Writes, the operation of either the A port or the B port is left, so that comparator 80-3 and The configuration of the peripheral circuit is different from that of 80-5.
[0140]
FIG. 34 is a timing chart showing the operation of the master device when the write addresses of both ports match. FIG. 35 is a timing chart showing the operation of the slave device when the write addresses of both ports match.
[0141]
Assume that the master determines that the A port is early as shown in FIG. 34, and the slave determines that the B port is early as shown in FIG. At the time when the coincidence signal is generated from the address comparator 26, the outputs of the master comparator 80-6 are N25 = "L" and N26 = "H", and the output of the slave comparator 80-6 is N25. = "H" and N26 = "L". The master latches RA3, WA3, RB3, and WB3 in this state, and outputs a BUSY-A signal.
[0142]
As in this case, when BUSY occurs in Write-Write, it is necessary to delete the Write that has been input first. The inverter 231, the NOR circuit 232, the NAND circuits 233 and 234, and the inverters 235 and 236 are circuits provided for that purpose. When the coincidence signal is generated, the HIGH edge pulsing circuit 230 generates an “H” pulse of the signal N4. The logic of the signal N3 is taken and an “H” pulse is generated at N31. In this example, in the case of the master, since N26 = "H", a "H" pulse is generated at N33, and N25 = "H" and N26 = "L" are switched. This is because the delay circuits 237 and 238 gain time in the state before switching to generate the BUSY signal, and prevent the switching result from being fed back to the NAND circuits 233 and 234 and switching again. . In the slave, N25 = "L" and N26 = "H" are switched.
[0143]
As described above, the master generates BUSY-A, and N10 = "L" in the slave that has received it. At this time, since N3 = “L”, the slave comparator 80-6 is inverted again and switched to N25 = “H” and N26 = “L”.
[0144]
The delay circuit 250 has a function of generating a wait period by receiving the signal N4 and delaying it for a predetermined time and outputting a wait cancellation signal. Here, when N1 or N2 is selected, Delay (t1) is selected, and when N3 is selected, Delay (t2) is selected.
[0145]
NAND circuits 251 and 252 and inverters 253 and 254 are circuits for deleting the erased Write command from the command register when the Wait period ends. For example, if N25 = “L” and N26 = “H” at the end of the Wait period, the Write command for the A port is executed. Therefore, ResetWB2 is generated in order to erase the B port Write command from the register. During the Wait period, it is necessary to change the determination by BUSY reception or interrupt, so the command in the command register is not erased during that period.
[0146]
FIG. 36 is a timing chart showing the operation of the master device when the write address of both ports coincides and an interrupt instruction is generated from the controller. FIG. 37 is a timing chart showing the operation of the slave device when an interrupt instruction is issued from the controller when the write addresses of both ports match.
[0147]
As shown in FIG. 36, the command selection state in the master device is inverted by an interrupt. As shown in FIG. 37, the command selection state in the slave device is inverted by BUSY and then further inverted by interrupt. Note that the inversion operation by interrupt is the same as the inversion operation by BUSY, and a detailed description thereof will be omitted.
[0148]
In the operation of the second embodiment, the command cycle from the occurrence of BUSY or interrupt until the next command is input is not changed.
[0149]
For example, in FIG. 26, BUSY occurs in ReadA2, but the command interval of ReadA1 → ReadA2 and the command interval of ReadA2 → ReadA3 are the same. BUSY and interrupts must be processed during the wait time, but if the bus line on the system is long, the number of installed slave devices is large, or the controller response speed is slow, BUSY or Since it takes time to exchange interrupt signals, a long wait time is required.
[0150]
In order to solve this, the wait time may be extended and the next command input after the occurrence of BUSY or interrupt may be delayed for a predetermined time. That is, in FIG. 26, the wait time may be increased and the command interval of ReadA2 → ReadA3 may be increased with respect to the command interval of ReadA1 → ReadA2.
[0151]
In order to delay the command input, this should be specified in the data sheet and the controller operated as such. As a method of extending the wait time, the delay time of the delay circuit 250 shown in FIG. If it is desired to change the wait time depending on the use state, a plurality of delay trains may be prepared in the delay circuit 250 so that the setting of the delay amount can be switched by setting the mode register.
[0152]
In addition, if the wait time is increased in this way, the wait time can be increased even in cases other than the write-write BUSY, so that even if a BUSY occurs in the read-write or write-read, an interrupt instruction can be issued from the controller. Become.
[0153]
As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.
[0154]
【Effect of the invention】
In the above invention, when a command is input from a plurality of N ports, N commands corresponding to the N ports are sequentially executed during a minimum command cycle when attention is paid to a certain port. As a result, externally, for any port, it appears to perform an access operation for the command input of that port during the minimum command cycle. In this case, there is a possibility of entering the BUSY state only when there are simultaneous access requests from a plurality of ports to the same address. Therefore, the BUSY occurrence probability of the SRAM type multi-port memory and the equivalent low BUSY occurrence probability can be realized.
[0155]
Furthermore, in the semiconductor memory device of the present invention, the internal circuit includes a cell array composed of dynamic memory cells and a refresh circuit that defines a timing for refreshing the memory cells. In the first mode, a plurality of N external circuits are provided. The memory cell is refreshed in response to a refresh command input to at least one of the ports, and in the second mode, the memory cell is refreshed at a timing specified by the refresh circuit.
[0156]
In the above invention, by preparing an operation mode in which a refresh operation is performed by designating from an external port and an operation mode in which a refresh operation is performed in accordance with an instruction of the built-in refresh circuit, for example, a predetermined external port is used for refresh management. Depending on the system configuration, it is possible to operate so that a refresh command is periodically input as a port, or when the refresh management port is in an inactive state, a refresh operation can be executed by a built-in refresh circuit. Refresh management can be performed flexibly.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining the operation principle of the present invention.
FIG. 2 is a diagram illustrating a refresh operation when only one of a plurality of ports is operated.
FIG. 3 is a diagram for explaining the principle of the present invention in the case of 2 ports, 3 ports, and N ports;
FIG. 4 is a block diagram showing a first embodiment of a multi-port memory according to the present invention.
FIG. 5 is a configuration diagram of a circuit related to command input to an arbiter.
FIG. 6 is a circuit diagram showing a configuration of an arbiter.
FIG. 7 is a timing chart showing the operation of the arbiter.
FIG. 8 is a configuration diagram of a circuit related to address input to a DRAM core.
FIG. 9 is a configuration diagram of a circuit related to data output.
FIG. 10 is a circuit diagram showing a configuration of a transfer signal generation circuit.
FIG. 11 is a configuration diagram of a circuit related to data input.
FIG. 12 is a timing chart showing an operation when Read commands are continuously input.
FIG. 13 is a timing chart showing an operation when a Write command is continuously input.
FIG. 14 is a timing diagram showing a case where both ports A and B operate at the maximum clock frequency.
FIG. 15 is a timing diagram showing a case where both ports A and B operate at the maximum clock frequency.
FIG. 16 is a timing chart showing an operation when a command is switched from Read to Write.
FIG. 17 is a diagram illustrating a timing when a refresh command is input when the command is switched from Read to Write.
FIG. 18 is a timing chart showing the operation when one port is deactivated.
FIG. 19 is a timing chart showing an operation when both ports are deactivated.
FIG. 20 is a timing chart showing the operation of the DRAM core.
FIG. 21 is a timing chart showing a double speed operation when only one port is operated.
FIG. 22 is a timing chart showing a double speed operation in which the clock frequency is doubled and the data transfer rate is doubled.
FIG. 23 is a diagram for explaining a second embodiment of the present invention.
FIG. 24 is a block diagram showing a second embodiment of the multi-port memory according to the present invention.
FIG. 25 is a timing chart for explaining a continuous mode.
FIG. 26 is a timing chart showing an operation when a BUSY occurs in A port Read and B port Write.
FIG. 27 is a timing chart showing an operation when BUSY occurs in Read of A port and Write of B port;
FIG. 28 is a timing chart showing an operation when BUSY occurs at the write of the A port and the write of the B port.
FIG. 29 is a timing chart showing an operation in the case where a BUSY occurs at the write of the A port and the write of the B port.
FIG. 30 is a timing chart showing an operation when the controller is configured to be able to insert an interrupt.
FIG. 31 is a diagram showing a configuration of an address comparator, a BUSY input / output system, and an interrupt system in a multi-port memory according to a second embodiment of the present invention.
FIG. 32 is a timing chart showing the operation of the master device.
FIG. 33 is a timing chart showing the operation of the slave device.
FIG. 34 is a timing chart showing the operation of the master device when the write addresses of both ports match.
FIG. 35 is a timing chart showing the operation of the slave device when the write addresses of both ports match.
FIG. 36 is a timing chart showing the operation of the master device when the write address of both ports coincides and an interrupt instruction is issued from the controller.
FIG. 37 is a timing chart showing the operation of the slave device when an interrupt instruction is issued from the controller when the write addresses of both ports match.
[Explanation of symbols]
10 Multiport memory
11 A port
12 B port
13 Self-refresh circuit
14 DRAM core
15 Arbiter
16 Refresh command register
17 Command register A
18 Command register B
19 Refresh address register
20 Address register A
21 Address register B
22 Write data register A
23 Write data register B
24 Transfer gate A
25 Transfer gate B

Claims (14)

A plurality of N external ports each receiving a command;
An internal circuit that sequentially executes at least N access operations during a minimum interval between a plurality of commands input to one of the external ports;
An arbitration circuit for determining a command execution order for causing the internal circuit to execute a plurality of commands respectively input from the N external ports;
An address comparison circuit for determining whether or not there are a plurality of commands for accessing the same address among a plurality of commands respectively input from the plurality of N external ports ;
Includes a master operation mode or a mode register that specifies the slave operation mode,
Each of the N external ports is
A signal output circuit for outputting a predetermined signal to the outside of the device when there are a plurality of commands for accessing the same address; and
A signal input circuit for receiving the predetermined signal from the outside of the device;
A circuit for supplying serially received data to the internal circuit as parallel data;
Including a circuit for outputting data supplied in parallel from the internal circuit to the outside as serial data;
The internal circuit includes a cell array composed of dynamic memory cells,
A semiconductor memory device comprising: activating the signal output circuit when the mode register designates a master operation mode; and activating the signal input circuit when the mode register designates a slave operation mode. .   2. The semiconductor device according to claim 1, wherein when the signal input circuit receives the predetermined signal from the outside of the apparatus when the mode register specifies a slave operation mode, the arbitration circuit changes the command execution order. Storage device.   A normal operation mode and a continuous operation mode are provided. In the normal operation mode, a process of selecting an ROW, executing an operation corresponding to one command, and performing a precharge is performed in one internal operation cycle. The process of selecting and continuously executing and precharging operations corresponding to a plurality of commands is executed in one internal operation cycle, and the normal operation mode and the continuous operation mode are switched based on the comparison result of the address comparison circuit. 3. The semiconductor memory device according to claim 2, wherein:   4. The semiconductor memory device according to claim 3, wherein when a plurality of commands to be processed in the continuous operation mode are write commands, one command is selected and executed, and the remaining commands are not executed.   The operation of transmitting the predetermined signal to the outside of the apparatus or receiving from the outside of the apparatus is a period provided between the process of selecting ROW in the continuous operation mode and the process of continuously executing operations corresponding to a plurality of commands. 4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is executed.   6. The semiconductor memory device according to claim 5, wherein the period is variable. A plurality of N external ports each receiving a command;
An internal circuit that sequentially executes at least N access operations during a minimum interval between a plurality of commands input to one of the external ports;
An arbitration circuit for determining a command execution order for causing the internal circuit to execute a plurality of commands respectively input from the N external ports;
An address comparison circuit for determining whether or not there are a plurality of commands for accessing the same address among a plurality of commands respectively input from the plurality of N external ports ;
Includes circuitry for receiving an interrupt signal transmitted from an external controller in response to a Jo Tokoro signal,
Each of the N external ports is
A signal output circuit for outputting the predetermined signal to the outside of the device when there are a plurality of commands for accessing the same address;
A circuit for supplying serially received data to the internal circuit as parallel data;
Including a circuit for outputting data supplied in parallel from the internal circuit to the outside as serial data;
The internal circuit includes a cell array composed of dynamic memory cells,
The semiconductor memory device, wherein the arbitration circuit changes the command execution order when the interrupt signal is received. A normal operation mode and a continuous operation mode are provided. In the normal operation mode, a process of selecting an ROW, executing an operation corresponding to one command, and performing a precharge is performed in one internal operation cycle. A step of selecting and continuously executing and precharging operations corresponding to a plurality of commands is executed in one internal operation cycle, and a normal operation mode and a continuous operation mode are switched based on a comparison result of the address comparison circuit, The operation of receiving an interrupt signal is performed in a period provided between a process of selecting ROW in the continuous operation mode and a process of continuously executing operations corresponding to a plurality of commands. Item 8. The semiconductor memory device according to Item 7 . A plurality of N external ports each receiving a command;
Including an internal circuit that sequentially executes at least N access operations during a minimum interval between a plurality of commands input to one of the external ports,
A cell array composed of dynamic memory cells;
A refresh circuit for defining a timing for refreshing the memory cell; in the first mode, the memory cell is refreshed in response to a refresh command input to at least one of the plurality of N external ports; A semiconductor memory device, wherein in the mode, the memory cell is refreshed at a timing designated by the refresh circuit.   10. The semiconductor memory device according to claim 9, wherein the second mode is set when at least one of the plurality of N external ports is inactive.   10. The semiconductor memory device according to claim 9, wherein an external port for inputting the refresh command among the plurality of N external ports can be designated from outside the device.   12. The semiconductor memory device according to claim 11, wherein the second mode is set when the external port for inputting the refresh command among the plurality of N external ports is inactive.   12. The semiconductor memory device according to claim 11, further comprising a mode register for designating an external port for inputting the refresh command among the plurality of N external ports.   Each of the N external ports includes a clock terminal for receiving a clock signal from the outside and operates in synchronization with the clock signal, and the signal input circuit and the signal output circuit operate asynchronously with the clock signal. The semiconductor memory device according to claim 1.

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