JP2000268573A - Semiconductor storage device - Google Patents

Abstract

(57) [Problem] To provide a multi-port semiconductor memory device capable of performing a stable operation even when a read operation and a write operation are simultaneously instructed to the same address. A semiconductor memory device includes a memory cell array that can be accessed independently from input / output ports. When a read operation and a write operation are instructed simultaneously for the same address, data corresponding to the write operation is temporarily stored in register circuit 140 together with the address signal. Access control circuit 1
Numeral 30 is for reading data between the memory cell array, the register circuit, and the input / output port in accordance with the result of the comparison between the register storage address and the input address signal and the completion of the write operation of the register storage data to the memory cell array. Controls operation and write operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a plurality of input / output ports,
The present invention relates to a multiport storage device that can be accessed independently from each input / output port.

[0002]

2. Description of the Related Art Hitherto, a multiport storage device capable of performing a data input / output operation independently of a plurality of external access systems has been developed. In particular, a memory that can read / write data by designating an address independently from two access systems for one memory cell array is called a dual port memory and is widely used.

FIG. 25 shows a dual port S of the prior art 1.
FIG. 2 is a schematic block diagram for explaining an overall configuration of a RAM (Static Random Access Memory) 500.

Referring to FIG. 25, a dual port SRA
M500 has a memory cell array 510, input / output circuits 520 and 530 capable of performing read and write operations on the memory cell array independently of each other, and inputs and outputs two independent sets of address signals, data signals and command signals. And an output terminal group 540.

[0005] The input / output terminal group 540 receives the clock signal CL.
K, address signals A1 and A2, and write signals W1 and W2.
, Write data signals D1 and D2, and read data signal Q
1 and Q2. The input / output terminal group 540 specifies a first port 541 for inputting / outputting a set of an address signal A1, a data signal D1, Q1 and a write control signal W1 for specifying one access operation, and another independent access operation. Address signal A2 and data signals D2, Q2
Port 5 for inputting / outputting a set of write control signals W2
42.

The clock signal CLK is a dual port SR
This is a clock signal for controlling the entire operation of the AM 500. Further, write control signals W1 and W2 are command signals which are set to H level when a write operation is instructed and set to L level when a read operation is instructed.

An input / output circuit 520 is a circuit for writing data D1 or reading data Q1 to a memory cell specified by an address signal A1 input from a first port. The input / output circuit 520 includes an address decode circuit 521 and a read / write circuit 522. The address decode circuit 521 outputs the address signal A
A specific memory cell is selected according to 1. Read / write circuit 522 transmits and receives read data Q1 and write data D1 to and from a memory cell via a bit line corresponding to an address signal.

The input / output circuit 530 is a circuit for accessing a memory cell designated by the address signal A2 input from the second port, and has the same structure and operation as the input / output circuit 520.

Memory cell array 510 includes a memory cell 503 including inverters 501 and 502 connected in a cross-like manner, and access transistors 505 to 508 provided for memory cell 503.
Word lines WL1 and WL2 are provided corresponding to each row of memory cells 503. Word line WL1 is connected to address decode circuit 521 operating in response to address signal A1.
Is selectively activated. Similarly, the word line W
L2 is selectively activated by the address decode circuit 531 in response to the address signal A2. That is,
In each row of the memory cells of the dual-port SRAM 500, two word lines are independently provided, and each word line is driven by an independent address signal.

[0010] Data stored in memory cell 503 is transferred to word line W by access transistors 505 and 507.
The signal is transmitted to the bit line BL1 in response to the activation of L1. Bit line BL1 is connected to read / write circuit 522.
Similarly, data in memory cell 503 is supplied to access transistors 506 and 50 in response to activation of word line WL2.
8 to the bit line BL2. Bit line BL
The data of No. 2 is exchanged with the read / write circuit 532.

With such a configuration, in the dual port memory SRAM, the first port and the second port
It is possible to access using either of the ports. Also, even when different memory cells are simultaneously accessed from both input / output ports, the input / output circuits, word lines, and bit lines used for accessing the memory cells are respectively connected to the first port and the second port. Since they are provided correspondingly and independently, they can be accessed without being affected by each other.

As an example of a semiconductor memory device having a memory cell array configuration (hereinafter, referred to as a multi-port memory cell configuration) capable of accessing a memory cell independently from a plurality of paths as in Conventional Example 1, Japanese Patent Laid-Open No. -4478
A technique disclosed in Japanese Patent Publication No. 3 (Japanese Patent Publication No. 3) is also disclosed (hereinafter referred to as Conventional Technique 2).

FIG. 26 is a block diagram showing the overall configuration of a semiconductor memory device using a multiport memory cell according to prior art 2.

Referring to FIG. 26, a semiconductor memory device 600 of the prior art 2 has two independent word lines 601A and 601B for memory cell 603 and independent bit line pairs 602A1, 602A2 and 602B1 and 602B.
2 and are controlled by independent row and column decoders, respectively. Therefore, the semiconductor memory device 600
Has two independent access systems.

In the semiconductor memory device 600,
The transmission and reception of the data signal accompanying the read / write operation is performed by a commonly provided output unit 607 and write control unit 606, and the same address signal is applied to two row / column decoders in the same cycle.

FIG. 27 is a timing chart for explaining the operation timing of semiconductor memory device 600.

Referring to FIG. 27, a semiconductor memory device 600
, Two independent access systems, a first system (A) and a second system (B), operate based on the same address signal, and one of the access systems actually performs read / write.
When performing a write operation, the other system performs a precharge operation of a bit line.

That is, semiconductor memory device 600 uses one of the access systems alternately for the charge-up operation, and shortens the pre-charge time to shorten the overall read / write operation time. It is the purpose. Therefore, writing / writing to the memory cell is actually performed.
The read operation is performed by one of the access systems specified alternately.

[0019]

However, in the dual-port SRAM of the prior art 1, a problem arises when read and write operations are simultaneously specified from each of two access systems for the same address in the same cycle. Occurs. That is, in this case,
It becomes impossible to identify whether the data signal read by the read operation is the data stored in the memory cell before the access in this cycle or the data newly written in this cycle. Therefore, in the conventional dual port memory, the timing is controlled from outside the memory device so that such access, that is, simultaneous execution of the read operation and the write operation to the same address at the same timing is not performed. A new circuit had to be provided.

In the prior art 2, although the time required for the read / write operation can be reduced by shortening the precharge time, it is necessary to perform the read / write operation following the memory cell at the same address. Since the number of addresses that can be accessed in one cycle is limited to a single address, the operation cycle cannot be sped up, and the effect of the multiport memory cell configuration cannot be sufficiently enjoyed.

An object of the present invention is to solve the above-mentioned problems, and more specifically, in a case where a read operation and a write operation are simultaneously performed on the same address in the same cycle. However, an object of the present invention is to provide a configuration of a multiport storage device capable of performing a stable operation without destruction of data without requiring external timing control.

[0022]

According to a first aspect of the present invention, there is provided a semiconductor memory device which performs reading and writing operations of data signals independently by a first plurality of access systems, wherein the semiconductor memory device is arranged in a matrix. A memory cell array having a plurality of memory cells arranged in the memory cell array. The memory cell array has a first plurality of word lines provided independently for each row of the memory cells, and a memory cell array for each column of the memory cells. A first plurality of input / output ports including a first plurality of bit lines provided independently of each other, for transmitting and receiving each of a set of a first plurality of address signals, data signals, and command signals; Input / output circuit for performing a data signal read or write operation in response to a command signal with respect to a memory cell corresponding to an address signal. When, in response to the register control signal,
When it is detected that the read operation and the write operation for the same memory cell are instructed at the same timing at the same timing, the register circuit stores the address signal and the data signal and temporarily stores the same. A write operation is performed in accordance with whether the stored address signal matches the address of the same memory cell and whether the data signal currently stored in the register circuit has been completely written to the memory cell array. An access control circuit for activating a register control signal to temporarily save the data signal is further provided.

A semiconductor memory device according to a second aspect is the semiconductor memory device according to the first aspect, wherein the address signal is n
A digital signal of m bits, the data signal has a digital signal of m bits, the first plurality is k (k is a natural number and an even number of 2 or more), and the register circuit has (n
(M) · (k / 2) bit digital signal.

A semiconductor memory device according to a third aspect is the semiconductor memory device according to the first aspect, wherein the address signal is n.
The first plurality includes k (where k is a natural number and an odd number of 2 or more), and the register circuit includes (n
+ M) · (k−1) / 2 bits.

According to a fourth aspect of the present invention, in the semiconductor memory device of the first aspect, the access control circuit is provided for each combination of two input / output ports of the first plurality of input / output ports. And a simultaneous access detection signal which is activated when a read operation and a write operation are instructed at the same timing by the two input / output ports with respect to the same memory cell. A register address match determination that generates a register address match signal activated when a register storage address, which is an address signal stored in the detection circuit and an address signal stored in the register circuit, matches the address signal input to the input / output port. Circuit and a memory cell in which register stored data, which is a data signal stored in the register circuit, corresponds to the register stored address A control flag generation circuit for generating a control flag signal that is deactivated when data has already been written, wherein the access control circuit generates a control flag signal and a control flag signal when the simultaneous access detection signal is activated. The register control signal is activated when one of the register address match signals is inactivated.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, the access control circuit is configured to control the simultaneous access detection signal and the control flag when the register address match signal is activated. An output data selection circuit for transmitting one of the data stored in the register and the storage data of the memory cell corresponding to the address signal to an input / output port instructed to perform a read operation in response to a control signal; In this case, one of the data stored in the register and the data signal corresponding to the write operation is sent to the input / output port to which the write operation is instructed in accordance with the simultaneous access detection signal and the register address match signal. And an input data selection circuit for transmitting the data to a corresponding input / output circuit.

According to a sixth aspect of the present invention, in the semiconductor memory device of the fifth aspect, the access control circuit activates the control flag signal when the simultaneous access detection signal is activated, When the register address coincidence signal is inactive, writing of the register storage data to the memory cell corresponding to the register storage address is instructed to the I / O circuit corresponding to the I / O port to which the write operation is instructed. .

According to a seventh aspect of the present invention, in the semiconductor memory device of the fifth aspect, the access control circuit activates the control flag signal when the simultaneous access detection signal is inactivated. And when the register address match signal is activated, the input / output circuit corresponding to the input / output port for which the read operation is instructed receives the register storage data from the memory cell corresponding to the register storage address. Instruct writing.

According to an eighth aspect of the present invention, in the semiconductor memory device of the fourth aspect, each input / output circuit operates based on a common clock signal, and the simultaneous access detection circuit operates based on the clock signal. At each activation timing, the simultaneous access detection signal is activated in accordance with the match between the address signals and the mismatch between the command signals input to each of the two input / output ports.

According to a ninth aspect of the present invention, there is provided the semiconductor memory device according to the fourth aspect, wherein each of the input / output circuits operates by an independent clock signal transmitted to a corresponding input / output port. The access detection circuit
A clock pulse generating circuit provided for a clock signal transmitted to each of the I / O ports and generating a clock pulse signal activated for a predetermined period from the rising timing of the clock signal; An address match determination circuit for determining a match between address signals input to each of the ports, wherein the simultaneous access detection circuit corresponds to each of the two input / output ports during a period in which each clock pulse signal is activated. The simultaneous access detection signal is activated according to the state of the command signal to be executed and the result of the judgment by the address coincidence judgment circuit.

According to a tenth aspect of the present invention, there is provided the semiconductor memory device according to the ninth aspect, wherein the predetermined period is set longer than a time required for a data signal read operation in the memory cell array, and the simultaneous access detecting circuit is provided. Means that a read operation is instructed to the input / output port corresponding to the clock pulse signal and a write operation is instructed to the other input / output port during a period in which the clock pulse signal is activated. Activate the simultaneous access detection signal when the address signals input to each of the two input / output ports match.

A semiconductor memory device according to an eleventh aspect includes a memory cell array having a plurality of memory cells arranged in a matrix, and the memory cell array includes a second plurality of memory cells provided independently of each other for each row of the memory cells. An input / output port for transmitting / receiving a clock signal, an address signal, a data signal, and a command signal, the input / output port including a plurality of word lines and a second plurality of bit lines provided independently of each other for each column of the memory cells. A second plurality of input / output circuits capable of independently performing a read operation or a write operation of a data signal in response to a command signal with respect to a memory cell corresponding to an address signal; An access switching circuit for distributing and supplying the command signal to each of the second plurality of input / output circuits. By dividing the clock signal, an internal clock generation circuit having activation timings independent of each other and generating an internal clock signal corresponding to each of the second plurality of input / output circuits, A flip-flop circuit for transmitting an address signal, a data signal, and a command signal to a corresponding input / output circuit, and a register circuit for receiving and temporarily storing an address signal and a data signal in accordance with a register control signal. When it is detected that the read operation and the write operation for the same memory cell are instructed at the same timing, the address signal currently stored in the register circuit matches the address of the same memory cell. And the presence of
Access control circuit for activating a register control signal to temporarily save a data signal corresponding to a write operation according to whether or not writing of a data signal currently stored in a register circuit to a memory cell array is completed And further comprising:

According to a twelfth aspect of the present invention, in the semiconductor memory device of the eleventh aspect, the address signal has an n-bit digital signal and the data signal has an m-bit digital signal.
The second plurality has k digital signals (k: a natural number of 2 or more and an even number), and the register circuit can store (n + m) · (k / 2) -bit digital signals. A storage circuit;

According to a thirteenth aspect of the present invention, a semiconductor memory device according to the first aspect is provided.
1. The semiconductor memory device according to 1, wherein the address signal is n
The first plurality includes k (where k is a natural number and an odd number of 2 or more), and the register circuit includes (n
+ M) · (k−1) / 2 bits.

According to a fourteenth aspect of the present invention, in the semiconductor memory device according to the eleventh aspect, the access control circuit is provided for each combination of two input / output circuits of the second plurality of input / output circuits. At the same timing.
A simultaneous access detection circuit for generating a simultaneous access detection signal activated when read operation and write operation are instructed by the input / output circuits for the same memory cell in duplicate, and stored in the register circuit A register address match determination circuit that generates a register address match signal that is activated when a register storage address, which is an address signal that has been input, matches an address signal input to an input / output port; A control flag generating circuit for generating a control flag signal which is deactivated when register data which is a data signal stored in the memory cell corresponding to the register storage address has already been written, When the simultaneous access detection signal is activated, the circuit matches the control flag signal with the register address. Either the No. activates the register control signal when being deactivated.

A semiconductor memory device according to a fifteenth aspect is the semiconductor memory device according to the eleventh aspect, wherein the semiconductor memory device is provided for each combination of two input / output circuits of the second plurality of input / output circuits, and A simultaneous access detection circuit that generates a simultaneous access detection signal that is activated when a read operation and a write operation are instructed in the same memory cell at the same time; A clock pulse generation circuit provided for each of the internal clock signals, for generating a clock pulse signal activated for a predetermined period from the rising timing of the internal clock signal, and an address corresponding to each of the corresponding two input / output circuits An address match determination circuit for determining signal match, and the simultaneous access detection circuit includes an activation timing for each clock pulse signal. In ring in accordance with the determination result of the state and the address match determining circuit command signals corresponding to each of the two input-output circuit, to activate the simultaneous access detection signal.

A semiconductor memory device according to a sixteenth aspect is the semiconductor memory device according to the fifteenth aspect, wherein the predetermined time is set longer than a time required for a data signal read operation in the memory cell array, and the simultaneous access detection circuit During a period in which a clock pulse signal is activated, a read operation is instructed to the corresponding input / output circuit, and a write operation is instructed to the other input / output circuit. The simultaneous access detection signal is activated when the address signals corresponding to the input / output circuits match.

[0038]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[First Embodiment] FIG. 1 is a schematic block diagram showing an overall configuration of a semiconductor memory device 100 according to a first embodiment of the present invention.

In the embodiment of the present invention, a dual port SRAM memory will be described as an example. However, the application of the present invention is not limited to the SRAM memory. That is, it is sufficient that each memory cell has a multi-port memory cell configuration accessible by a plurality of independent systems, and the configuration of the memory cell itself is not limited.

Referring to FIG. 1, a semiconductor memory device 100 according to the first embodiment of the present invention has a clock signal
A group of input / output terminals 105 for transmitting and receiving control signals and address signals, a memory cell array 110 including memory cells arranged in rows and columns, data reading and reading for addresses specified independently of each other with respect to the memory cell array. Input / output circuits 120a, 12 capable of performing writing
0b, that a read operation and a write operation are simultaneously instructed to a memory cell at the same address in the same cycle (hereinafter, also referred to as “simultaneous access”), and access to the memory cell of each gate at the time of simultaneous access. , And a register circuit 140 for temporarily storing externally written data when simultaneous access is performed.

The input / output terminal group 105 receives the clock signal CL
K, address signals A1 and A2, and write signals W1 and W2.
, Write data signals D1 and D2, and read data signal Q
1 and Q2. The input / output terminal group 105 designates a first port 106a for inputting and outputting a set of an address signal A1, a data signal D1, Q1 and a write control signal W1 for specifying one access operation, and another independent access operation. Address signal A2 and data signals D2, Q
2 and a second port 106b for inputting / outputting a set of write control signals W2.

The clock signal CLK is supplied to the dual port S
This is a clock signal for controlling the operation of the entire RAM. Write control signals W1 and W2 are signals for controlling a read / write operation to the memory cell array. When activated (H level), a write operation is instructed, and when inactive (L level), read operation is performed. Operation is instructed.

Input / output circuit 120a transmits and receives data to and from a corresponding memory cell in response to write control signal W1 and address signal A1 input to the first port, and writes write data signal D1. And read data signal Q
1 is read. Similarly, input / output circuit 120b reads or writes data of a corresponding memory cell in the memory cell array according to write control signal W2 and address signal A2 input to the second port, and reads data signal Q2 Or the input of the write data signal D2.

The two access operations by the first port and the second port can be performed independently. That is, different memory cells can be accessed at the same clock timing without affecting each other.

The register circuit 140 includes an address register 142 and a data register 144. The address register and the data register temporarily store an address signal and a write data signal related to a write operation when simultaneous access is instructed, and perform a read operation at the timing to destroy data before access. This is a circuit provided in order to stably perform the write operation and to store the write data in the memory cell corresponding to the address. Register circuit 140 operates in response to a register control signal RT, and stores an address signal and a data signal applied to an input node as storage address RA and storage data RD.

The access control circuit 130 compares the simultaneous access detection circuit 150 for detecting simultaneous access with the address currently stored in the register circuit 140 and whether the input address signals A1 and A2 match. And a register address match comparison circuit 168 for generating an address match signal.

Simultaneous access detection circuit 150 receives address signals A1 and A2 and write control signals W1 and W2, and performs a read operation on memory cells at the same address from the first and second ports at the same timing. This circuit activates the simultaneous access detection signal ERR when a write operation is instructed at the same time.

The register address match comparison circuit 168
When the address signal A1 matches the address signal RA stored in the address circuit, the register address match signal MAT1 is activated. When the address signal A2 matches the address signal RA, the register address match signal MAT2 is activated. , Register address match signal MAT is activated when at least one of signals MAT1 and MAT2 is activated.

The access control circuit 130 includes a control flag generation circuit 169 for generating a control flag FLG indicating the validity / invalidity of data stored in the register, and a main control circuit 17
0.

When the storage data RD of the register has been written in the memory cell corresponding to the storage address RA, the control flag generation circuit 169 sets the control flag FLG to L level, and stores the storage data RD in the memory cell array. Is not written yet, the control flag FLG is set to the H level.

Main control circuit 170 activates register control signal RT in response to simultaneous access detection signal ERR, control flag FLG and register address match signal MAT, and supplies an internal clock to each of input / output circuits 120a and 120b. Signals ICLK1 and ICLK2
Is output. When the simultaneous access is instructed, the internal clock signal is inactivated to instruct the I / O circuit corresponding to the I / O port to which the write operation is instructed to suspend the write operation.

Access control circuit 130 further includes an input selection circuit 162, an output selection circuit 164, and a data selection circuit 166 provided for adjusting the data flow when simultaneous access is instructed. .

Input select circuit 162 normally transmits write data signals D1 and D2 to input / output circuits 120a and 120b, but stores data RD stored in register circuit 140 in a memory cell array as necessary. The signal is transmitted to the input / output circuits 120a and 120b. Similarly, output selection circuit 164 normally provides memory cell storage data MCDa, MC
Db is transmitted as input / output data, and data RD stored in register circuit 140 is transmitted as output data as necessary.

The data selection circuit 166 receives the simultaneous access detection signal ERR and the write signals W1 and W2 of each gate.
, And transmits one of write data signals D1 and D2 to an input node of register circuit 140.

The detailed configuration of the semiconductor memory device 100 will be further described below with reference to the drawings. FIG. 2 is a block diagram for describing in detail the configuration of the memory cell array 110 and the input / output circuits 120a and 120b in the semiconductor memory device 100.

Referring to FIG. 2, memory cell array 110
Includes a memory cell 101 formed by cross-connecting two inverters 102 and 104. In memory cell array 110, word lines WLa and WLb are provided for each memory cell column. Two bit line pairs BLa, / BLa and BLb, / BLb are provided for each column of memory cells.

The data in the memory cell 101 is stored in the word line W
Bit lines BLa and / BL are provided by access transistors 111 and 112 each having a gate connected to La.
a. Similarly, access transistors 113 and 11 having gates connected to word line WLb
4, the data of the memory cell 101 is stored in the bit line pair B
Lb and / BLb.

The input / output circuit 120a includes an address decoder 122a and a read / write circuit 124a, and is configured by a word line WLa and a bit line pair BLa, / BLa.
Data is input / output to / from a selected memory cell in accordance with address signal A1 and write control signal W1 input to the first port. Similarly, the input / output circuit 120b
Are the address decode circuit 122b and the read / write circuit 1
24b. The input / output circuit 120b is connected to the word line WL
b and the bit line pair BLb, / BLb, the second
Data is input / output to / from a selected memory cell according to address signal A2 and write control signal W2 input to the port.

As described above, since input / output circuits, word lines, and bit line pairs are independently arranged for the two access systems for memory cell array 110, each input / output system has different memory cells. , The reading and writing operations can be simultaneously performed independently of each other without performing any special control.

FIG. 3 is a circuit diagram showing a specific configuration of the simultaneous access detection circuit 150. Simultaneous access detection circuit 150 is a circuit that activates simultaneous access detection signal ERR when read and write operations are instructed redundantly from the first port and the second port for the same memory cell.

Simultaneous access detection circuit 150 receives n-bit (n; natural number) address signals A1 and A2, determines whether or not both match, and writes write control signal W1 to the first port and second control signal W1 to the second port. The comparison with the write control signal W2 to the port is performed.

Simultaneous access detection circuit 150 includes n logic gates that compare and match each bit of address signals A1 and A2 and output an H level when they match. FIG. 3 shows, as a representative, a logic gate LG1 for determining the coincidence between A1 <0> and A2 <0> which are the first bits of the address signal, and A1 <n-1> and A2 which are the last bits of the address signal. Logic gate LG2 that performs a match determination with <n-1> is shown.

The simultaneous access detection circuit 150 further comprises
A logic gate LG3 that outputs an H level when the write control signals W1 and W2 do not match, and a logic gate LG4 that receives the outputs of the logic gates LG1 to LG3 for determining a match as inputs. Logic gate LG4 outputs a simultaneous access detection signal ERR. With such a configuration, the simultaneous access detection signal ERR indicates that the access to the same memory cell is designated by the first port and the second port, and that the write control signals W1 and W2 do not match. That is, when the read operation and the write operation are instructed in an overlapping manner, they are activated (H level).

FIG. 4 shows a register address match comparison circuit 1.
68 is a circuit diagram showing a configuration of the embodiment 68. FIG. The register address coincidence comparing circuit stores the storage address RA stored in the register circuit 140 and the input address signals A1 and A2.
Is a circuit for determining whether or not.

Referring to FIG. 4, register address match comparison circuit 168 calculates the first bit of the address signal
A logic gate LG5 for judging the coincidence between the storage address RA and the address signal A1 and a logic gate LG6 for comparing the coincidence between the storage address RA and the address signal A2 are included. Logic gates LG5 and LG6 are
When the address signal A1 or A2 matches the register storage address RA in the relevant bit, an H level signal is generated. Register address match comparison circuit 168
Includes a similar match comparison circuit for each bit of the address signal.

The result of the coincidence comparison of each bit between the register storage address RA and the address signal A1 is input to the AND operation gate LG9a. Similarly, the result of the comparison of the coincidence of each bit between the register storage address RA and the address signal A2 is input to the AND gate LG9b.

The AND operation gate LG9a outputs an address coincidence signal MAT1, and the AND operation gate LG9b outputs an address coincidence signal MAT2. That is, address match signal MAT1 is activated (H level) when each bit of register storage address RA and address signal A1 completely match, and address match signal MAT1 is similarly set.
2 is activated (H level) when the register storage address RA and the address signal A2 completely match.

The register address match comparison circuit 168
Further, there is provided an OR gate LG10 which receives the address match signals MAT1 and MAT2 as two inputs. OR gate LG
10 outputs an address match signal MAT. Address match signal MAT is activated (H level) when register storage address RA and at least one of input address signals A1 and A2 match.

FIG. 5 is a block diagram showing a configuration of main control circuit 170. Referring to FIG. 5, main control circuit 170 includes:
Register control circuit 17 for generating register control signal RT
2, a flag switching circuit 174 for generating flag setting signals SET and RST, and data switching signals I0, I1, O
1, O2, a data switching control circuit 176 for generating internal clock signals ICLK1, ICLK2, and internal write control signals IW1, IW2.
And a write control circuit 179 for generating the same. Hereinafter, the detailed configuration of each control circuit will be further described.

FIG. 6 is a circuit diagram showing a configuration of register control circuit 172. When the simultaneous access is instructed, the register control circuit 172 sets the register circuit 14 in accordance with the state of the control flag FLG and the address match signal MAT.
A register control signal RT for activating an address signal and data signal fetch operation at 0 is activated.

Referring to FIG. 6, register control circuit 172
Is an inverter IV25 for inverting the control flag FLG.
And an inverter IV for inverting the address match signal MAT.
26, the simultaneous access detection signal ERR and the inverter IV
AND gate LG20 which outputs the logical product of the outputs of 25
And the simultaneous access detection signal ERR and the address coincidence signal M
AND gate LG2 for outputting the logical product of the inverted signal of AT
1 and an OR operation gate LG22 that outputs a logical sum operation of the AND gates LG20 and LG21.

OR gate LG22 outputs a register control signal RT. When the simultaneous access detection signal ERR is activated (H level), the register control signal RT becomes the control flag FLG or the address coincidence signal MAT.
Is at the L level, that is, the storage data RD of the register circuit has already been written into the memory cell corresponding to the storage address RA, or the storage address RA of the register circuit does not match any of the address signals A1 and A2. At this time, it is activated (H level) to store an address signal and a data signal corresponding to a write operation.

FIG. 7 is a circuit diagram showing a configuration of flag switching circuit 174. Flag switching circuit 174 generates a signal SET for setting control flag FLG to H level and a signal RST for setting control flag FLG to L level.

Referring to FIG. 7, flag switching circuit 174
Is an inverter IV27 for inverting the control flag FLG.
, Simultaneous access detection signal ERR and inverter IV27
And an AND gate LG25 having two inputs of an address match signal MAT and a control flag FLG. AND gate LG2
4 outputs a signal SET, and an AND gate LG25 outputs a signal RST.

The flag switching circuit 174 activates the simultaneous access detection signal ERR and sets the control flag FLG to L
When the level is at the level, an operation of newly storing the address signal and the data signal corresponding to the write operation in the register circuit is executed.
Is set to the H level to set the flag setting signal SET to the H level.

When the control flag FLG is at the H level, that is, when the data stored in the register circuit has not yet been written to the memory cell corresponding to the address, the address match signal MAT is at the H level, When any of the address signals A1 and A2 matches the address RA stored in the register circuit, the operation of writing the data RD stored in the address circuit into the memory cell corresponding to the register storage address RA is executed. Accordingly, the flag setting signal RST is set to the H level in order to change the control flag from the H level to the L level.

FIG. 8 is a circuit diagram showing a configuration of data switching control circuit 176. Data switching control circuit 176 generates data switching signals I1, I2, O1, and O2 for selecting switching between regular input / output data and register storage data RD according to an operation instruction of each input / output port.

Referring to FIG. 8, data switching control circuit 17
6, an inverter IV28 for inverting the address match signal MAT1, an inverter IV29 for inverting the address match signal MAT2, an inverter IV30 for inverting the write control signal W1 to the first port, and a write control to the second port. And an inverter IV31 for inverting the signal W2.

The data switching control circuit 176 further receives the simultaneous access detection signal ERR and the output of the inverter IV28 as two inputs, and outputs an AND gate LG31 for outputting a logical product operation result, and outputs the simultaneous access detection signal ERR and the output of the inverter IV29 to two inputs. An AND gate LG32 that outputs a logical product operation result as an input, an OR gate LG33 that has two inputs of the outputs of the AND gate LG31 and the inverter IV30, and two inputs that are the outputs of the AND gate LG32 and the inverter IV31. OR with two inputs
AND gate LG35 having a gate LG34, a control flag signal FLG and an address match signal MAT1 as two inputs.
And control flag signal FLG and address match signal MAT2
And an AND gate LG36 having two inputs.

Logic gates LG33 to LG36 output data switching control signals I1, I2, O1, and O2, respectively.

Control signals I1 and I2 are signals for instructing data switching when performing a write operation at the corresponding input / output ports.

Control signal I1 is stored in the register circuit when the simultaneous access detection signal is activated and address signal A1 does not match register storage address RA, or when a read operation is instructed to the first port. Data R
It is activated to connect D to the input / output circuit 120a.

Similarly, control signal I2 is activated to connect register circuit storage data RD to input / output circuit 120b. Control signals I1 and I2 are used to transmit write data signals D1 and D2 applied to the respective input / output ports to the corresponding input / output circuits 120a and 120b as data to be written into the memory cells during normal operation. Inactivated (L level).

Control signals O1 and O2 are signals for instructing data switching when a read operation is instructed at the corresponding input / output port. In normal operation, data MCDa read from a memory cell is provided. ,
It is inactivated to transmit MCDb as read data signals Q1, Q2. On the other hand, when a read operation for register circuit storage address RA is instructed, storage data RD of the register circuit is transferred to read data signal Q1,
This is a switching signal for directly outputting as Q2.

FIG. 9 is a circuit diagram showing a configuration of clock control circuit 178. Clock control circuit 178 receives clock signal CLK, and receives input / output circuit 120a provided corresponding to the first port according to the state of other control signals.
Internal clock ICLK1 for controlling the input / output operation of
And an input / output circuit 120 provided corresponding to the second port.
internal clock ICLK for controlling the input / output operation of
And 2.

Referring to FIG. 9, clock control circuit 178
Is an inverter I that inverts the address match signal MAT1.
V33, an inverter IV34 for inverting the address match signal MAT2, a control flag FLG and an inverter IV3.
An AND gate LG40 having two inputs of the output of No. 3 and an AND gate LG42 having two inputs of the control flag FLG and the output of the inverter IV34. Clock control circuit 178 further includes a logic gate LG41 for comparing and matching control flag FLG with write control signal W1, a logic gate LG43 for comparing and matching control flag FLG with write control signal W2, and simultaneous access detection. An inverter IV35 for inverting the signal ERR and a simultaneous access detection signal E
OR gate LG having three inputs of an inverted signal of RR, the output of logic gate LG40, and the output signal of logic gate LG41
44, an OR gate LG45 having three inputs of an inverted signal of the simultaneous access detection signal ERR, an output of the logic gate LG42, and an output of the logic gate LG43, and a logic gate LG4.
AND which uses the output of C.4 and the clock signal CLK as two inputs
The gate LG46, the clock signal CLK and the logic gate L
And an AND gate LG47 having the output of G45 as two inputs.

Logic gate LG46 receives internal clock signal I
CLK1 and logic gate LG47 generates internal clock signal ICLK2. Internal clock signal ICLK
1 is supplied to the input / output circuit 120a for controlling the input / output operation of the gate 1, and the internal clock signal ICLK2 is
An input / output circuit 12 for controlling the input / output operation of the gate 2
0b.

Clock control circuit 178, when instructed to perform simultaneous access, deactivates the input / output circuit corresponding to the input / output port to which the write operation is instructed, and performs an internal write operation so as not to execute the write operation. This circuit deactivates the clock signal. Also, logic gates LG44 and LG45
, The simultaneous access detection signal ERR, the control flag FLG, the address match comparison signals MAT1 and MAT2 corresponding to each input / output port, and the write control signal W1
Internal clock signals ICLK1 and ICLK2 generate the same clock signal as clock signal CLK only when it is necessary to access the memory cell array according to the combination of W2.

FIG. 10 is a circuit diagram showing a configuration of write control circuit 179. Write control circuit 179 receives write control signals W1 and W2 and receives internal write control signals IW1 and IW1 for controlling write operations of input / output circuits 120a and 120b, respectively, according to the states of other control signals. And IW2.

Referring to FIG. 10, write control circuit 179
Are an inverter IV100 for inverting the simultaneous access detection signal ERR, an AND gate LG101 having three inputs of an output of the inverter IV100, a control flag FLG, and an address match signal MAT1, an output of the inverter IV100, a control flag FLG, and an address match signal. MAT2 and an AND gate LG102 having three inputs. The write control circuit 179 further includes an OR gate LG1 that receives the output of the logic gate LG101 and the write control signal W1 as two inputs.
03, the output of logic gate LG102 and write control signal W
2 and an OR gate 104 having two inputs.

Logic gate LG103 generates internal write control signal IW1, and logic gate LG104 generates internal write control signal IW2. Internal write control signal IW1
Is applied to input / output circuit 120a to control the write operation instructed to the first port, and internal write control signal IW
2 is supplied to the input / output circuit 120b to control the write operation specified by the second port.

When simultaneous access is not performed, when control flag FLG is at H level and address signal A1 or A2 matches register circuit storage address RA, write control circuit 179 matches the register flag. The writing is instructed to the input / output circuit corresponding to the address.

FIG. 11 is a circuit diagram showing a configuration of control flag generation circuit 169. The control flag generation circuit 169
A control flag FLG indicating whether the storage data stored in the register circuit 140 has been written to the memory cell,
The setting is made in accordance with signals SET and RST generated by flag switching circuit 174.

Referring to FIG. 11, control flag generating circuit 1
69 switches the state of the control flag signal FLG according to the signals SET and RST. Signals SET and RST
Is generated by the flag switching circuit 174 described above, the signal SET is a signal for setting the control flag signal FLG to the H level, and the signal RST is the control flag signal F
This is a signal for setting LG to L level.

The control flag generation circuit 169 outputs the signal SET.
, An inverter IV2 for inverting the signal RST, and two logic gates LG11 and LG12 forming a flip-flop having the outputs of the inverters IV1 and IV2 as two inputs. Control flag generation circuit 169 further includes inverters IV4 and IV6 for transmitting the output of the flip-flop to an output node generating control flag FLG.

Control flag generating circuit 169 further includes an inverter IV5 connected to inverter IV4 so as to form a data latch, and an inverter IV7 similarly connected to inverter IV6.

Data transmission to these data latches and output nodes is controlled by transistor gates TG1 to TG4 which are turned on and off in synchronization with clock signal CLK. That is, in the control flag generation circuit 169,
If an H level signal is input to signal SET at the rising timing of clock signal CLK, flag signal FLG is set to H level. Similarly, when an H level signal is input to the signal RST, the control flag FLG
Is set to L level. When both signals SET and RST are at L level, logic gate LG1
1, the state of the control flag FLG is held by the action of the latch circuit constituted by LG12.

FIG. 12 is a circuit diagram showing the structure of the data selection circuit 166. Data selection circuit 166 receives the write control signal and write data signal of each input / output port and simultaneous access detection signal ERR, and transmits write data signals D1 and D2 to register circuit 140 when necessary. Circuit.

Referring to FIG. 12, data selection circuit 166
Is an output node for generating a data signal D transmitted to the register circuit, a precharge transistor QPC connected between the output node and the power supply voltage Vcc and receiving a simultaneous access detection signal ERR at a gate, and a write data signal D1. Transistor gate TG1 for transmitting to output node
0 and a transistor gate TG11 for transmitting write data signal D2 to an output node.

In data selection circuit 166, when the simultaneous access detection signal is inactive (L level), precharge transistor QPC is turned on, and the output node is at H level.
Level. However, the simultaneous access detection signal ERR
Is activated (H level), precharge transistor QPC is turned off, and when write control signal W1 is activated (H level), transistor gate TG10 is turned on and write data Signal D1
Is transmitted to the output node. Similarly, when the simultaneous access detection signal is activated and at the same time write control signal W2 for gate 2 is activated, transistor gate TG11 is activated and write data signal D2 is transmitted to the output node.

In other words, when simultaneous access is instructed, data selection circuit 166 temporarily saves write data in order to prioritize a read operation.
It serves to transmit the write data to the register circuit.

FIG. 13 is a circuit diagram showing the configuration of address register 142 and data register 144 constituting register circuit 140. Referring to FIG.

Data register 144 takes in input data D provided from data selection circuit 166 in accordance with register control signal RT, and holds it as register storage data RD. The address register 142 takes in the address signal A1 at the same timing and holds it as the register storage address RA.

Referring to FIG. 13, address register 14
2 and data register 144 include inverters IV9 and IV connected in series between an input node and an output node.
10, IV12 and IV14. Inverter IV10
An inverter IV11 is provided in a cross-like manner to form a data latch. Similarly, an inverter IV13 is provided to cross the inverter IV12. Fetching of data from the input node and transmission to the output node are executed by transistor gates TG5 to TG8 in response to activation of register control signal RT.

FIG. 14 is a circuit diagram showing the structure of the input selection circuit 162. The input selection circuit 162 responds to the data switching control signals I1, I2, O1, O2 to input / output circuit 12
0a and final address signal LA transmitted to 120b
1, LA2 and final data signals LD1, LD2.

Referring to FIG. 14, input selection circuit 162
Includes transistor gates TG20 and TG24 that are turned on in response to control signal I1, and transistor gates TG21 and TG25 that are turned on in response to an inverted signal of control signal I1.

The input selection circuit 162 determines that the control signal I1 is H
Level, that is, the transistor gate TG2
When 0 and TG24 conduct, the storage address RA of the register circuit is output as the last address signal LA1, and the storage data RD of the register circuit is output as the last data signal LD1.

Conversely, when control signal I1 is at the L level, normal input address signal A1 and write data signal D1 are set to LA1 and LD1, respectively.
20a. Thus, the input selection circuit 162
Is the last address signal L according to the state of the control signal I1.
A circuit that switches between A1 and the final data signal LD1 as a normal input address signal A1 and a write data signal D1, or an address RA and data RD stored in a register circuit.

Similarly, depending on the state of signal I2, final address signal LA2 and final data signal LD2 can be any one of normal address signal A2 and write data signal D2 and address RA and data RD stored in the register circuit. Crab is selected.

FIG. 15 is a circuit diagram showing the structure of the output selection circuit 164. Output selection circuit 164 responds to control signals O1 and O2 supplied from data switching control circuit 176 to output read data MCDa, MCDa output from the memory cell.
This circuit selects one of MCDb and data RD stored in a register circuit and outputs the selected data as read data signals Q1 and Q2.

Referring to FIG. 15, output selection circuit 164
Are the transistor gate TG28 which is turned on when the signal O1 is at H level, the transistor gate TG29 which is turned on when the signal O1 is at L level, and the transistor gate TG which is turned on when the signal O2 is at H level.
30 and a transistor gate TG31 which is turned on when the signal O2 is at the L level.

When signal O1 is at H level, data RD stored in the register is output as first port read data signal Q1. Conversely, when signal O1 is at L level, read data MCDa from the memory cell
Is output as Q1.

When signal O2 is at H level, transistor gate TG30 is turned on, and register storage data RD is output as read data signal Q2 from the second port. On the contrary, when the signal O1 is at the L level,
Transistor gate TG31 turns on, and read data MCDb from the memory cell is output as Q2.

Next, the operation of semiconductor memory device 100 when simultaneous access is executed will be described with reference to a flowchart.

FIG. 16 is a flowchart for explaining the overall operation of semiconductor memory device 100.

As shown in FIG. 16, the semiconductor memory device 10
The operation of 0 is the simultaneous access detection signal ERR and the control flag F
It is controlled according to the state of LG and the address match signal MAT. In FIG. 16, the H level of each signal is "1".
, The L level is represented by “0”.

The operation of semiconductor memory device 100 is roughly classified according to the state of simultaneous access detection signal ERR.

When the simultaneous access is executed, first, the state of the control flag FLG is checked, and the control flag FLG is checked.
When the value of G is “0”, that is, when the data stored in the register circuit has already been written to the address in the memory cell array, the read operation among the simultaneously accessed operations is normally performed. Then, the address and data are transferred to register circuit 140 in order to temporarily save the write data in the register circuit. Then, since the address and data transferred to this register are not yet stored at the regular address in the memory cell array, the flag FLG is set to 1 (case (a) in the figure).

On the other hand, if the control flag FLG is 1 even when the simultaneous access is executed, the data currently stored in the register circuit has not been written to the memory cell, so that the write operation is performed. Address and data cannot be directly stored in the register circuit.
Therefore, in this case, the operation of (b) or (c) in the figure is performed according to the value of the address match signal MAT.

In this case, address match signal MA
When T is "1", the data at the address currently stored in the register circuit is a target of the read and write operations, so that the data stored in the register circuit may be directly read first. Then, the write operation specified at the same time is performed on the memory cell array.
By this write operation, the write operation according to the latest access instruction has already been completed for the address stored in the register circuit.
May be set to “0” (operation (b) in the figure).

On the other hand, when the address match signal MAT is "0", it is necessary to store the write data signal in the register circuit. Therefore, the data RD currently stored in the register circuit is stored in the register circuit storage address RA. It is necessary to write to the corresponding memory cell. On the other hand, the read operation is executed from the address to which the simultaneous access is instructed. The address and data signals corresponding to the write instruction are newly stored in the register circuit. In this case, since the address and data newly stored in the register circuit have not yet been reflected in the memory cell array, the control flag FLG remains "1" (operation (c) in the figure).

Next, a case where simultaneous access is not instructed, that is, a case where simultaneous access detection signal ERR is "0" will be described. In this case, basically, even if the read and write operations are performed simultaneously, the instructions are issued to the memory cells at different addresses. Therefore, the operations are normally performed independently without special control. be able to.

Therefore, when both the control flag FLG and the address match signal MAT are "1", that is, the data which is not yet written in the memory cell array is stored in the register circuit and is stored in the address. Except when an access is instructed to the address, normal operation is performed (operations (e) and (f) in the figure).

When register data RD stored in the register circuit has not been written in the memory cell and access to register address RA stored in the register circuit is instructed, the read operation is not performed. Performs a read operation of data RD stored in register circuit 140, and performs a write operation on a memory cell array for addresses and data stored in the register circuit. If the access instruction is a write operation, the write operation is directly performed on the memory cell at the specified address. As a result, the data stored in the register circuit up to now is correctly reflected in the memory cell array in any case of operation, so that the control flag FLG is cleared to “0”.

Next, an operation example of the semiconductor memory device 100 will be described based on a timing chart.

FIG. 17 is a timing chart for explaining the overall operation of semiconductor memory device 100. FIG.
In the figure, the shaded portion in the figure indicates that the state may be at the H level or the L level. In the initial state,
The control flag FLG is at the L level.

At time T0 when clock signal CLK is first activated, address A1 is input by the first port.
An operation of writing data D1 [0] to [0] and writing data D2 [0] to address A2 [0] is instructed by the second port. At this time, since the address signals for the operations specified by both input / output ports do not match, the simultaneous access detection signal ERR is at the L level, and the control flag FLG
Is at the L level, a normal operation is performed (FIG. 1).
6 (e)).

At the next clock signal activation timing T1, data D1 [1] is written to address A1 [1] by the first port, and address A1 is written from the second port.
An instruction to read the data of [1] is issued. At this time, the simultaneous access detection signal ER
R is at the H level. At this time, the internal clock signal ICLK1 is kept at the L level by the clock control circuit, and the write operation via the input / output circuit 120a by the first port is not performed. The address signal A1 [1] and the data D1 [1] designated to be written are stored in the register circuit 140, and the control flag FLG is set to H in order to indicate that the data stored in the register circuit is valid. Level. On the other hand, the read operation by the second port is executed as usual ((a) in FIG. 16).

At the next clock activation timing time T2, data D1 [2] is written from the first port to address A1 [2], and address A1 is written from the second port.
An instruction to read the data of [2] is issued. Again,
The signal ERR is set to the H level by the simultaneous access detection circuit. Further, the control flag FLG remains at the H level at the time T1. Therefore, the output of the register circuit is connected to the input / output circuit 120a, and the address and data stored in the register are transferred to the memory cell array. That is, the address A stored in the register
Data D1 [1] is written to 1 [1]. On the other hand, the address A1 corresponding to the write instruction input to the first port
[2] and data D1 [2] are newly stored in the register circuit. The read operation by the second port is executed as usual (operation (c) of FIG. 16).

At the next clock activation timing time T3, data D1 [3] is written from the first port to address A1 [3], and address A2 is written by the second port.
Instruct [3] to write data D2 [3]. In this case, since simultaneous access detection signal ERR is at L level, control flag FLG is at H level and address match signal MAT is at L level, the same operation as in the conventional example is performed. The address A1 [2] and the data D1 [2] transferred at the time T2 remain stored in the register circuit (operation (f) in FIG. 16).

At the next clock activation timing time T4, data D1 [4] is written from the first port to address A1 [4], and address A1 is written from the second port.
An instruction to read the data of [2] is issued. In this case, the simultaneous access detection signal ERR is at L level,
Since the address signal specified by the port is equal to the address signal stored in the register, the address match signal MAT2 goes high. Therefore, the data stored in the register circuit needs to be written to the memory cell array together with the read operation. Therefore, the output of the register circuit is connected to the input / output circuit 120b and the output Q2, and the data D1 [2] is written to the address A1 [2] stored in the register, and at the same time, the data stored in the register is output. D1 [2] is read as read data Q2. Further, since the data stored in the register circuit has been transferred to the memory cell array, the data in the register circuit becomes invalid, and the control flag FLG is set to L level. On the other hand, a normal write operation is performed in the first port (operation (d) in FIG. 16).

At the next clock activation timing T5, the data D1 is transferred from the first port to the address A1 [5].
An operation of writing [5] and reading data of address A1 [5] from the second port is instructed. This operation is performed at time T2
The description is omitted because it is the same as that described above.

At the next clock activation timing T6, data at address A1 [5] is read from the first port, and data D2 is read from address A1 [5] from the second port.
The operation of writing [6] is instructed. In this case, simultaneous access detection signal ERR and address match signals MAT1 and MAT2 attain H level. At this time, since the address at which the read operation is instructed is equal to the address stored in the register circuit, data D1 [5] stored in the register circuit is read from first port as read data Q1. The internal clock signal ICLK1 is kept at L level by the clock control circuit,
While access to the memory cell array is not performed using input / output circuit 120a, internal clock signal ICLK
2 is activated, and by operating the input / output circuit 120b, data D2 [6] is written to the address A1 [5] in the memory cell array. In addition, since the writing of the address stored in the register circuit into the memory cell has already been completed, the control flag FLG is set to the L level (operation (b) in FIG. 16).

As described above, the register circuit for temporarily storing the address and data corresponding to the write operation at the time of the simultaneous access is provided. At each operation timing, the occurrence of the simultaneous access, the input address signal and the address signal being stored in the register circuit are provided. Is performed, data is read and written to the memory cell array while validity / invalidity of data stored in the register circuit is determined, so that read and write operations can be simultaneously performed on the same memory cell. Even when the access is executed, data stored in the memory cell before the access is executed can be normally read, and a write operation can be normally accepted in the same cycle. Further, there is no need to adjust the timing from the outside in order to execute the simultaneous access normally.

In the first embodiment, the case of a dual-port SRAM has been described as an example. However, the same method is applied to a semiconductor memory device having n (n; n ≧ 3, a natural number) input / output ports. It is also possible to apply.

That is, n having n input / output ports
In a port memory, the same effect can be obtained by using n / 2 register circuits ((n-1) / 2 register circuits when n is an odd number). Further, by combining the circuits described in the first embodiment, a simultaneous access detection circuit and a register address match comparison circuit in a semiconductor memory device having a plurality of n input / output ports can be realized, and equivalent effects can be obtained. Is possible.

[Second Embodiment] In the first embodiment, the configuration of the semiconductor memory device in which data is input / output by two independent input / output ports based on the same clock signal has been described. In the second embodiment, a configuration of a semiconductor memory device capable of coping with simultaneous access when two input / output ports operate based on independent clock signals, respectively, is considered.

FIG. 18 is a schematic block diagram showing an overall configuration of a semiconductor memory device 200 according to the second embodiment of the present invention.

Referring to FIG. 18, semiconductor memory device 200
Is compared with the semiconductor memory device 100 of the first embodiment, first, independent clock signals C
LK1 and CLK2 are provided independently. Further, input address signals A1, A2, write data signals D1, D2 and write control signal W1,
A flip-flop circuit 280 for holding W2 is newly provided.

On the other hand, the configurations of memory cell array 110 and input / output circuits 120a and 120b are as described in the first embodiment, and independent access operations can be performed by two input / output ports.

Under this configuration, the clock control circuit 27 included in the simultaneous access detection circuit 250, the control flag generation circuit 269, and the main control circuit 270 to realize the operation for simultaneous access as described in the first embodiment.
8 needs to be different from the semiconductor memory device 100 of the first embodiment. The configuration and operation of other circuits are the same as those of the first embodiment, and therefore description thereof will not be repeated.

FIG. 19 is a circuit diagram showing a configuration of simultaneous access detection circuit 250 of semiconductor memory device 200.

Referring to FIG. 19, simultaneous access detection circuit 250 generates clock signal CLK1 corresponding to the first port.
Clock pulse generation circuit 231 which generates clock pulse CPS1, which is a periodic pulse signal that maintains the H level for a pulse width dt at the rising timing of. The clock pulse generation circuit 231 receives the clock signal CLK1 and delays it by the delay time dt, an inverter IV51 that inverts the output of the delay circuit 251, and an AND that receives the output of the inverter IV51 and the clock signal CLK1 as two inputs. And a gate LG50. Logic gate LG50 generates clock pulse CPS1. This pulse width dt is set to be equal to or longer than the time required for the semiconductor memory device to perform a read operation. That is, during the period in which clock pulse CPS1 is activated (H level), the read operation by the first port is being executed, so that access to the same memory cell by other input / output ports needs to be restricted. There will be.

Simultaneous access detection circuit 250 generates a clock pulse CPS2 which is a periodic pulse signal that maintains the H level for a pulse width dt at the rising timing of clock signal CLK2 corresponding to the second port. A generation circuit 232 is included. The clock pulse generation circuit 232 includes the clock pulse generation circuit 2
31 has substantially the same configuration as that of the first embodiment, and includes a delay circuit 252, an inverter IV53, and a logic gate LG52.

The simultaneous access detection circuit 250 includes address signals A1 and A1 input to respective input / output ports.
An address comparison circuit 253 for performing a comparison of coincidence of two is further included. Address comparison circuit 253 includes a group of logic gates for performing an address match comparison. Logic gate LG54 is a gate that performs a match comparison with respect to the first bit of address signals A1 and A2, which is representatively shown.
This is a logic gate for performing a match comparison of the last bit of 1 and A2. Logic gate LG56 is an AND gate that receives as input each of the results of the match comparison for each bit of the address signal, and includes address signals A1 and A2.
Are completely coincident with each other, the signal ADQ is set to the H level.

Simultaneous access detection circuit 250 further includes an AND gate LG51 having two inputs of an inverted signal of write control signal W1 and clock pulse CPS1. The output of logic gate LG51 is output when clock pulse CPS1 is at H level and write control signal W1 is at L level, that is, during a period when a read operation is instructed to the first port and the read operation is being executed. H level. Similarly, an inverter IV54 and a logic gate LG53 are provided for clock pulse CPS2 and write control signal W2. Simultaneous access detection circuit 250
Is an AND gate LG having three inputs of the output of the logic gate LG53, the write control signal W1, and the address coincidence signal ADQ.
58, the output of logic gate LG51 and write control signal W2
And an AND gate LG59 having three inputs of an address match signal ADQ and an address match signal ADQ.

Therefore, the output of logic gate LG59 attains H level when the output of logic gate LG51 is at high level, that is, when the read operation is instructed to the first port and the read operation is being executed. It is activated when the write operation is instructed to the second port (signal W2 is at H level) and the address signals instructed to the first and second ports match. This corresponds to the fact that the write operation by the second port is instructed to the same address while the read operation by the first port is being executed.

Similarly, in the output of logic gate LG58, the read operation is instructed to the second port, and at the timing when the read operation is being executed, the write operation is instructed to the same memory cell by the first port. In this case, it is set to the H level. Logic gate LG60 outputs an OR operation result of outputs from logic gates LG58 and LG59 as a simultaneous access detection signal ERR. Therefore, even when the first port and the second port are operating based on different clock signals, the simultaneous access detection circuit 250 can control the memory cell whose read operation is being executed by one of the input / output ports. On the other hand, when a write operation instruction is issued by the other input / output port at the same time, this circuit activates (H level) the simultaneous access detection signal ERR.

FIG. 20 is an operation waveform diagram for explaining the operation of simultaneous access detection circuit 250. Referring to FIG.

Referring to FIG. 20, clock pulse CPS1 is generated with a pulse width dt at each rising timing of clock signal CLK1 for the first port. Write control signal W1 is a signal for instructing an operation for the first port. When it is at the H level, a write operation is instructed, and when it is at the L level, a read operation is instructed. Similarly, W2 is a write control signal for the second port. W2 is activated at a timing independent of the clock signal CLK1.

Address match signal ADQ is applied at the output of logic gate LG56 in FIG. 19, and is activated (H level) when address signals A1 and A2 match. First, at the first activation timing T1 of the clock signal CLK1, since the address match signal ADQ is at the H level, the operation for the same memory cell is instructed by the first port and the second port. While the read operation is being performed, that is, the clock pulse C
Since both write control signals W1 and W2 are at the L level during the active period of PS1, this does not apply to the case where read and write operations occur simultaneously in the same memory cell.

Thereafter, at time ta, a write operation is instructed for the same address signal, and write control signal W2 changes to the H level. At this timing, clock pulse CPS1 is already at the L level, that is, at the timing ta. The read operation at one port has been completed. Therefore, the write operation by the second port can be executed independently of the first port without being affected by the write operation.

At activation timing T3 of clock signal CLK1 again, address match signal ADQ is activated, and the operation of the first port and the second port is instructed for the same address.

Here, at time tb, while clock pulse CPS1 is at H level, write control signal W2 changes from L level to H level, and a write operation is started. In this case, the read and write operations have occurred simultaneously in the same memory cell, and independent access cannot be permitted as it is.
RR is activated (H level), and it is detected that read and write operations have repeatedly occurred in the same memory cell at the same timing.

By adopting such a circuit configuration,
Even when the input / output ports operate with different clock signals, it is possible to accurately detect that the read and write operations have occurred at the same timing.

Also in semiconductor memory device 200 of the second embodiment, the operation when read and write operations for the same memory cell are instructed at the same timing at the same timing based on simultaneous access detection signal ERR is adjusted. Things. However, in semiconductor memory device 200, since read and write operations are instructed to each input / output port based on two independent clock signals CLK1 and CLK2, a clock control circuit for generating an internal clock signal and a control flag generation The configuration of the circuit is different from that of the semiconductor memory device 100.

FIG. 21 is a circuit diagram showing a configuration of clock control circuit 278 according to the second embodiment.

Referring to FIG. 21, clock control circuit 27
8 has the same configuration as that of the clock control circuit 178 of the first embodiment. That is, clock control circuit 278 inactivates internal clock signals ICLK1 and ICLK2 when clock control circuit 178 of the first embodiment needs to stop the write operation in simultaneous access based on common clock signal CLK. In response to (L level), internal clock signals ICLK1 and ICLK2 are generated by inactivating clock pulses CPS1 and CPS2 during a simultaneous access operation in which a write operation needs to be restricted.

FIG. 22 shows a structure of a control flag generation circuit 269 according to the second embodiment.

Referring to FIG. 22, control flag generating circuit 2
Reference numeral 69 has the same configuration as that of the control flag generation circuit 169 of the first embodiment in a region surrounded by a dotted line. The control flag generation circuit 269 further includes a clock pulse CPS1.
OR gates LG71, L having two inputs CPS2 and CPS2
G72 and clock pulses CPS1 and CPS
A logic gate LG70 having 2 inputs as two inputs and a logic gate L
Logic gate LG7 forming an RS flip-flop having two inputs of the output of G70 and the output of logic gate LG71
3, LG74.

Control flag generating circuit 269 further includes transistor gates TG74 and TG75 at the last stage, and has an inverter I in response to the output of the flip-flop.
The output of V76 and the output of logic gate LG75 are output as control flag FLG. That is, the control flag generation circuit 269 controls the control flag setting signals SET and RST.
The state of the control flag FLG set in response to the activation of one of the clock pulses CPS1 and CPS2 is latched by the activation of the transistor gates TG70 to TG73, and the clock pulse C
When PS1 and CPS2 are both activated (H level), transistor gates TG74 and TG74
G75 is turned on to generate a control flag FLG.

With such a configuration, the semiconductor memory device 200 has a plurality of input / output ports each operated by an independent clock signal, but the simultaneous access detection signal generated by the simultaneous access detection circuit 250. Even when simultaneous access is instructed by ERR and control flag FLG generated by control flag generation circuit 269, semiconductor memory device 100
The same operation as described above can be performed.

In the second embodiment, a synchronous memory which operates based on a clock signal has been described. However, an asynchronous semiconductor memory device is provided with an address transition detection circuit (ATD circuit) inside the semiconductor memory device. As a result, a control signal corresponding to the clock pulses CPS1 and CPS2 can be generated every time the address signal is switched. Therefore, the use of this control signal can also support simultaneous access.

In the second embodiment, the case of a dual-port SRAM has been described as an example. However, the same method is applied to a semiconductor memory device having n (n; n ≧ 3) input / output ports. It is also possible to apply. That is, in an n-port memory having n input / output ports, n / 2 memories ((n-1) / 2 when n is an odd number)
) Can be configured to obtain the same effect. Further, by combining the circuits described in the second embodiment, a simultaneous access detection circuit and a register address match comparison circuit in a semiconductor memory device having a plurality of n input / output ports can be realized, and equivalent effects can be obtained. Is possible.

[Third Embodiment] In a third embodiment, one memory cell array having a multiport configuration is used.
Consider a high-speed operation when a set of input / output ports is arranged.

FIG. 23 is a schematic block diagram showing an overall configuration of a semiconductor memory device 300 according to the third embodiment of the present invention.

Referring to FIG. 23, memory cell array 11
0 has a multi-port configuration that can be accessed by two independent input / output ports as in the first and second embodiments, and the input / output circuits 120a and 120b can independently read and write data. It is.

The semiconductor memory device 300 is different from the semiconductor memory device 200 of the second embodiment in that the access switching circuit 3
10 is further provided. Also, the input / output terminal group 3
The input / output signals given to 05 are a set of input / output data of an address signal A1, a write data signal D1, a read data signal Q1, and a write control signal W1 in addition to the clock signal CLK.

Access control circuit 310 is a circuit for distributing a set of input / output control signals and data signals to input / output circuits 120a and 120b.

FIG. 24 is a circuit diagram showing a specific structure of access switching circuit 310. Referring to FIG. 24, access switching circuit 310 includes a flip-flop circuit 322 having clock signal CLK as a set input, an inverter IV80 for negatively feeding an output of flip-flop circuit 322 to an input of flip-flop circuit 322, and a flip-flop. Inverter IV81 for inverting the output of circuit 322
And Flip-flop circuit 322 outputs clock signal CLK′1, and inverter IV81 outputs clock signal CLK′2.

Here, clock signals CLK'1 and CLK'2 are complementary clock signals having half the frequency of clock signal CLK and having inverted states with respect to each other. , H periods may be overlapped.

Address signal A1 is supplied to flip-flop circuit 3 having clock signal CLK'1 as a set input.
23, is converted into an address signal A'1 and CLK '
It is converted to A'2 by a flip-flop circuit 324 having 2 as a set input. Similarly, write data signal D1
Is applied to the signals D'1 and D'2 by the flip-flop circuit 32.
5 and 326. Similarly, write control signal W1 is also supplied to flip-flop circuits 327 and 328.
Are converted into control signals W′1 and W′2.

Semiconductor Storage Device 30 in Third Embodiment
0, clock signals CLK'1 and CLK'2, address signals A'1 and A'2, data signals D'1 and D'2 and write control signal W'1 generated by these access switching circuits. And W′2, a circuit group having the same configuration as that of the semiconductor memory device 200 arranged at the subsequent stage can achieve the same effect as the semiconductor memory device 200.

With such a configuration, in semiconductor memory device 300, data transmission and reception can be performed without any problem even if reading operation and writing operation are successively and sequentially performed on the same memory cell. Can be. Therefore, the problem that the read operation and the write operation cannot be accessed in parallel with respect to the same memory cell at the same timing as in the semiconductor memory device shown in the prior art 2 is solved, and the range where simultaneous access can occur is solved. , The frequency of the clock signal CLK can be increased. Thus, the effect of the multi-port memory cell configuration can be fully enjoyed, and the next write operation can be started before the read operation is completed, so that high-speed operation can be performed.

Although the third embodiment has been described with respect to a memory cell having a dual-port configuration, the same technique is applied to a memory cell array having an n-port (n; a natural number of n ≧ 3) multi-port configuration. By applying, it is also possible to enjoy the same effect.

It should be noted that the embodiment disclosed this time is an example in all respects and is not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0178]

According to the semiconductor memory device of the first, fourth, fifth, sixth, and seventh aspects, when a read operation and a write operation for the same memory cell are instructed at the same timing, the operation is repeated.
Since the read operation can be executed after the address signal and the data signal corresponding to the write operation are temporarily stored in the register circuit, the data can be read at the same timing without externally performing special timing adjustment. The operation and the writing operation can be performed normally, and the operation can be speeded up.

According to the semiconductor memory device of the second and third aspects, the effect of the semiconductor memory device of the first aspect can be realized by the configuration of the minimum-scale register circuit, so that the layout area can be reduced. Is possible.

According to the semiconductor memory device of the eighth aspect, the effect of the semiconductor memory device of the first aspect can be enjoyed even when each input / output circuit operates based on a common clock signal.

The semiconductor memory device according to the ninth and tenth aspects,
The effect of the semiconductor memory device according to claim 1 can be enjoyed even when each input / output circuit operates based on an independent clock signal.

According to the semiconductor memory device of the present invention, the data read operation and the data read operation can be performed even when the read operation and the write operation for the same memory cell are instructed at the same timing. Since the writing operation can be performed normally, the frequency of the clock signal can be increased.
The operation can be speeded up.

The semiconductor memory device according to the twelfth and thirteenth aspects has the effect of the semiconductor memory device according to the eleventh aspect,
Since this can be realized by the configuration of the minimum-scale register circuit, the layout area can be reduced.

[Brief description of the drawings]

FIG. 1 shows a semiconductor memory device 10 according to a first embodiment of the present invention.
FIG. 2 is a schematic block diagram showing the overall configuration of the ０0 ’.

FIG. 2 shows a memory cell array 110 and an input / output circuit 1
It is a block diagram for showing composition of 20a and 120b.

FIG. 3 is a circuit diagram showing a specific configuration of a simultaneous access detection circuit 150.

FIG. 4 is a circuit diagram showing a specific configuration of a register address match comparison circuit 168.

FIG. 5 is a block diagram showing a configuration of a main control circuit 170.

FIG. 6 is a circuit diagram showing a specific configuration of a register control circuit 172.

FIG. 7 is a circuit diagram showing a specific configuration of a flag switching circuit 174.

FIG. 8 is a circuit diagram showing a specific configuration of an input / output data switching control circuit 176.

FIG. 9 is a circuit diagram showing a specific configuration of a clock control circuit 178.

FIG. 10 is a circuit diagram showing a specific configuration of a write control circuit 179.

FIG. 11 is a circuit diagram showing a specific configuration of a control flag generation circuit 169.

FIG. 12 is a circuit diagram showing a specific configuration of a data selection circuit 166.

FIG. 13 is a circuit diagram showing a specific configuration of an address register 142 and a data register 144.

FIG. 14 is a circuit diagram showing a specific configuration of an input selection circuit 162.

FIG. 15 is a circuit diagram showing a specific configuration of an output selection circuit 164.

FIG. 16 is a flowchart for explaining the overall operation of the semiconductor memory device 100;

FIG. 17 is a timing chart showing an example of the operation of the semiconductor memory device 100.

FIG. 18 is a schematic block diagram showing an overall configuration of a semiconductor memory device 200 according to a second embodiment.

FIG. 19 is a circuit diagram showing a specific configuration of a simultaneous access detection circuit 250.

20 is an operation waveform diagram for explaining an operation of the simultaneous access detection circuit 250. FIG.

FIG. 21 is a circuit diagram showing a specific configuration of a clock control circuit 278.

FIG. 22 is a circuit diagram showing a specific configuration of a control flag generation circuit 269.

FIG. 23 is a schematic block diagram showing an overall configuration of a semiconductor memory device 300 according to a third embodiment.

FIG. 24 is a circuit diagram showing a specific configuration of access switching circuit 310.

FIG. 25 is a schematic block diagram showing an overall configuration of a semiconductor memory device 500 according to the conventional technique 1.

FIG. 26 is a schematic block diagram showing the overall configuration of a semiconductor memory device 600 according to the conventional technique 2.

FIG. 27 is a timing chart for explaining the operation of the semiconductor memory device 600.

[Explanation of symbols]

110 memory cell array, 120a, 120b input / output circuit, 130, 230 access control circuit, 140
Register circuit, 150, 250 simultaneous access detection circuit, 162 input selection circuit, 164 output selection circuit,
66 data selection circuit, 170, 270 main control circuit,
168 register address match comparison circuit, 169 control flag generation circuit, 172 register control circuit, 174
Flag switching circuit, 176 data switching control circuit, 17
8,278 Clock control circuit, 310 Access switching circuit.

Claims (16)

[Claims] 1. A semiconductor memory device for independently reading and writing data signals by a first plurality of access systems, comprising a memory cell array having a plurality of memory cells arranged in a matrix. The memory cell array includes: the first plurality of word lines provided independently for each row of the memory cells; and the first plurality provided independently for each column of the memory cells. A plurality of bit lines, the first plurality of input / output ports for transmitting and receiving each of the set of the first plurality of address signals, the data signals, and the command signals; Input / output for performing a read operation or a write operation of the data signal with respect to the memory cell corresponding to the address signal in response to the command signal And a register circuit that fetches and temporarily stores the address signal and the data signal according to a register control signal, and instructs a read operation and a write operation to the same memory cell at the same timing in an overlapping manner. If it is detected that the address signal currently stored in the register circuit matches the address of the same memory cell, and the data signal currently stored in the register circuit, A semiconductor memory device further comprising: an access control circuit for activating the register control signal to temporarily save the data signal corresponding to the write operation according to whether or not writing to the memory cell array is completed. . 2. The address signal includes an n-bit digital signal, the data signal includes an m-bit digital signal, and the first plurality includes k (k: a natural number of 2 or more and 2. The register circuit according to claim 1, wherein the register circuit includes a storage element capable of storing a digital signal of (n + m). (K / 2) bits.
13. The semiconductor memory device according to claim 1. 3. The address signal includes an n-bit digital signal, the data signal includes an m-bit digital signal, and the first plurality includes k (k: a natural number of 2 or more) 2. The semiconductor memory device according to claim 1, wherein the register circuit includes a storage element capable of storing a digital signal of (n + m) · (k−1) / 2 bits. 3. 4. The access control circuit is provided for each combination of two input / output ports of the first plurality of input / output ports, and the same access control circuit is used by the two input / output ports at the same timing. A simultaneous access detection circuit that generates a simultaneous access detection signal that is activated when a read operation and a write operation are instructed in an overlapping manner with respect to a memory cell; A register address match determination circuit that generates a register address match signal activated when a certain register storage address matches the address signal input to the input / output port; Register data stored as a data signal has already been written to the memory cell corresponding to the register storage address. And a control flag generation circuit for generating a control flag signal that is deactivated when the access flag is present, wherein the access control circuit matches the control flag signal with the register address when the simultaneous access detection signal is activated. Activating the register control signal when one of the signals is inactive,
The semiconductor memory device according to claim 1. 5. The access control circuit, when the register address match signal is activated, responds to the register storage data and the address signal according to the simultaneous access detection signal and the control flag signal. An output data selection circuit for transmitting one of the stored data of the memory cell to the input / output port to which the read operation is instructed; and the simultaneous access when the control flag signal is activated. In response to the detection signal and the register address match signal, one of the register stored data and the data signal corresponding to the write operation is changed to a signal before the input / output port corresponding to the write operation is specified. 5. The semiconductor memory device according to claim 4, further comprising: an input data selection circuit for transmitting the input data to the entry output circuit. 6. The access control circuit, when the simultaneous access detection signal is activated, when the control flag signal is activated and the register address match signal is inactivated, 6. The semiconductor memory device according to claim 5, wherein writing of said register storage data to said memory cell corresponding to a storage address is instructed to said input / output circuit corresponding to said input / output port to which said write operation is instructed. 7. The access control circuit, when the simultaneous access detection signal is inactivated and the control flag signal is activated and the register address match signal is activated, 6. The semiconductor according to claim 5, wherein said input / output circuit corresponding to said input / output port to which a read operation is instructed instructs writing of said register storage data to said memory cell corresponding to said register storage address. Storage device. 8. The input / output circuit operates based on a common clock signal, and the simultaneous access detection circuit inputs signals to each of the two input / output ports at each activation timing of the clock signal. 5. The semiconductor memory device according to claim 4, wherein the simultaneous access detection signal is activated in accordance with the coincidence between the address signals and the mismatch between the command signals. 9. Each of the input / output circuits operates by an independent clock signal transmitted to the corresponding input / output port, and the simultaneous access detection circuit is transmitted to each of the two input / output ports. A clock pulse generating circuit that is provided for the clock signal and generates a clock pulse signal activated for a predetermined period from the rising timing of the clock signal; An address match determination circuit that determines a match between the address signals, wherein the simultaneous access detection circuit is configured to correspond to each of the two input / output ports during a period in which each of the clock pulse signals is activated. The simultaneous access detection is performed according to a state of a command signal and a determination result of the address match determination circuit. Activates No. The semiconductor memory device according to claim 4, wherein. 10. The method according to claim 1, wherein the predetermined period is set to be longer than a required time of a read operation of the data signal in the memory cell array, and wherein the simultaneous access detection circuit is during a period in which a clock pulse signal is activated. A read operation is instructed to the input / output port corresponding to the clock pulse signal,
When a write operation is instructed to the other input / output port, the simultaneous access detection signal is output when the address signals input to the two input / output ports match. 10. The semiconductor memory device according to claim 9, wherein: 11. A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells arranged in a matrix, wherein the memory cell array is provided independently for each row of the memory cells. A plurality of word lines; and a second plurality of bit lines provided independently of each other for each column of the memory cells, for receiving and transmitting clock signals, address signals, data signals, and command signals. An output port, and for the memory cell corresponding to the address signal,
A second plurality of input / output circuits capable of independently performing a read operation or a write operation of the data signal in response to the command signal; An access switching circuit that distributes and supplies the input / output circuits to the input / output circuits, wherein the access switching circuit has activation timings independent of each other by dividing the frequency of the clock signal, and An internal clock generating circuit that generates an internal clock signal corresponding to each of the plurality of input / output circuits; and the input / output corresponding to the address signal, the data signal, and the command signal in synchronization with the internal clock signal. A flip-flop circuit for transmitting the address signal and the data signal in response to a register control signal. And a register circuit for temporarily storing the address currently stored in the register circuit when detecting that a read operation and a write operation for the same memory cell are instructed at the same timing. In response to the presence or absence of a match between a signal and an address of the same memory cell and the completion of writing of the data signal currently stored in the register circuit to the memory cell array, the write operation is performed. An access control circuit for activating the register control signal to temporarily save the data signal. 12. The address signal includes an n-bit digital signal, the data signal includes an m-bit digital signal, and the second plurality includes k (k: a natural number of 2 or more) 2. The register circuit according to claim 1, wherein the register circuit includes a storage circuit capable of storing (n + m) · (k / 2) -bit digital signals.
2. The semiconductor memory device according to 1. 13. The address signal includes an n-bit digital signal, the data signal includes an m-bit digital signal, and the first plurality includes k (k: a natural number of 2 or more and 12. The semiconductor memory device according to claim 11, wherein the register circuit has a storage element capable of storing a digital signal of (n + m). (K-1) / 2 bits. 14. The access control circuit is provided for each combination of two input / output circuits of the second plurality of input / output circuits, and the same access control circuit is provided by the two input / output circuits at the same timing. A simultaneous access detection circuit that generates a simultaneous access detection signal that is activated when a read operation and a write operation are instructed in an overlapping manner with respect to a memory cell; A register address match determination circuit that generates a register address match signal that is activated when a certain register storage address matches the address signal input to the input / output port; Register data, which is a data signal, has already been written to the memory cell corresponding to the register storage address. And a control flag generation circuit for generating a control flag signal that is deactivated when the simultaneous access detection signal is activated, the control flag signal and the register address coincidence signal when the simultaneous access detection signal is activated. Activating the register control signal when any one of them is inactivated,
The semiconductor memory device according to claim 11. 15. A read operation and a write operation which are provided for each combination of two input / output circuits of the second plurality of input / output circuits at the same timing with respect to the same memory cell. A simultaneous access detection circuit that generates a simultaneous access detection signal that is activated when instructed. The simultaneous access detection circuit is provided for each of the internal clock signals. A clock pulse generation circuit that generates a clock pulse signal activated for a predetermined period from a rising timing; and an address match determination circuit that determines a match between the address signals corresponding to each of the two corresponding input / output circuits. The simultaneous access detection circuit is configured to control the two input / outputs at the activation timing of each of the clock pulse signals. According to the determination result of the address match determining circuit state of said command signal corresponding to each of the road, activate the simultaneous access detection signal, the semiconductor memory device according to claim 11, wherein. 16. The simultaneous access detection circuit according to claim 16, wherein the predetermined time is set to be longer than a required time of a read operation of the data signal in the memory cell array, and wherein the simultaneous access detection circuit is in a period during which the clock pulse signal is activated. When the read operation is instructed to the corresponding input / output circuit and the write operation is instructed to the other input / output circuit,
16. The semiconductor memory device according to claim 15, wherein said simultaneous access detection signal is activated when said address signals corresponding to said input / output circuits match.