JP5028710B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a one-chip multiport semiconductor memory device (hereinafter referred to as a memory), and more particularly to a multiport memory using a DRAM memory array.
[0002]
[Prior art]
There are several types of multi-port memory, but here we have multiple ports that can access a common memory array independently from each port. For example, a 2-port multi-port memory has an A port and a B port, and can be independently read from and written to a common memory array from a CPU-A connected to the A port and a CPU-B connected to the B port.
[0003]
As such a multi-port memory, an SRAM is used as a memory array, word lines and bit line pairs are provided in duplicate, and each memory cell is connected to two word line and bit line pairs. It has been. However, this multi-port memory has a problem that it is necessary to provide double word line and bit line pairs, and the degree of integration is low.
[0004]
Therefore, it is conceivable to use a mechanism similar to that of a shared memory used in a multiprocessor computer or the like. A shared memory is provided with a plurality of ports with respect to a common memory. In general, an SRAM is used as a memory, and a plurality of ports are configured using a discrete IC. In the shared memory, when access is simultaneously made from a plurality of ports, the memory array is common, so that there is a problem that the operation processing from the plurality of ports cannot be executed simultaneously. The simplest measure to prevent such a problem is to output a busy signal to the other port so that it is not accessed when access is being made from one port. This has the problem that the usage is limited. Therefore, in the shared memory, an arbitration circuit called an arbiter is provided to determine the priority order of access requests received from a plurality of ports, and the memory array control circuit sequentially executes them according to the order. For example, it is preferentially performed in order from the input to each port in the early order. For example, it is preferentially performed in order from the input to each port in the early order. However, it is the same that a new command cannot be processed while a command of another port is processed. In such a case, it is necessary to issue a busy signal. There is a problem that a processing mechanism must be provided.
[0005]
Since the memory array is randomly accessed from a plurality of ports, a column access operation for continuously accessing consecutive column addresses to the same row address generally performed in a DRAM is not performed. That is, a cell is selected for one access, read or write is performed, and reset is performed.
For this reason, when composing a shared memory, an SRAM is generally used as a memory array. This is because the SRAM is easy to use because the random access is fast and refresh is unnecessary. A 1-chip multi-port memory has a configuration in which the word line and bit line pairs are provided in duplicate, and a 1-chip multi-port memory using a memory array similar to a normal SRAM is practical. It was not converted.
[0006]
[Problems to be solved by the invention]
In any case, the conventional multi-port memory and shared memory use SRAM, but do not use DRAM that requires refreshing.
As the performance of the system increases, the amount of data handled increases, and the multi-port memory is also required to have a large capacity. For this reason, it has been proposed to adopt a DRAM array having a higher degree of integration than a SRAM for a multiport memory, and to realize a multiport memory having a large storage capacity at a low cost. However, the problem here is refresh of the memory cells.
[0007]
In a normal DRAM, it is necessary to periodically give a refresh command from the outside between write / read commands. For this reason, a controller device of a system on which the DRAM is mounted includes a timer and a control circuit for refresh management. However, such a circuit is not provided in a system equipped with a conventional multiport memory using an SRAM. Even when the memory array is composed of DRAM, it is required that such a system can be used in the same manner as a conventional multi-port memory. That is, in the multi-port memory in which the memory array is configured by DRAM, it is necessary to take some measures for the refresh by the memory device itself.
[0008]
In addition, as described above, when the arbiter outputs a busy signal, there is a problem that the usability is not good.
It is an object of the present invention to realize a large-capacity and easy-to-use multi-port memory at low cost, which can be used without considering refresh even if the memory array is constituted by a DRAM core.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, in the multi-port semiconductor memory device of the present invention, the minimum input cycle time of the first command input from each set of external ports is m (m ≧ 2) times the minimum input cycle time. The semiconductor memory device can perform at least n internal operations during a period of
It is set to satisfy the condition of m × N <n <m × (N + 1).
[0010]
In other words, the condition is that the minimum external command cycle of each of the N ports is [time in which N internal operation cycles are possible + time α shorter than one internal operation cycle], for example, N In the case of = 2, the minimum external command cycle of each port is [time in which two internal operation cycles are possible + α]. Here, α is “α <one internal operation cycle”.
[0011]
In the present invention, when the arbiter outputs a busy signal, the problem that it is not easy to use is dealt with by “time in which two internal operation cycles are possible”, and the refresh problem is dealt with by “+ α”.
FIG. 1 is a diagram for explaining the principle of the present invention, and shows a case where a read operation is performed with two ports.
[0012]
A command input to the two external ports of the A port and the B port is input with a time in which 2.2 internal operation cycles are possible as a minimum cycle. That is, internal operation cycle × 2.2 times = minimum external command cycle, and the external command cycle is set to be longer than the time that 2.2 internal operation cycles are possible. Clocks CLKA and CLKB are input to the A port and the B port, respectively, and input / output of commands, addresses, and data between the external and external ports is performed in synchronization with the respective clocks. Although not shown, the address is input simultaneously with the command. As shown in the figure, when a read command is input from the A port and the B port in the minimum external command cycle, the arbitration circuit controls to perform the core operation with priority given to the input first.
[0013]
The DRAM core performs two read operations from the memory array during the external command cycle, and outputs the read data to the A port and the B port. Each of the A port and the B port holds read data, and outputs the read data in synchronization with the sixth clock from the input of the read command. That is, the data latency in this case is 6.
[0014]
A refresh timer is built in and a refresh command is automatically generated inside. When no refresh occurs, the inside of the device operates in a normal operation, and two processes of command-A and command-B are executed inside during the external command cycle. At this time, since the internal operation can be performed 2.2 times during the external command cycle as described above, the DRAM core performs the internal operation twice and has a further margin (tα).
[0015]
When a refresh command is generated internally, the device operates at high speed. The high-speed operation is to operate without a surplus time (tα). When a refresh command occurs, the device performs a refresh. In the meantime, since commands are input from the A port and the B port, commands to be processed are accumulated. The device sequentially executes commands at high speed without tα. In the meantime, commands are input from the A port and the B port, but the refresh command is generated with a period sufficiently longer than the external command cycle. Therefore, the command to be processed until the next refresh command is generated is the command − Since there are two commands, A and command-B, and the speed of processing the command internally is faster, there will be no accumulated command in the end. In other words, the internal operation catches up with the external command input. Then, the inside of the device returns to normal operation again. The margin time α is appropriately determined in consideration of the number of external ports, the internal operation cycle, the refresh interval, and the like.
[0016]
Further, the delay time (data latency) of the data output with respect to the Read command (RD) is worst when the command of the other port and the internal refresh command are generated immediately before, so about three cycles of the internal operation cycle ( 2 port) is required. However, since the external command cycle can operate with more than two internal operation cycles, the data transfer rate is high.
[0017]
As described above, according to the present invention, the external command cycle can be set to a high speed of slightly more than two internal operation cycles (in the case of two ports) while completely hiding the refresh from the outside. Further, it is not necessary to perform refresh control from the outside, and even if refresh is performed internally, it is completely hidden from the outside and does not affect the operation of the device as seen from the outside. Therefore, it is possible to access the memory from each external port without being aware of other ports.
[0018]
That is, according to the present invention, DRAM memory cells are used. However, as in the case of using SRAM, it is not necessary to be aware of refresh from the outside, and a multiport memory having a large capacity and a high data transfer rate can be realized. it can.
In the example of FIG. 1, for one read command, the output of read data is performed once in synchronization with the external clock. That is, the burst length is 1. Therefore, when the output of read data ends in one clock cycle, the external port does not output data for the remainder of the external command cycle (in this case, for 3 clock cycles), and the data transfer efficiency is improved. There is a problem of being bad. This problem can be solved by increasing the burst length.
[0019]
FIG. 2 is a diagram for explaining the principle of the present invention, and is an example when the burst length is 4. FIG. Also in this example, the external command cycles of the two external ports are set to a time that allows 2.2 internal operation cycles. Further, one external command cycle is four clock cycles, and data is output from the external port four times in synchronization with the clock at the data latency 6 during one external command cycle. Therefore, if the burst length is set according to the number of clocks in one external command cycle, gapless reading can be performed at two ports, and the data transfer rate can be greatly increased. In this case, it is necessary that data corresponding to the burst length can be input / output in one operation with respect to the memory array. For example, if the external port has four data input / output terminals and the burst length is 4, 16-bit data can be input / output to / from the memory array in one operation.
[0020]
Note that the A port and the B port do not need to operate in synchronization, and each external command cycle has a minimum cycle of [time in which N internal operation cycles are possible + time α shorter than one internal operation cycle]. If the conditions to be satisfied are satisfied, they can be arbitrarily set independently.
3 and 4 are diagrams showing the relationship between the minimum external command cycle and the internal operation cycle when the number of ports is 2, 3 and N. FIG. As shown in the figure, when the number of ports is 2, the minimum external command cycle is [time in which two internal operations are possible + α], and when the number of ports is 3, the minimum external command cycle is [3 If the number of ports is N, the minimum external command cycle is [N + 1 time when internal operation is possible + α].
[0021]
DETAILED DESCRIPTION OF THE INVENTION
5 and 6 are diagrams showing the configuration of the multi-port memory according to the embodiment of the present invention. FIG. 5 shows the DRAM core and its peripheral portion, FIG. 6A shows the A port, and FIG. 6B shows a B port, FIG. 6C shows a refresh circuit, and the parts (A) to (C) of FIG. 6 are connected to the part of FIG.
[0022]
As shown in the figure, the multi-port memory according to the embodiment temporarily stores the DRAM core 11, an arbiter 26 that controls processing to be executed in accordance with the order, and a command transferred from the arbiter 26. A command register 25 that holds and transfers the data to the control circuit 14 of the DRAM core 11 in that order, a register group that temporarily holds commands, addresses, and data of each port, and two ports, an A port 30 and a B port 40 An external port and a refresh circuit 50 are provided.
[0023]
The A port 30 and the B port 40 have mode registers 31, 41, CLK buffers 32, 42, data input / output circuits 33, 43, address input circuits 34, 44, and command input units 35, 45, respectively. In addition, each can operate at different clock frequencies supplied from the outside, and the data latency and burst length can be stored in the mode registers 31 and 41 and set separately. The data input / output circuits 33 and 43 have a mechanism for converting the input / output data from parallel to serial and serial to parallel in accordance with the burst length.
[0024]
The refresh circuit 50 includes a refresh timer 51 and a refresh command generator 52. The refresh timer 51 generates a refresh start signal at a predetermined cycle, and the refresh command generator 52 generates a refresh command accordingly.
Commands input from both the A and B ports are held in command registers A and B indicated by reference numbers 28A and 28B, addresses are held in address registers A and B indicated by reference numbers 19A and 19B, respectively, and write data is Write data registers A and B indicated by reference numbers 22A and 22B, respectively. The refresh command is also held in the refresh command register 27, and the refresh address is held in the refresh address counter / register 18.
[0025]
The arbiter 26 determines the execution order of the commands based on the arrival order of the commands, and transfers the commands to the command register 25 in order. When the commands transferred from the arbiter 26 are transferred to the control circuit 14 of the DRAM core 11 in that order, the command register 25 executes the commands in the DRAM core, and when the control circuit 14 is ready to receive the next command, Are transferred to the control circuit 14.
During this time, the command transferred from the arbiter 26 is temporarily held in the command register 25. The command register 25 transfers the command to the control circuit 14 of the DRAM core 11 and transmits a transfer signal to the corresponding address register and data register (in the case of writing). The DRAM core 11 performs an access operation to the memory array 12 by controlling the decoder 13, the write amplifier 15, and the sense buffer 16 according to the command received by the control circuit 14. In the case of the write operation, the decoder 13 decodes the write destination address, activates the word line and column signal line of the memory array 12, and writes the write data held in the write data registers A and B from the write amp 15 to the memory. Write to array 12. In the case of reading, the memory array 12 is similarly accessed, and the data read from the sense buffer 16 is sent to the data output circuit of each port via transfer gates A and B indicated by reference numbers 24A and 24B. The transfer timing of the transfer gate is determined by the operation cycle of the DRAM core 11 and is generated by the control circuit 14. Output data is output in synchronization with an external clock in the data output circuit of each port.
[0026]
Hereinafter, portions related to the processing of the command, address, and data will be described in detail.
7 and 8 are diagrams showing the configuration of the part related to the command of the first embodiment, and the same parts as those shown in FIGS. 5 and 6 are denoted by the same reference numerals. The same applies to other figures below.
[0027]
As shown in FIG. 7, the A port command input unit 35 includes an input buffer 36, a command decoder 37, and an (n-1) clock delay 38, and the B port command input unit 45 includes an input buffer. 46, a coder 47 by command, and an (m-1) clock delay 48. n and m are burst lengths. As shown in FIG. 8, the command register A has a Read command register AR and a Write command register AW, and the command register B has a Read command register BR and a Write command register BW.
[0028]
The input buffers 36 and 46 receive the input Read command in synchronization with the clocks CLKA1 and CLKB1, and the command decoders 37 and 47 decode the received command and generate RA1 and RB1 if they are read commands. If it is a write command, WA1 and WB1 are generated. RA1 and RB1 are transferred to the Read command registers AR and BR at the same timing, but WA1 and WB1 receive the final data of the burst data by (n-1) clock delay 38 and (m-1) clock delay 48. And then transferred to the Write command registers AW and BW. In addition, the refresh command REF 1 generated by the refresh circuit 50 is transferred to the refresh command register 27.
[0029]
The arbiter 26 detects the order in which the commands are transferred to the five command registers AR, AW, BR, BW, 27 and transfers the commands to the command register 25 in that order. When the command register 25 receives the command transmitted from the arbiter 26, the command register 25 transmits a command reception notification to the arbiter 26. When receiving the command reception notification, the arbiter 26 transmits the next command to the command register.
[0030]
The command register 25 transfers the commands transferred from the arbiter 25 to the control circuit 14 of the DRAM core 11 one by one in that order. The control circuit 14 of the DRAM core executes the received command and transmits a command acceptance signal to the command register 25 when the command is completed (or approaching completion). When the command register 25 receives the command receivable signal, the command register 25 transfers the next command to the control circuit 14. During this time, the command transferred from the arbiter 26 is temporarily held in the command register 25.
[0031]
FIG. 9 shows an embodiment of the arbiter 26. The order in which the commands arrived at the five registers (Read command register AR, Write command register AW, Read command register BR, Write command register BW, refresh command register 27) in FIG. judge. Each comparator 53 compares the timings of the two command registers, and the output on the side where “H” is input first becomes “H”. The AND gate 54 determines whether each command has been previously input to all the other four commands by determining whether the outputs of the related comparators 53 are all “H”. Signals RA31, WA31, RB31, WB31, and REF31 corresponding to each command indicate “H” in the case of the earliest command and are transferred to the command register 25. For example, if RA2 is the earliest among RA2 to REF2, the outputs of the comparators connected to RA2 are all “H” on the RA2 side, and as a result, RA31 is “H”. At this time, since the command reception notification has not yet occurred (= “L”), N1 = “H”, RA3 becomes “H”, and the command RA3 is sent to the command register 25.
[0032]
When the command register 25 receives the command, it generates a command reception notification. In response to this, an “L” pulse is generated at N1, and RA3 to REF3 all become “L”. In the meantime, any of ResetRA to ResetREF occurs. If RA31 is "H", ResetRA is generated and the Read command register AR is reset. Then, RA2 becomes “L”, and RA31 to REF31 become “H” in the next order command. Then, when the “L” pulse of N1 is cut off and N1 = “H”, the command in the next order is transferred to the command register 25. The above operation is repeated.
[0033]
FIGS. 10 and 11 are diagrams showing the configuration of the command register 25 of the embodiment, which are divided into two diagrams.
The command register 25 is mainly composed of a shift register 92 that stores commands and outputs them in order to the DRAM core 11 and switches (SW1 to SW3) 82 to 84 that transfer commands received from the arbiter 26 to the shift register 92. . In this example, the shift register 92 has a three-stage configuration, registers 85 to 87 that hold commands, flags 88 to 90 that indicate the holding states of the registers 85 to 87, and resets that reset the states of the registers 85 to 87. A data portion 91 is provided. When no commands are stored in the registers 85 to 87, the flags 88 to 90 (FL1 to FL3 = “L”) and the switch 82 (SW1) is connected. The first command is stored in the register 85 via SW1, and FL1 = "H". When FL1 = "H", a pulse is generated in the "H" edge pulsing circuit 93, and a command reception notification is transmitted to the arbiter 26.
[0034]
At this time, if a command acceptance signal is output from the DRAM core 11, the gate 97 is connected and the command of the register 85 is transferred to the latch 98 and is sent to the control circuit 14 of the DRAM core 11 as it is. At this time, an address corresponding to the command is transferred to the DRAM core 11. The DRAM core 11 starts the operation according to the received command and cuts off the command acceptance signal. Then, the gate 97 is cut off. The register control circuit 96 generates a shift signal, sends the contents of the register 86 to the register 85, and sends the contents of the register 87 to the register 86. If the command is not stored in the register 86 before the shift signal is generated, the shift is performed, so that the register 85 is reset and FL1 = "L". The register control circuit 96 generates a shift signal and at the same time generates a transfer prohibition signal, disconnects SW1 to SW3, and prohibits data from being transferred to the shift register 92 during the shift operation. When the first command (command 1) is stored in the register 85 via SW1, if the previous command is being executed in the DRAM core 11, the command is held in the register 85. FL1 = "H" and SW1 is disconnected, and SW2 is connected after a predetermined delay. The predetermined delay is a time corresponding to a time until a command reception notification is generated and the output of the arbiter is reset. If the next command (command 2) is transmitted from the arbiter 26 before the DRAM core 11 can accept the command, the command 2 is stored in the register 86 via SW2. FL2 = "H", a command reception notification is generated, SW2 is disconnected, and SW3 is connected after a predetermined delay time. Thereafter, when the DRAM core becomes ready to accept commands, a command acceptance signal is generated, the gate 97 is connected, the command 1 of the register 85 is transferred to the latch 98, and sent to the DRAM core 11. The DRAM core 11 starts the operation according to the command 1 and disconnects the command acceptance signal. Then, the gate 97 is cut off. The register control circuit 96 generates a shift signal, sends the command 2 of the register 86 to the register 85, and sends the contents (reset state) of the register 87 to the register 86. Command 2 is stored in the register 85, and the registers 86 and 87 are reset. Since FL1 = "H", FL2, FL3 = "L", SW2 is connected and SW1 and SW3 are disconnected.
[0035]
The reset data unit 91 is attached to the left of the register 87 of the shift register 92 in order to reset the register 87 by shifting the command of the register 87 to the register 86 with the subsequent shift signal when the command is stored up to the register 87. It is. As described above, the command register 25 temporarily accumulates the commands sent from the arbiter 26, detects the state of the DRAM core 11, and sequentially transfers the commands.
[0036]
A command generation detection signal is input to the register control circuit 96. The command generation detection signal is a signal generated when a command is transmitted from the arbiter 26. FIG. 12 shows the operation of the register control circuit 96. When the register control circuit 96 command acceptance signal is disconnected, a shift signal and a transfer prohibition signal are generated. If a command is transmitted from the arbiter 26 immediately before the command acceptance signal is disconnected, the command sent first It is better to shift after transferring to the shift register 92. Therefore, comparing which of the falling edge of the command acceptance signal and the rising edge of the command generation detection signal is faster, if the former is early, the shift signal and transfer prohibition signal are generated from the former falling edge, and the latter is If it is early, a shift signal and a transfer prohibition signal are generated from the latter falling edge.
[0037]
13 and 14 are operation diagrams of the command register 25. FIG. The case where Refresh occurs internally at the time of Write → Read switching where the input command is the densest (that is, the case of FIGS. 26 and 27) is described as an example. The numbers written in the operation diagrams of SW1 to SW3 are the numbers of the connected SWs and indicate the period during which the switch is connected. Registers 1 to 3 are registers with reference numbers 85 to 87, respectively.
[0038]
FIG. 15 is a diagram illustrating a configuration of a portion related to an address in the embodiment. In the following drawings, “P” at the end of a signal is a signal on a pulse generated by pulsing the rising edge of the original signal. As shown, the address input circuits 34 and 44 have input buffers 57A and 57B and transfer gates 58A and 58B. The address register 19A and the address register 19B include address latches A1 to A4 and B1 to B4, and transfer gates 59A to 63A and 59B to 63B. Addresses from the transfer gates 62A, 62B, 63A, 63B are transferred to the DRAM core 11 via the address bus 17. Further, the refresh address output from the refresh address counter / register 18 is also transferred to the DRAM core 11 via the transfer gate 64 and the address bus 17.
[0039]
When a Read command or a Write command is input from the outside, the address input to the input buffers 57A and 57B is transferred to the address latches A1 and B1 through the transfer gates 58A and 58B at the same time. If the command is a Read command, the command is transferred to the DRAM core 11 in synchronization with the command transfer via the transfer gates 61A, 63A, 61B, 63B and the address latches A4, B4. If the command is a Write command, it is further transferred to the address latches A2 and B2 at the final data fetch timing, and then transferred from the transfer gates 62A and 62B to the DRAM core 11 in synchronization with the command transfer. The refresh address is generated and held in the refresh address counter / register 18 and is similarly transferred from the transfer gate 64 to the DRAM core 11 in synchronization with the transfer of the refresh command to the DRAM core.
[0040]
FIG. 16 is a diagram showing a configuration of a portion related to data output in the embodiment, and FIG. 17 is a diagram showing a transfer signal generation circuit in the portion. The data input / output circuits 33 and 43 of the A port 30 and the B port 40 have data output circuits 65A and 65B and data input circuits 74A and 74B described later. As shown in the figure, the data read from the memory array 12 via the sense buffer 16 is transferred to the data output circuits 65A and 65B via the data bus 21 and the transfer gates 24A and 24B.
[0041]
Data output circuits 65A and 65B include data latches A1 and B1, transfer signal generation circuits 67A and 67B, transfer gates 68A and 68B, data latches A2 and B2, and parallel-serial (parasiri) converters 70A and 70A, respectively. 70B and output buffers 71A and 71B.
The transfer gates 24A and 24B are controlled based on the internal operation by the control circuit 14 of the DRAM core 11. If the executed command is Read-A (read operation from the A port), the transfer gate 24A is opened, Read-B If so, the transfer gate 24B opens. Data is held in the data latches A1 and B1, and is transferred to the data latches A2 and B2 after a predetermined latency from reception of the Read command at each port by the transfer gates 68A and 68B. , 71B and output.
[0042]
As shown in FIG. 17, the transfer signal generation circuit 67 delays the Read commands RA1 and RB1 by the number of clocks corresponding to the set latency by the flip-flops 72 connected in series to generate the data transfer signal 2. appear. Since transfer of read data from the transfer gates 68A and 68B is performed according to the data transfer signal 2, the read data is delayed from the read operation by the number of clocks corresponding to the latency.
[0043]
18 and 19 are diagrams showing a configuration of a portion related to data input in the embodiment. The data input circuits 74A and 74B have data input (Din) buffers 75A and 75B, serial-parallel converters 76A and 76B, and data transfer units 77A and 77B. Write data WDA and WDB from the data transfer units 77A and 77B are sent via the first wire data registers 78A and 78B, the data transfer gates 79A and 79B, the second wire data registers 80A and 80B, the data transfer gates 81A and 81B, and the data bus 21. Is sent to Write Amp. 15 and written to the memory array 12.
[0044]
The serially input data is serial-parallel converted according to the burst length, and transferred to the first write data registers 78A and 78B when the last data is input. When the Write command is transferred from the command register 25 to the DRAM core 11, the corresponding data is also transferred to the DRAM core 11.
20 to 28 are time charts showing the operation of the multiport memory of the first embodiment. FIG. 20 and FIG. 21, FIG. 23 and FIG. 24, and FIG. 26 and FIG. 27 are diagrams in which one time chart is divided for convenience of display, one showing the first half of the time chart and the other showing the second half. , Some are shown redundantly.
[0045]
FIG. 20 and FIG. 21 show operations when a Read operation command is continuously input to two ports. The A port and the B port receive clocks CLKA and CLKB having different frequencies, respectively, take in commands, addresses, and write data in synchronization with the input clocks, and output read data in synchronization with the clocks. . In this example, the A port operates at the highest clock frequency, the B port operates at a slower clock frequency, the A port operates with Read command cycle = 4 (CLKA), data latency = 6 (CLKA), burst length = 4. , B port has Read command cycle = 2 (CLKB), data latency = 3 (CLKB), and burst length = 2. The data latency and burst length are set in the mode registers 31 and 41 of the respective ports. Therefore, in the A port, the data input / output operation is performed four times in synchronism with the clock for one command, and the read data is output after six clocks from the input of the read command. In response to one command, the data input / output operation is performed twice in synchronization with the clock, and the read data is output three clocks after the input of the read command.
[0046]
The commands received by both the A and B ports are held in the command registers 28A and 28B, respectively. When the refresh timer 51 generates a signal, the refresh command is held in the refresh command register 27. The arbiter 26 monitors these command registers and transfers them to the command register 25 in order from the command that occurred earlier. The command register 25 temporarily holds the sent command and sequentially transfers the command to the DRAM core 11 in the order of sending according to the operation status of the DRAM core 11. That is, the next command is transferred after processing of the previously transferred command is completed.
[0047]
As shown in the figure, a command Read-A2 is input to the Read command register AR, a refresh occurs once before the command Read-B2 is input to the Read command register BR, and a refresh command is input to the refresh command register. Then, according to the generation order, the arbiter 26 transfers the data to the DRAM core 11 in the order of Read-A2->Ref-> Read-B2, and sequentially executes them in the core.
[0048]
There is an extra time between Read-B1 and Read-A2 in the core operation, and so far, it is a normal operation. When refresh occurs, Refresh is executed after Read-A2 without a margin time, and further, Read-B2, Read-A3,... Are executed continuously without a margin time, and there is no margin time until Read-A5. Is high-speed operation.
[0049]
Although the internal operation is delayed with respect to the command input from the outside due to the execution of the refresh command, it is recovered by the high-speed operation and caught up with Read-A5. There is a surplus time between Read-A5 and Read-B5, and the normal operation is restored. Data read from the DRAM core 11 in the sense buffer 16 is transferred to the data latch (data latch A1 or B1) of the port corresponding to the Read command by the transfer gate. The data is time-adjusted in the data latch A1 or B1, transferred to the data latch A2 or B2, and output in synchronization with the clock of each port.
[0050]
Even if refresh is performed internally, data is output after a predetermined data latency when viewed from the outside, and there is no need to be aware of refresh from the outside.
FIG. 22 shows an example in which the Write command is continuously input under the same conditions. Data input from the outside at the time of Write is also a burst input. At this time, the write command is held in the write command register AW at the timing when the last data is input. In this case as well, it can be seen that there is no need to be conscious from the outside even if a refresh occurs internally.
[0051]
FIGS. 23 and 24 are operation diagrams when both ports A and B perform a read operation at the maximum clock frequency, and FIG. 25 illustrates an operation diagram when both ports A and B perform a write operation at the maximum clock frequency. It is. In this case, there may be a phase difference between the clocks of both ports. In both ports, Read command cycle = 4, Write command cycle = 4, data latency = 6, and burst length = 4. As shown in the figure, it can be seen that the system operates without any problems even in such a case.
[0052]
FIG. 26 and FIG. 27 are time charts when both ports operate at the highest frequency, the Write command is switched to the Read command, and a refresh occurs inside, and in this case, the commands are most crowded.
As shown in the figure, the DRAM core 11 is implemented in the order of Ref → Write-A 1 → Write-B 1 → Read-A 2 → Read-B 2, and there is no gap between them. In this example, Read-A2 and Read-B2 are input 6 clocks after the write command is input, but even if this is advanced 2 clocks, the operation in the DRAM core cannot be advanced. In contrast, the read data output timing is determined by the data latency from the Read command input. Therefore, if the input timings of Read-A2 and Read-B2 are advanced, it is necessary to advance the data output timing accordingly. However, if, for example, Read-B2 is input after 4 clocks of Write-B1, Read-B2 comes in data output timing almost simultaneously with the start of operation in the DRAM core, and becomes inoperable. For the reasons described above, the command interval is increased with respect to the switching of Write → Read, for example, 6 clocks in this example.
[0053]
Regarding the command interval of Read → Write, since the Write data cannot be received from the DQ terminal unless the output of Read data is completed, the command interval is inevitably widened.
FIG. 28 is an operation diagram of the DRAM core 11, (A) shows the Read operation, and (B) shows the Write operation. In this way, word line selection → data amplification → write back → precharge is executed for one command to complete the operation. When the DRAM core 11 receives a command from the command register 25, the DRAM core 11 disconnects the command acceptance signal, and generates a command acceptance signal when the operation corresponding to the command is finished or is nearing the end.
[0054]
(Appendix 1) Memory array
N sets of external ports each receiving the first command (N is an integer of 2 or more);
A semiconductor memory device including an internal command generation circuit that independently generates a second command;
The minimum input cycle time of the first command input from the external port of each set is at least n times for the semiconductor memory device during m (m ≧ 2) times the minimum input cycle time. Internal operations can be performed,
A semiconductor memory device characterized by being set so as to satisfy a condition of m × N <n <m × (N + 1).
[0055]
(Supplementary note 2) The semiconductor memory according to supplementary note 1, wherein the n internal operations include an operation corresponding to m × N first commands and an operation corresponding to at least one second command. apparatus.
(Supplementary note 3) The semiconductor memory device according to supplementary note 2, wherein the memory array is composed of dynamic memory cells, and the second command is a refresh command.
[0056]
(Supplementary Note 4) a control circuit for controlling the memory array;
A command register for temporarily holding the first command and the second command before transferring them to the control circuit;
An arbitration circuit that determines the arrival order of the first command and the second command, and controls to transfer to the command register in that order;
The semiconductor memory device according to appendix 1, wherein the command register transfers the first command and the second command to the control circuit in the order of reception.
[0057]
(Supplementary Note 5) The semiconductor memory device according to Supplementary Note 4, wherein timing at which the command register transfers the first command and the second command to the control circuit is determined based on an operation cycle of the memory array.
(Appendix 6) The command register is composed of a shift register.
The semiconductor memory device according to appendix 5.
[0058]
(Supplementary note 7) The command register generates a capture completion signal when the command transferred from the arbitration circuit is fetched. When the arbitration circuit detects the fetch completion signal, the command register transfers a command of the next order. The semiconductor memory device described.
(Supplementary note 8) The semiconductor memory according to supplementary note 1, wherein each of the N sets of external ports includes a clock input circuit that receives a clock from outside, and performs an input / output operation of each external port in synchronization with the received clock. apparatus.
[0059]
(Supplementary Note 9) The semiconductor device according to Supplementary Note 8, wherein each of the N sets of external ports includes a mode register that stores data latency set from outside, and each external port outputs data at the set data latency. Storage device.
(Supplementary Note 10) Each of the N sets of external ports includes a burst type data input / output unit,
The mode register stores an externally set burst length,
The semiconductor memory device according to appendix 9, wherein each external port inputs / outputs data for the number of times corresponding to the set burst length during the input cycle of the first command.
[0060]
(Supplementary note 11) The semiconductor memory device according to supplementary note 4, wherein the multi-port semiconductor memory device is capable of inputting / outputting data for one burst length between the memory array and each external port in one operation.
(Supplementary Note 12) The first command includes a read command and a write command,
The arbitration circuit determines the order of the read command based on the first timing fetched by the external port, and the write command at the second timing when the last data that is burst input is input. The semiconductor memory device according to attachment 4, wherein the order is determined based on the order.
[0061]
【Effect of the invention】
As described above, according to the present invention, even if the memory array of a multi-port memory is constituted by a DRAM core, it can be used without being aware of refresh, and a large-capacity and easy-to-use multi-port memory can be realized at low cost. .
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 is a diagram illustrating the principle of the present invention when the burst length is 4. FIG.
FIG. 3 is an explanatory diagram of the principle of the present invention when the burst length is 4. FIG.
FIG. 4 is a diagram illustrating the principle of the present invention.
FIG. 5 is a diagram (part 1) illustrating a configuration of a multi-port memory according to an embodiment of the present invention;
6 is a diagram (part 2) illustrating the configuration of the multi-port memory according to the embodiment of the present invention.
FIG. 7 is a diagram (part 1) illustrating a configuration of a portion related to a command of the multi-port memory according to the embodiment.
FIG. 8 is a diagram (No. 2) illustrating a configuration of a portion related to a command of the multi-port memory according to the embodiment.
FIG. 9 is a diagram illustrating a configuration of an arbiter of the multi-port memory according to the embodiment.
FIG. 10 is a first diagram illustrating a configuration of a command register according to the embodiment.
FIG. 11 is a second diagram illustrating the configuration of the command register according to the embodiment.
FIG. 12 is a time chart showing the operation of the register control circuit used in the command register of the embodiment.
FIG. 13 is a time chart (part 1) illustrating the operation of the command register according to the embodiment.
FIG. 14 is a time chart (part 2) illustrating the operation of the command register according to the embodiment.
FIG. 15 is a diagram illustrating a configuration of a portion related to an address of the multi-port memory according to the embodiment.
FIG. 16 is a diagram illustrating a configuration of a portion related to data output of the multiport memory according to the embodiment.
FIG. 17 is a diagram illustrating a configuration of a transfer signal generation circuit according to an embodiment.
FIG. 18 is a diagram (No. 1) illustrating a configuration of a portion related to data input of the multi-port memory according to the embodiment.
FIG. 19 is a diagram (No. 2) illustrating a configuration of a portion related to data input of the multi-port memory according to the embodiment.
FIG. 20 is a time chart (part 1) illustrating the operation (continuous read) of the multi-port memory according to the embodiment.
FIG. 21 is a time chart (part 2) illustrating the operation (continuous read) of the multi-port memory according to the embodiment.
FIG. 22 is a time chart illustrating an operation (continuous write) of the multi-port memory according to the embodiment.
FIG. 23 is a time chart (part 1) showing the operation (fastest continuous read) of the multi-port memory according to the embodiment.
FIG. 24 is a time chart (part 2) illustrating the operation (fastest continuous read) of the multi-port memory according to the embodiment.
FIG. 25 is a time chart illustrating an operation (fastest continuous write) of the multi-port memory according to the embodiment.
FIG. 26 is a time chart (part 1) illustrating the operation of the multiport memory according to the embodiment (switching from Write to Read);
FIG. 27 is a time chart (part 2) illustrating the operation of the multiport memory according to the embodiment (switching from Write to Read);
FIG. 28 is a time chart illustrating a DRAM core operation of the multi-port memory according to the embodiment.
[Explanation of symbols]
11 ... DRAM core
12 ... Memory array
14 ... Control circuit
15 ... Write Amp.
16 ... Sense buffer
18 ... Refresh address counter / register
19A ... Address register A
19B: Address register B
22A ... Write data register A
22B: Write data register B
24A ... Transfer gate A
24B ... Transfer gate B
25 ... Command register
26 ... Arbiter
30, 40 ... (A, B) External port
31, 41 ... mode register
32, 42 ... CLK buffer
33, 43 ... Data input / output circuit
34, 44 ... Address input circuit
35, 45 ... Command input circuit
50 ... Refresh circuit

Claims (7)

A memory array,
N sets of external ports (N is an integer of 2 or more) for receiving external commands,
A semiconductor memory device comprising an internal command generation circuit for periodically generating a refresh command independently internally,
The minimum input cycle time of the external command input from each set of the external ports is m × N for the semiconductor memory device during a time that is m times the minimum input cycle time (m is an integer of 2 or more). The time corresponding to the external command and the time corresponding to the refresh command can be performed ,
A control circuit for controlling the memory array;
A command register for temporarily holding the external command and the refresh command before transferring them to the control circuit;
An arbitration circuit that determines the arrival order of the external command and the refresh command, and controls to transfer to the command register in the order of the arrival order;
The semiconductor memory device , wherein the command register transfers the external command and the refresh command to the control circuit in the order received . Timing at which the command register to transfer the external command and the refresh command to said control circuit, a semiconductor memory device according to claim 1 which is determined based on the operating cycle of the memory array. The semiconductor memory device according to claim 2 , wherein the command register includes a shift register. 3. The semiconductor according to claim 2 , wherein the command register generates a capture completion signal when the command transferred from the arbitration circuit is received, and the arbitration circuit transfers a command of the next order when detecting the capture completion signal. Storage device.   2. The semiconductor memory device according to claim 1, wherein each of the N sets of external ports includes a clock input circuit that receives a clock from the outside, and performs an input / output operation of each external port in synchronization with the received clock. 6. The semiconductor memory device according to claim 5 , wherein each of the N sets of external ports includes a mode register for storing data latency set from outside, and each external port outputs data at the set data latency. Each of the N sets of external ports includes a burst type data input / output unit,
The mode register stores an externally set burst length,
7. The semiconductor memory device according to claim 6 , wherein each external port inputs / outputs data for the number of times corresponding to the set burst length during the input cycle of the external command.

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