JP3223847B2 - Heat treatment method and manufacturing method for silicon single crystal wafer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heat treatment method and a production method for simultaneously and uniformly heat-treating a large number of silicon single crystal wafers. For example, about 10 wafers are stacked to form a group. By stacking a plurality of groups and stacking them at a slight inclination in the vertical direction, and performing a required heat treatment in the same furnace, DZ (Denuded Zone) is performed.
e) Oxygen outward diffusion heat treatment for layer formation, IG (Int
BMD (Bulk Micro D) with oxygen precipitates for imparting rinsic gettering ability
effect), heat treatment to control generation of surface COP (Cr
ystal Originated Particl
e) A large number of wafers to be processed simultaneously in any one of the heat treatments, such as a heat treatment for eliminating a grown-in defect serving as a COP source inside the substrate and improving the device characteristics, can be uniformly and effectively subjected to heat treatment. The present invention relates to a heat treatment method for a silicon single crystal wafer and a manufacturing method using the heat treatment method.

[0002]

2. Description of the Related Art Most silicon wafers used for semiconductor devices are pulled up (Czochralski method,
CZ method). A silicon single crystal grown by the CZ method usually contains oxygen impurities of about 10 ¹⁸ / cm ³ , and if used as it is in a device manufacturing process, supersaturated oxygen is precipitated during the process. .

In addition, dislocations, stacking faults, and the like are generated secondarily due to the strain caused by the volume expansion of the oxygen precipitate. These oxygen precipitates (BMD) and their secondary defects have a great effect on the characteristics of the semiconductor device. If there are defects on the wafer surface and the device active layer, they cause an increase in leak current and a failure in withstanding oxide film. cause.

Further, with the increase in integration and miniaturization of MOS LSI devices, Gr introduced at the time of pulling a CZ silicon single crystal which was not regarded as a problem up to 16M DRAM.
Since the own-in defect significantly degrades the oxide film breakdown voltage characteristic of the MOS capacitor, the appropriateness of the crystallinity in the vicinity of the surface of the silicon single crystal substrate greatly affects the reliability and yield of the device after 64M DRAM.

[0005] As a countermeasure, as a method of improving the oxide film breakdown voltage characteristic during single crystal growth by the CZ method, the crystal growth rate is reduced at a low speed of 0.8 mm / min or less. It has been proposed that the withstand voltage characteristics can be significantly improved (Japanese Patent Laid-Open No. 2-267195).

[0006] In addition, the Green-i in the silicon single crystal.
As a method of reducing the n-defect, it has been proposed that the crystal growth be performed at a cooling rate of 2.0 ° C./min or less in a temperature range from 1150 ° C. to 1000 ° C.
93).

As another method, a silicon single crystal pulled by the CZ method is subjected to a heat treatment at a temperature of 1150 ° C. or more and 1400 ° C. or less by directly heating a silicon ingot as disclosed in JP-A-5-319988 and JP-A-5-319998. It is disclosed that the grown-in defects introduced during the growth can be reduced or eliminated to improve the reliability of the gate oxide film.

[0008] As for the heat treatment of the wafer, Japanese Unexamined Patent Publication No.
JP-A-231365, JP-A-61-193456, JP-A-61-193458, and the like, wherein a silicon substrate is placed in a hydrogen atmosphere or a hydrogen-containing atmosphere at 950 ° C. to 1200 ° C. At a temperature of 5 minutes or more to form a DZ layer on the surface layer of the silicon wafer by promoting oxygen outward diffusion.

On the other hand, in the ULSI device process, there are heavy metal contaminations typified by Fe, Ni, and Cu due to a heat treatment process at a high temperature or the like, and these heavy metal contaminations cause defects or electric near the wafer surface. When the level is formed, the characteristics of the device are deteriorated. Therefore, it is necessary to remove the heavy metal contamination from the vicinity of the wafer surface.
A gettering technique of “trinsic gettering” has been conventionally used.

[0010] It is clear that in the future device process, further integration and high-temperature ion implantation will be performed at lower temperatures. In this case, the formation of BMD in the process will increase the process temperature. It is expected to be difficult. Therefore, it is more difficult to obtain a sufficient IG effect in the low-temperature process than in the high-temperature process. Further, even if the process temperature is lowered, heavy metal contamination due to high energy ion implantation or the like is unavoidable, and it is considered that gettering technology is essential.

[0011] To improve the quality of ordinary CZ-Si wafers , DZ-IG processing has been widely used so far, and as described above, this method performs high-temperature processing of wafers at a temperature of about 1100 ° C to 1200 ° C. By doing
Oxygen in the vicinity of the wafer surface is diffused outward to reduce interstitial oxygen serving as nuclei of minute defects, thereby forming a defect-free DZ (Denude Zone) layer in the device active region. After that, a low-temperature heat treatment at 600 to 900 ° C.
A two-stage high-temperature and low-temperature heat treatment of forming oxygen precipitation nuclei in the wafer Bulk is performed.

[0012]

However, as a method of improving the oxide film breakdown voltage characteristics during single crystal growth by the CZ method, a method of growing a crystal at a low speed of 0.8 mm / min or less is a method of increasing the pulling speed. Slowing will significantly reduce productivity. In addition, in this method, there is a problem that the crystal becomes rich in interstitial silicon atoms and a dislocation loop is generated due to excess interstitial silicon atoms. On the other hand, when pulling a silicon single crystal, 1150 to 100
A cooling rate of 2.0 ° C./mi in a temperature range up to 0 ° C.
It is impossible to completely eliminate the grown-in defect even if the method is set to n or less.

The method of directly heat-treating a silicon ingot at a temperature of 1150 ° C. or more and 1400 ° C. or less cannot be used as a product because dislocation and slip occur in the entire ingot. On the other hand, the method of heat-treating a silicon substrate at a temperature of 900 ° C. to 1200 ° C. in a hydrogen atmosphere or a hydrogen-containing atmosphere is true. If the wafer surface is mirror-polished again to remove particles adhering to the wafer surface in the process and surface flaws caused by transfer of the wafer, the effect is significantly reduced.

In a structure in which a hole of about 8 to 10 μm is dug below the wafer surface like a trench capacitor, gro
Since the wn-in defect has not disappeared, the growth-i
Leakage current occurs due to the presence of n defects, and improvement in device characteristics cannot be expected. Further, in the case of wafer heat treatment, a horizontal or vertical furnace is generally used, and the wafer to be subjected to the heat treatment is one boat by a boat made of SiC or quartz.
Since one wafer is mounted in one boat support groove, it is not easy to process a large amount of wafers at the same time.

As a countermeasure, there is a conventional method for heat-treating a large amount of silicon single crystal substrate wafers and its apparatus as disclosed in JP-A-57-97622 and JP-A-53-25351.
FIG. 18 shows an example disclosed in Japanese Unexamined Patent Application Publication No. H10-260, FIG.

In this method, a plurality of silicon single-crystal wafers 1 are stacked in the horizontal direction in a state of standing vertically, placed on a silicon boat 2, and holding plates 3 are placed on both sides of the stacked silicon single-crystal wafers 1. Is pressed and supported, and the silicon single crystal wafer 1 pressed and supported on the silicon boat 2 is heated in a heat treatment furnace 4. Since a plurality of silicon single crystal wafers 1 superposed in the lateral direction are uniformly pressed and held from both sides by the holding plate 3, the warpage is small and the diffusion depth is low in the high concentration deep impurity diffusion. Variations such as surface concentration can be reduced.

In general, when a slip dislocation occurs in a silicon wafer, a device made of this silicon substrate has an adverse effect such as an increase in leak current from the slip dislocation portion and cannot be put to practical use. In the heat treatment apparatus shown in FIG. 18, the silicon single crystal wafer 1 superposed laterally on the silicon boat 2 is placed, and the side end portion of the silicon single crystal wafer 1 is in contact with the silicon boat 2. In addition, dislocations and slips occur during the heat treatment at the respective contact sites of all the superposed silicon single crystal wafers 1 and are not applied to the current production.

As described above, there is no method for completely eliminating the grown-in defects grown at the time of CZ pulling.
As a countermeasure, the movement of performing silicon epitaxial growth on the surface of a CZ silicon substrate has become active. Although epitaxial growth film is an oxide film resistance pressure characteristics are very good,
SiHCl ₃ , SiH ₂ Cl ₂ ,
Further, HCl gas is used for wafer cleaning, and this chlorine atom promotes corrosion of pipes and the like, so that a problem of heavy metal contamination is likely to occur, and the production cost is high and disadvantageous portions are large.

Also, gr, which affects the oxide film breakdown voltage characteristics,
When the shape of the own-in defect exists inside the crystal, as shown in FIG. 17B, the inside is a polyhedron having a hollow octahedron as a basic structure and exposed to the surface after being processed into a wafer state In this case, as shown in FIG. 17A, the pit is a concave pit having a quadrangular pyramid shape, and has a diameter of 0.
1 to 0.2 μm, after cutting into wafers
Defect pits (COP (Crystal Originated) that appear on the surface after mirror polishing and wafer cleaning
Particle) has been reported to have affected the oxide film breakdown voltage characteristics. However, in any conventional heat treatment, the COP of the surface layer of the wafer and the C
It was not possible to reduce the grown-in defect which is a source of OP.

The present invention includes an oxygen outward diffusion heat treatment for forming a DZ layer, a heat treatment for controlling generation of a BMD for imparting IG capability, a surface COP and a grown surface inside a wafer.
In a variety of heat treatments applied to silicon single crystal wafers, such as heat treatments that eliminate device defects and improve device characteristics, increase the number of silicon single crystal wafers processed in a single heat treatment step, It is an object of the present invention to provide a heat treatment method for a silicon single crystal wafer that can suppress dislocations and slips in the wafer.

[0021]

SUMMARY OF THE INVENTION The inventor of the present invention has proposed that, for example, when heat-treating a silicon single crystal
About the same number of wafers are loaded at the same time, or a large number of wafers more than 100 are loaded at the same time to prevent dislocation and slip in a high-temperature heat treatment atmosphere for each wafer,
As a result of various investigations for the purpose of a heat treatment method capable of uniformly providing the same heat treatment effect, about 10 wafers were stacked and this group was taken as a unit, horizontally or 0.5 to 5
°, placed on a boat that is slightly inclined and does not contact and support the outer peripheral end surface of the wafer. For example, when heat treatment at 1100 ° C. or more is performed to promote oxygen outward diffusion, the wafer is placed on the boat. even dislocations or slip on the bottom wafer in contact Te occurs, adjacent main surfaces thereto
It has been found that propagation to the wafers to be laminated can be prevented, and that the DZ layer can be formed on any of the wafers at the same time.

Further, the inventor of the present invention has proposed a method in which a plurality of stacked wafers are grouped as a group, and a plurality of wafers are vertically arranged in multiple stages in a stack within a range of a soaking range of a heat treatment furnace to be loaded. It has been found that the same heat treatment effect can be exerted uniformly on each wafer by preventing the heat treatment, and heat treatment of a large number of wafers is possible.

That is, the same heat treatment can be simultaneously performed on three or more times the number of wafers by using the conventional heat treatment furnace, and the overall dislocations that occur in the conventional heat treatment process of so-called ingot annealing are obtained. It was found that high productivity and high yield could be achieved without expansion of slip and slip.

As a result of further studies, the inventor has found that: 1) a buffer plate (layer) on the back strut portion of the above-mentioned inclined boat and a material having excellent high-temperature strength on the lowermost layer of a plurality of wafers; For example, Si, SiC, ceramics,
By disposing a disk or ring of alumina or the like, dislocation or slip does not occur. 2) Heat treatment in oxygen alone or in an oxygen-containing atmosphere prevents adhesion between wafers. 3) Necessary. It has been found that in particular, when a wafer to be heat-treated is not subjected to a polishing treatment or is not subjected to a finish polishing treatment, adhesion between wafers is particularly prevented.

Furthermore, the inventor of the present invention performs a heat treatment at 1100 ° C. or more in the above-described heat treatment according to the present invention, for example, at 1100 ° C. to 1350 ° C.
It has been found that by performing the treatment for minutes to 6 hours, it is possible to form a defect-free region (DZ layer) on each of the surface layers of a large number of wafers.

The inventor of the present invention has studied for the purpose of optimizing the heat treatment conditions for forming the defect-free region (DZ layer). 1) 500 ° C. to 900 ° C. in the process of raising the temperature to 1100 ° C. or more.
When a heat treatment such as holding at a constant temperature for 10 minutes or more and 4 hours or more at a constant temperature within a range of 10 ° C. is performed, BMD is formed and IG is formed.
2) A heating rate of 0.5 ° C./900° C.
BMD can be formed by increasing the temperature at a rate of min to 5 ° C./min to provide IG capability. 3) In the temperature decreasing step after heating and holding at 1100 ° C. or more, 5
BMD when heat treatment such as holding at a constant temperature for 10 minutes to 16 hours or a plurality of constant temperatures in the range of 00 ° C to 900 ° C is performed.
4) that the IG ability can be provided by forming
The cooling rate in the range of 00 ° C to 900 ° C is 0.5 ° C / min.
When the temperature is lowered at ~ 5 ° C / min, BMD is formed and I
It has been found that G ability can be imparted.

Further, the inventor has found that in the above-mentioned heat treatment according to the present invention, 1250 ° C. or more, for example,
By heating at ウ ェ ー ハ 1380 ° C. for 5 minutes to 6 hours, a large amount of wafers can be processed at the same time, and the surface COP of each wafer and the grown-
In defects can be reduced or eliminated.
When performing a heat treatment at 250 ° C. or higher, a high-quality silicon single crystal wafer can be manufactured by using the heat treatment for forming the defect-free region (DZ layer) described above or the heat treatment for further imparting IG capability. We have found and completed this invention.

[0028]

FIG. 1 shows an example of a heat treatment apparatus used in a heat treatment method according to the present invention. This heat treatment apparatus is a cylindrical heat treatment furnace (not shown). In the figure, ten silicon single crystal wafers 1 are stacked to form a group, and a plurality of groups of silicon single crystal wafers 1 can be supported. A heat treatment boat 10 made of a material having excellent high-temperature strength such as porous SiC, Si impregnated SiC, etc., and each silicon single crystal wafer 1 supported by the heat treatment boat 10
For example, for the DZ-IG treatment, the group is heated at a rate of 1 ° C./min up to 1000 ° C., kept at 1280 ° C. for 2 hours, and then cooled at a rate of 1 ° C./min. 1150 ° C or higher for DZ treatment 13
Various heat treatments are performed, such as heat treatment within a temperature range of 80 ° C. or less for 5 minutes to 6 hours.

The heat-treated boat 10 has a disc-shaped lower plate 1
1 and the upper plate 12 and the three support plates 13, 14, and 15. The three support plates for forming a cylindrical space between the lower plate 11 and the upper plate 12 are approximately the diameter of a disk. A pair of front ends of the front support plate 1 are fixed between the lower plate 11 and the upper plate 12 at one end in a diametrical direction perpendicular to the pair of ends, respectively.
, 14 and a rear support plate 15 are arranged, and rear support holders 15a, 15b... Protruding at a plurality of positions of a predetermined height of the rear support plate 15 and front support plates 13, 14 are also provided. , 14a, 14b... Protruding at a position slightly higher than the rear support holder 15a, and the pair of front supports 13a, 13b,.
An opening 16 is formed between 14b..., And a group of stacked silicon single crystal wafers is inserted from the opening 16.

The rear support holders 15a, 15b,...
, 14a, 14b,..., 14a, 14b,.
The upper surface is formed as an inclined surface that coincides with the upper surface of the rear support holders 13a, 13b.

As described above, the front and rear support holders 1
On 3a, 14a, 15a, 13b, 14b, 15b,
Since one group of stacked silicon single crystal wafers is mounted, slip occurs only in the lowermost silicon single crystal wafer 1 of each group of wafers. 1 is that the wafers only touch each other and do not touch anything else,
This is a configuration that can realize slip-free.

As described above, the silicon single crystal wafers 1 stacked on each support holder can be directly mounted. However, a circular material made of a material having excellent high-temperature strength, for example, SiC, ceramics, etc., is placed on each support holder. A plate or ring is installed and a group of silicon single crystal wafers stacked thereon is mounted, or a silicon single crystal wafer is stacked on the disk or ring and this is grouped as a group on each support holder. A configuration for mounting can be adopted.

That is, a slip occurs due to the influence of the accuracy of a disk or a ring on which only the lowermost silicon single crystal wafer 1 of each group of wafers 1 is placed, and the silicon single crystal wafer 1 stacked thereon is a wafer. The configuration is such that slip-free can be realized only by mutual contact without any other contact. Here, it is preferable that the thickness of the disk or the ring to be placed below the group of silicon single crystal wafers is about 2 mm to 7 mm. The thickness 17 of the support holder of the heat treatment boat 10 is 4
It is preferably about mm to 6 mm.

The heat treatment apparatus used in the heat treatment method according to the present invention shown in FIGS. 3 and 4 is an example having a heat treatment boat 20 for horizontally mounting a group of stacked silicon single crystal wafers. Ring-shaped support holders 21, 22, 23 made of a cylindrical body and arranged at predetermined intervals on the inner peripheral surface
Are arranged in a circumferential direction, and on one side of the outer peripheral surface, an opening 24 for inserting a jig (not shown) on which a group of a required plurality of silicon single crystal wafers 1 is placed into a cylindrical body.
And a vertical insertion groove 25 are formed, and a group of wafers 1 is mounted on the ring-shaped support holders 21, 22, 23, respectively.

A group of wafers 1 is inserted and placed on the uppermost support holder 23 by using the upper opening of the boat 20 and the insertion groove 25. In the heat treatment boat 20 as well, a disk or ring made of a material having excellent high-temperature strength, for example, SiC, ceramics, or the like is placed on each support holder, and a group of silicon single crystal wafers stacked thereon is mounted. Alternatively, it is possible to adopt a configuration in which a silicon single crystal wafer is stacked on the disk or ring, and the silicon single crystal wafers are grouped and placed on each support holder.

The heat treatment boat 30 used in the heat treatment method according to the present invention shown in FIG. 5 includes a low-height cylindrical boat unit 31, and a ring-shaped support holder 32 is provided on the inner peripheral surface of the boat unit 31. A jig (not shown) on which one group of a plurality of required silicon single crystal wafers is mounted, and a boat is provided with a vertical insertion groove 33 formed on one side of the outer peripheral surface. The upper surface opening of the unit 31 and the insertion groove 33 are used so as to be insertable and mountable, and a plurality of boat units 31 storing and mounting the silicon single crystal wafers 1 are vertically stacked in a plurality of stages. Therefore, similarly to the heat treatment boat 20 of FIGS. 3 and 4, a group of a plurality of silicon single crystal wafers 1 can be stored and mounted, and heat treatment can be performed on a large number of wafers at the same time.

In the heat treatment boat 30 shown in FIG. 5, the support holder 32 may be formed of a disk, and a disk or a ring made of a material having excellent high-temperature strength, for example, SiC or ceramics may be formed on each support holder. A configuration in which one group of silicon single crystal wafers mounted and stacked thereon is mounted, or a plurality of silicon single crystal wafers are stacked on the disk or the ring and are mounted as a group on each support holder. Can be adopted.

Each of the above-mentioned heat treatment boats 10, 20, 30
In the support holder described in the above, a step portion having an inner diameter dimension such that it is in contact with the outer periphery of the wafer 1 can be formed on the mounting surface of the silicon single crystal wafer 1. The step allows easy positioning of the silicon single crystal wafer 1 placed on the support holder, and the outer peripheral portions of the second and subsequent silicon single crystal wafers 1 from the lowermost layer contact the heat treatment boat main body. Can be prevented.

According to the present invention, for example, while one wafer is set in one groove of a boat in the conventional heat treatment for forming a DZ layer, a large number of
By performing heat treatment at 0 ° C. or higher, it is possible to form out diffusion of interstitial oxygen in the vicinity of the surface between adjacent wafers, and to find out that the out diffusion distribution in the wafer surface is also good. is there.
Therefore, it is necessary to stack a number of wafers and transfer them as a group at once.

As shown in FIG. 6A, a conventional silicon wafer transfer method is a suction type transfer robot provided with a suction plate 41 on an arm 40, and as shown in FIG.
Any of the picking-up type wafer transfer robots provided with the mounting plate 42 at 0 is a single-wafer type, but the conventional single-wafer type wafer transfer robot stacks wafers on one groove of the heat treatment boat. This makes the device itself complicated and very expensive.

Therefore, as an apparatus for transferring a plurality of stacked wafers at one time, the configuration example shown in FIG. 7 is a heat treatment boat 10 shown in FIG. 1, that is, a pick-up type wafer transfer method for a three-point support boat. An arm 40 is provided on a jig 43 which is a robot and has small arc-shaped support walls provided at both ends of a curved strip-shaped bottom plate portion, and allows the wafer 1 to be horizontally stacked and stored between a pair of small arc-shaped support walls. , One small arc-shaped support wall supports the boat at the time of loading (illustrated with imaginary lines)
Is provided with a cutout portion 44 for clearing.
After stacking a plurality of wafers on the jig 43 (see FIG. 7A), the wafers can be transferred to a heat treatment boat as a wafer group in which a large number of wafers are stacked.

Next, as an apparatus for transferring a plurality of stacked wafers at one time, a configuration example shown in FIGS. 8A and 8B is a robot for transferring a wafer of a scooping type to a four-point support boat, and is a curved strip. A small arc-shaped support wall is provided at both ends of a bottom plate portion, and an arm 40 is provided on a jig 45 capable of horizontally stacking and storing the wafers 1 between a pair of small arc-shaped support walls. After laminating a plurality of wafers on the jig 43, the wafers can be transferred to a heat treatment boat as a group of many laminated wafers. Further, as shown in FIG. 8C, a configuration using a pair of small-diameter support columns and a jig 46 provided with a pair may be used instead of the pair of small arc-shaped support walls. Further, in order to simplify the transfer of the wafer, a silicon single crystal wafer can be stacked on the disk or the ring and can be transferred as a group by a scooping type wafer transfer robot. .

The heat treatment boat 50 used in the heat treatment method according to the present invention shown in FIG. 9 is the same as the heat treatment boat 1 shown in FIG.
0 shows a configuration having three front and rear support plates 13, 14, and 15 having the same configuration as that of FIG. 0. In the drawing, illustration of a plurality of stacked wafers is omitted, and only one silicon single crystal wafer 1 is shown. . When a wafer is transferred to the heat treatment boat 50 using a scoop-up type wafer transfer robot, the front and rear support holders 13a, 13a, 1
4a, 15a, 13b, 14b, 15b, 13c, 14
c, 15c... A group of many stacked wafers is placed on top of the wafer. For example, if a slide occurs on the support holder and comes into contact with the rear support plate 15, the contact portion is between the wafer end face and the boat during high-temperature heat treatment. Causes a local temperature difference, causing slip.

Therefore, as shown in FIG.
The rear support plate 15 of the inclined starting end side of the heat treatment boat 50 made of a material having excellent high-temperature strength such as iC, Si, or alumina.
By installing the buffer material 51 made of a strip, the wafer end surface comes into contact with the buffer material 51 even if the wafer slides, and the presence of the buffer material 51 changes heat conduction and heat transfer. The local temperature difference is reduced, and the occurrence of slip is suppressed.

In the present invention, a group of a large number of stacked wafers is placed on a heat treatment boat at an angle of 45 ° or less, preferably 0.
About 5-5 degrees is good. 0.5 ° or more during heat treatment,
Alternatively, it is possible to prevent the wafer from falling from the boat due to slippage between the wafers when transferring the wafer. Also, 45 °
When the inclination angle is larger, it is difficult to transfer the wafer.

In the present invention, the silicon single crystal wafer to be subjected to the heat treatment is an etched wafer,
In addition to wafers that have been subjected to various mirror polishing and finish mirror polishing, any unpolished wafers are targeted.
Unpolished wafers are advantageous because they can prevent adhesion between wafers. Further, in consideration of metal contamination and the like in the wafer heat treatment, it is preferable to perform general RCA cleaning, for example, pre-loading cleaning such as SC-1 + SC-2 cleaning on the wafer before the heat treatment.

It is preferable that the processing allowance for the wafer surface polishing after the heat treatment is small, and it is preferable that the processing allowance is about 0.1 μm to 20 μm. If the processing allowance is less than 0.1 μm,
It is difficult to improve the surface accuracy, and if the processing allowance exceeds 20 μm, the processing loss is large, and the productivity is reduced due to problems such as mirror polishing time. Therefore, the processing allowance is set to about 0.1 μm to 20 μm. More preferably, it is about 1 μm to 5 μm.

In the method of the present invention, since the wafers are stacked and heat-treated, for example, in a non-oxidizing gas atmosphere (Ar, H ₂ gas, etc.), the natural oxide film grown on the wafer surface is not heat-treated. Etching off (sublimation) is performed in the range of 950 ° C. to 1000 ° C., and it becomes easy to firmly adhere to an adjacent etched off wafer. Since the bonding between the wafers is strong, peeling after heat treatment becomes difficult. Therefore, in the present invention, the heat treatment atmosphere is an oxygen gas or diluted oxygen atmosphere, for example, O ₂ / Ar or O ₂ / N
The heat treatment in step ₂ is advantageous because the wafers can be easily separated from each other after the heat treatment and cracks do not occur.

Even under a hydrogen or argon gas atmosphere, by alternately stacking about 10 wafers on which a thermal oxide film has been formed in advance and wafers without thermal oxidation in advance, the wafers after the heat treatment can be combined. Separation is facilitated, and of course, a wafer in which an oxide film has been formed in the previous step or a wafer in which an oxide film has been formed in advance can be used for all the wafers to be laminated.

In the present invention, a defect-free region (DZ layer)
Is preferably 1100 ° C.
In the heating process up to the above, 10 in the range of 500 ° C to 900 ° C.
When the heat treatment is performed for not less than minutes and not more than 4 hours, IG ability can be provided by forming BMD. When the temperature is raised at a rate of 0.5 ° C./min to 5 ° C./min in a temperature range of 500 ° C. to 900 ° C., BMD can be formed to provide IG capability. Particularly preferred conditions are a heat treatment at about 600 to 800 ° C. for 30 minutes to 1 hour, or a temperature increase in the range of 600 to 800 ° C. at a rate of 2 to 3 ° C./min.

The above conditions are for the temperature rise. However, the inventors have found that the temperature is lowered to 50 ° C. after the temperature is kept at 1100 ° C. or more.
The IG capability can be provided by forming a BMD by maintaining the constant temperature for 10 minutes or more and 4 hours or less in the range of 0 ° C. to 900 ° C. Similarly, the cooling rate in the range of 500 ° C. to 900 ° C. is 0.5 ° C. It was confirmed that when the temperature was lowered at a rate of / min to 5 ° C / min, BMD could be formed and IG capability could be imparted. Particularly preferred conditions are 600 to 700 ° C. during the temperature decreasing process.
Is to maintain the temperature at 4-8 hours.

The heat treatment for lamination and stacking according to the present invention
1250 ° C. or higher, for example,
By performing the heat treatment for minutes to 6 hours, a large amount of wafers can be processed at the same time, and it is possible to reduce or eliminate the grown-in defects that are the origin of the COP in the surface layer of each wafer and the internal COP. For example, as is clear from the examples, the COP is greatly eliminated by the heat treatment at 1280 ° C. for 2 hours, and particularly, 1280 ° C. × 4 hours and 1300 ° C. ×
It was confirmed that the COP completely disappeared in the heat treatment at a high temperature of about 1300 ° C. as in the case of 2 hours.
Particularly preferable conditions are 1300 to 1350 ° C. for about 2 to 3 hours.

In the heat treatment for stacking and stacking according to the present invention, in the heat treatment for eliminating the COP in the surface layer of the wafer, various heat treatment conditions for forming the defect-free region (DZ layer) described above, or further, BMD
In addition to reducing and eliminating the COP on the surface layer of the wafer by using various heat treatment conditions for imparting the IG capability by forming a GaN layer at the time of raising or lowering the temperature to 1250 ° C. or higher, the DZ-IG capability is reduced. It is possible to easily mass-produce the high-quality silicon single crystal wafer provided. It was confirmed that the combination of the heat treatment conditions can be arbitrarily combined within the above-mentioned range.

[0054]

【Example】

Example 1 Diameter 200 mm, oxygen concentration 13 grown by CZ method
~ 15 × 10 ¹⁷ atoms / cm ³ [old AST
M], the silicon ingot is rounded, then sliced, and further mixed with a hydrofluoric acid / nitric acid mixed aqueous solution or K
For a silicon single crystal wafer whose surface has been etched with an OH aqueous solution, 10 silicon single crystal wafers are grouped as a group using the heat treatment boat shown in FIG.
By stacking the groups vertically in order, the number of mounted
It was set to 0 sheets.

The charging temperature of the heat treatment boat into the cylindrical heat treatment furnace is 700 ° C., and the temperature up to 1000 ° C. is 8 ° C./min.
The temperature was raised to 1300 ° C. at a rate of 1 ° C./min, and 1300
℃ 2 hours, then up to 1000 ℃ 1 ℃ / min, 7
The temperature was lowered to 00 ° C at a rate of 2.5 ° C / min, and the heat treatment boat was taken out of the heat treatment furnace. The atmosphere in the furnace is 20% O ₂ −
The atmosphere was 80% N ₂ .

The state of occurrence of slip and dislocation on the silicon single crystal wafer thus heat-treated was confirmed by X-ray tomography (XRT). This X
Of the 10 silicon single crystal wafers superimposed by RT, only the lowermost silicon single crystal wafer on each support holder was observed to generate slip from the support holder. No slip or dislocation was observed in the second and subsequent stacked silicon single crystal wafers from the lowermost layer. This situation was the same for each wafer group.

Next, the wafer was etched with an HF aqueous solution to etch the oxide film grown during the heat treatment.
Mirror polishing of about μm is performed, then a gate oxide film is formed (25 nm thick) in a dry oxygen gas atmosphere, a polycrystalline silicon film is deposited, phosphorus is doped into the polycrystalline silicon to form an electrode, and the electrode area is determined by lithography. An 8 mm ² MOS Cap device was fabricated. An evaluation test of oxide film breakdown voltage characteristics was performed on the silicon single crystal wafer on which this MOS Cap structure device was manufactured. The evaluation conditions were such that a chip having an electric field strength of 8 MV / cm or more was regarded as a good chip.

Further, the same sample (wafer) as described above was subjected to a heat treatment at 1150 ° C., 1250 ° C., 1300 ° C., and 1350 ° C. for 2 hours. For comparison, the surface of the silicon single crystal wafer 1 including the same sample (wafer) that has not been subjected to the heat treatment is mirror-finished,
A Cap structure device was manufactured.

FIG. 2 shows the evaluation results in the evaluation test. 60% non-defective sample, 11%
The sample subjected to the heat treatment at 50 ° C. had a good product rate of 70%, and the heat treatment at 1200 ° C. or more had a good product rate of 90% or more.

Example 2 As in Example 1, 10 silicon single crystal wafers having an outer diameter of 8 inches were stacked, placed on a heat treatment boat, and
1 ° C./min from 128 ° C. to 1280 ° C., 128
After holding at 0 ° C for 2 hours, the temperature decreasing rate up to 1000 ° C is 1 ° C /
Heat treatment for cooling in min. The silicon single crystal wafer has an initial oxygen concentration of 15 × 10 ¹⁷ atoms /
cc (old ASTM) was used.

After the heat treatment, the oxygen concentration in the depth direction from the surface layer of the wafer was measured by SIMS for the total number of one wafer group and the fourth and eighth wafers of the other wafer group. I was able to secure. The measurement results of the oxygen concentration of the fourth and eighth wafers from a certain wafer group are shown in FIGS. 11 and 12 which are graphs showing the relationship between the surface depth and the oxygen concentration.

The heat treatment according to the present invention, in which a plurality of wafers are stacked and placed on a heat treatment boat to stack a plurality of groups, is capable of uniformly generating oxygen out-diffusion on all simultaneously processed wafers. The progress of the oxygen outward diffusion depends on the heat treatment temperature and time.

Example 3 Oxygen concentration: 14 to 15.5 × 10 ¹⁷ atoms / cm
Ten ( ³ ) (old ASTM) boron-doped wafers having an outer diameter of 8 inches were stacked on each other, and subjected to the heat treatment shown in FIG. 13A in the same heat treatment furnace as in Example 1. In addition, heat treatment of the heat pattern shown in FIG. 13B was also performed.

The heat pattern shown in FIG.
Temperature to 50 ° C / min.
After holding for 1 minute, the temperature is raised to 1000 ° C. at a rate of 10 ° C./min, further raised to 1280 ° C. at a rate of 1 ° C./min, held at 1280 ° C. for 2 hours, and then lowered to 1000 ° C. at a rate of 1 ° C./min. min, and the cooling rate is 2.5 ° C /
This shows a heat treatment for lowering the temperature to 700 ° C. in min.

In the heat pattern shown in FIG. 13B, the temperature was raised from room temperature to 1000 ° C. at a rate of 10 ° C./min, and further raised to 1280 ° C. at a rate of 1 ° C./min.
After holding at 280 ° C for 2 hours, the temperature is lowered to 1000 ° C at a rate of 1 ° C.
/ Min, and further shows a heat treatment of decreasing the temperature to 700 ° C. at a rate of 2.5 ° C./min.

After the two types of heat treatment, both of them were 1000 ° C. × 1
An evaluation heat treatment for 6 hours was performed. Thereafter, the wafer was cleaved and subjected to selective etching. The etching allowance at this time was about 2 μm. Next, the density of oxygen precipitates on the cross section of the wafer was measured with an optical microscope.

As a result of observing the cross section of the wafer with an optical microscope, no oxygen precipitate was observed in the sample wafer subjected to the heat treatment shown in FIG. 13B, and the sample wafer subjected to the heat treatment shown in FIG. 13A had a DZ layer having a depth of 30 μm from the wafer surface. Was formed, and in the region deeper than that, oxygen precipitates grew to about 10 ⁵ to 10 ⁶ / cm ² . Also,
The wafer obtained by the heat pattern shown in FIG.
Since the G effect cannot be expected, an EG effect by depositing a Poly Si film may be subsequently applied.

Example 4 In the same manner as in Example 1, 10 pieces of silicon single crystal wafers having an outer diameter of 8 inches after etching were stacked, and a plurality of stages were placed on a heat treatment boat, and heat treatment was performed at 1280 ° C. × 1 hour. When applying, the atmosphere is an argon gas atmosphere, 100% dr
The test was performed under the respective atmosphere conditions of a yO ₂ atmosphere, a 100% N ₂ atmosphere and a 3% O ₂ / N ₂ atmosphere. In addition, a heat treatment was similarly performed under the above-described atmosphere conditions using a silicon single crystal wafer having been subjected to mirror polishing.

In the atmosphere of argon gas, the outer peripheral portion of the wafer was locally bonded, but in other atmospheres, the bonded wafer was not bonded at all.

Example 5 Oxygen concentration grown by CZ method 12.5 to 15 × 10
The silicon ingot of ¹⁷ atoms / cm ³ [old ASTM] is rounded and then sliced,
Further, the silicon single crystal wafer whose surface was etched with a mixed aqueous solution of hydrofluoric acid and nitric acid or an aqueous KOH solution and then cleaned with SC-1 and SC-2 was used as a target in FIG.
By using the heat treatment boat of No. 1, 30 silicon single crystal wafers were grouped as a group, and 30 groups were sequentially stacked in the vertical direction, so that the number of mounted wafers was 300.

The temperature at which the heat treatment boat was introduced into the cylindrical heat treatment furnace was 700 ° C., and the temperature up to 1000 ° C. was 8 ° C./min.
The temperature is raised to 1280 ° C at a rate of 1 ° C / min.
And then lowered to 1000 ° C. at 1 ° C./min, and further lowered to 700 ° C. at 2.5 ° C./min.
The heat treatment boat was taken out of the heat treatment furnace. The atmosphere in the furnace was a 5% O ₂ -95% Ar atmosphere.

The sample wafer subjected to the above heat treatment was subjected to a deposition heat treatment at 600 ° C. × 4 hours or 700 ° C. × 4 hours using a horizontal furnace, followed by an evaluation heat treatment at 1000 ° C. × 16 hours. Thereafter, the wafer was cleaved and subjected to selective etching. The etching allowance at this time is about 2 μm
Met. Next, the oxygen precipitate density (BMD density) of the wafer cross section was measured with an optical microscope.

In FIG. 14 and FIG. 15, the initial oxygen concentration 1
A wafer having a low oxygen concentration of 2.5 to 13 × 10 ¹⁷ atoms / cm ³ was used for Group A, and an initial oxygen concentration of 13.5 to 14 ×
10 ¹⁷ atoms / cm ³ B groups the oxygen concentration wafers in the initial oxygen concentration 14.5~15 × 10 ¹⁷ atom
s / cm ³ high oxygen concentration wafers were classified as Group C.
4 hours at 0 ° C, mark △, precipitation heat treatment at 700 ° C x 4
The time is indicated by a square. As shown in FIG. 15, all the sample wafers have a DZ layer of 30 μm or more, and as shown in FIG. 14, in the bulk, a combination of the initial oxygen concentration and the post heat treatment temperature of 1 × 10 ⁵ cm ² or more. BMD
It is possible to secure the density.

Further, it was found that, in the sample wafer having a low oxygen concentration, the precipitate density was higher in the heat treatment at 600 ° C. than in the heat treatment at 700 ° C. Therefore, although the temperature of the oxygen precipitation treatment depends on the initial oxygen concentration of the wafer,
It can be determined that it is applicable within the range of 0 ° C.

Example 6 Oxygen concentration grown by CZ method 12.5 to 15 × 10
The silicon ingot of ¹⁷ atoms / cm ³ [old ASTM] is rounded and then sliced,
Further, for the silicon single crystal wafer whose surface has been etched with a mixed solution of hydrofluoric acid and nitric acid, using the heat treatment boat shown in FIG. By stacking, the number of sheets mounted was set to 300 sheets.

The temperature at which the heat treatment boat was introduced into the cylindrical heat treatment furnace was 700 ° C.
The temperature is raised to 1280 ° C. at a rate of 1 ° C./min.
Hold at 0 ° C for 2 hours, then up to 1000 ° C at 1 ° C / min,
The temperature was lowered to 700 ° C. at a rate of 2.5 ° C./min, and the heat treatment boat was taken out of the heat treatment furnace. The atmosphere in the furnace is 5% O
Was ₂ -95% N ₂ atmosphere.

After the heat treatment, a polishing allowance of about 1
After performing mirror polishing of about 0 μm and repeating SC-1 cleaning of RCA cleaning, LPD (L
A laser point inspection machine (surf scan 6200 manufactured by Tencor) was used to measure the right point defect.
I went in. In addition, LPD A
FM observation was also performed. Cleaning and measurement were also performed on the wafers not subjected to the heat treatment according to the present invention.

FIG. 16 shows the result of LPD observation after repeating the SC-1 cleaning. The initial oxygen concentration was 12.5 × 10 ¹⁷
Low oxygen concentration wafers of atoms / cm ³ are marked with ○, initial oxygen concentration 13.5 × 10 ¹⁷ atoms / cm ³ medium oxygen concentration wafers are marked with Δ, initial oxygen concentration 14.5 × 10 ¹⁷ a
high oxygen concentration wafer of toms / cm ³ is marked with □,
In particular, wafers not subjected to the heat treatment according to the present invention are indicated by black circles, black triangles, and black squares, respectively.

A wafer not subjected to the heat treatment according to the present invention has about 300 pieces of L
PD was present, and a significant increase in the number of LPDs was confirmed by repeated SC-1 washing. However, the wafers subjected to the heat treatment according to the present invention confirmed a significant decrease in the number of LPDs, and found that the number of increase in the LPDs was small even after repeated SC-1 cleaning.

In order to elucidate the identity of this LPD, AFM
, The LPD of the wafer subjected to the heat treatment according to the present invention was particles and COP-free.

Example 7 In Example 6, the heat treatment was performed at 1280 ° C. for 2 hours.
By changing the conditions to 80 ° C. × 4 hours and 1300 ° C. × 2 hours, the same heat treatment was performed on the sample wafer, and the COP existence probability was examined in the same manner as in Example 6.
It was confirmed that the COP had completely disappeared in any of the heat treatments. Therefore, in the heat treatment for lamination and stacking according to the present invention, it was confirmed that by maintaining the temperature at 1280 ° C. for 2 hours or more, there was a significant COP reduction effect.

[0082]

According to the heat treatment method of the present invention, about 10 wafers are stacked and a group of these wafers is contacted at a plurality of locations on the outer periphery of the wafer horizontally or at a slight inclination of about 0.5 to 5 °. It is placed on a supporting boat and further heat-treated by stacking a plurality of groups in multiple stages, as shown in the examples, it is possible to apply various heat treatments applied to silicon single crystal wafers, and to reduce dislocations and slips Thus, the same heat treatment effect can be exerted uniformly on each wafer.

According to the present invention, a large number of wafers are stacked and heat-treated. By using the lowermost wafer of the stacked wafers as a dummy wafer, the occurrence of dislocations and slips can be completely prevented.
Heat treatment can be applied to those that have not been subjected to mirror finish polishing, or they can be performed in an atmosphere where a protective film is formed on the surface, and the manufacturing process can be devised so that mirror polishing is performed after the heat treatment. Never do.

In particular, the heat treatment method according to the present invention makes it possible to simultaneously perform the same heat treatment on all the wafers formed from the same silicon single crystal ingot, which may occur in a conventional so-called ingot annealing heat treatment step. It is possible to improve the yield of the silicon single crystal wafer without any significant dislocation or slip enlargement.

The heat treatment method according to the present invention comprises:
Heat treatment to keep the temperature above 00 ° C.
By performing a constant temperature holding in the range of ° C. to 900 ° C., or raising the temperature at a predetermined rate, or performing the above-mentioned constant temperature holding in a temperature decreasing process after heating and holding to 1100 ° C. or more, or by performing a temperature lowering process. It is possible to simultaneously form a BMD on a large number of wafers to provide IG capability and to form a defect-free region (DZ layer), so that heat treatment of a large number of wafers is completed efficiently and in a short time.

Further, according to the heat treatment method of the present invention, for example, a large number of wafers are simultaneously heated at 1280 ° C. to 1380 ° C.
And the COP in the surface layer and inside of the wafer can be reduced or eliminated by this heat treatment, so that there is an advantage that a high-quality wafer can be stably supplied.

[Brief description of the drawings]

FIG. 1A is an explanatory top view of a heat treatment boat used in a heat treatment method according to the present invention, and FIG.

FIG. 2 is a graph showing a relationship between a heat treatment temperature and a non-defective product rate, showing a result of evaluating an oxide film breakdown voltage characteristic of a wafer by a heat treatment method of the present invention.

FIG. 3 is an explanatory perspective view showing another embodiment of the heat treatment boat used in the heat treatment method according to the present invention.

FIG. 4 is an explanatory longitudinal sectional view of the heat treatment boat shown in FIG. 3;

FIG. 5 is a perspective explanatory view showing another embodiment of the heat treatment boat used in the heat treatment method according to the present invention.

FIG. 6 is an explanatory view showing a configuration of a conventional robot for transferring a single wafer of wafers, wherein A shows a suction type and B shows a scooping type configuration.

FIG. 7 is an explanatory top view showing a configuration of a robot for transferring a wafer used in the present invention.

8A is an explanatory front view showing another configuration of a wafer transfer robot used in the present invention, FIG. 8B is an explanatory top view thereof, and FIG. 8C is an explanatory top view showing another embodiment. is there.

FIG. 9A is an explanatory view showing an example of a use situation of the heat treatment boat used in the present invention, and FIG. 9B is an explanatory top view thereof.

FIG. 10A is an explanatory view showing an example of the configuration of a heat treatment boat used in the present invention, and FIG. 10B is an explanatory top view thereof.

FIG. 11 is a graph showing a relationship between a surface depth of a wafer and an oxygen concentration.

FIG. 12 is a graph showing a relationship between a surface depth of a wafer and an oxygen concentration.

FIGS. 13A and 13B are heat pattern diagrams showing an example of heat treatment conditions.

FIG. 14 is a graph showing a relationship between a difference in oxygen concentration and a BMD density of a wafer subjected to a heat treatment method according to the present invention. In the figure, A is the initial oxygen concentration of 12.5 to 13 × 10 ¹⁷
A low oxygen concentration wafer of atoms / cm ³ , B is a medium oxygen concentration wafer having an initial oxygen concentration of 13.5 to 14 × 10 ¹⁷ atoms / cm ³ , and C is an initial oxygen concentration of 14.5 to 15 ×.
10 shows a high oxygen concentration wafer at 10 ¹⁷ atoms / cm ³ .

FIG. 15 is a graph showing a relationship between a difference in oxygen concentration of a wafer subjected to a heat treatment method according to the present invention and a DZ layer width.

FIG. 16 is a graph showing the relationship between the number of times of repeated washing and the number of LPDs.

17A is a perspective view illustrating an AFM image of a COP defect on a wafer surface, and FIG. 17B is a perspective view of a defect having a hollow interior and a polyhedral shape having an octahedral basic structure estimated from FIG. .

FIG. 18 is a partially cutaway perspective view showing a schematic configuration of a conventional silicon single crystal wafer heat treatment apparatus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon single crystal wafer 2 Silicon boat 3 Holding plate 4 Heat treatment furnace 10, 20, 30, 40, 50 Heat treatment boat 11 Lower plate 12 Upper plate 13, 14 Front support plate 13a, 14a, 15a, 13b, 14b, 15b, 1
3c, 14c, 15c Support holder 15 Rear support plate 17 Thickness of support holder 21, 22, 23 Support holder 24 Opening 25 Insertion groove 30 Heat treatment boat 31 Boat unit 32 Support holder 33 Insertion groove 40 Arm 41 Suction plate 42 Mounting Plate 43, 45, 46 Jig 44 Notch 51 Buffer material

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 21/322 H01L 21/322 Y (56) References JP-A-6-163440 (JP, A) JP-A-53-25351 ( JP, A) JP-A-6-5611 (JP, A) JP-A-58-87833 (JP, A) JP-A-1-242500 (JP, A) JP-A-5-345699 (JP, A) JP-A-6-45269 (JP, A) JP-A-6-268048 (JP, A) JP-A-7-147258 (JP, A) JP-A-5-121414 (JP, A) JP-A-5-326535 (JP) JP-A-55-77170 (JP, A) JP-A-8-18084 (JP, A) JP-A-1-280322 (JP, A) JP-A-8-1007081 (JP, A) 6-196491 (JP, A) Japanese Utility Model Showa 55-62042 (JP, U) Japanese Utility Model Application Hei 5-59837 (JP, U) (58) Fields surveyed (In t.Cl. ⁷ , DB name) H01L 21/22-21/24 H01L 21/26-21/268 H01L 21/322-21/326 H01L 21/68

Claims (17)

(57) [Claims] A plurality of silicon single crystal wafers are stacked and arranged on a heat treatment boat so that only the lowermost wafer of the group of wafers formed by stacking a plurality of silicon single crystal wafers is supported by the heat treatment boat. , Each wafer group is horizontal or one side is tilted above the horizontal,
Heat treatment method for a silicon single crystal wafer to be heat treated without Rukoto to generate slip each wafer stacked except the lowermost wafer in each wafer groups by heating to at least 1100 ° C. or higher. 2. The method according to claim 1, wherein the inclination angle is 0.5 to
A heat treatment method for a silicon single crystal wafer at 5 °. 3. The method according to claim 1, wherein the heat treatment atmosphere is a non-oxidizing gas atmosphere, and each wafer group is configured by alternately stacking a wafer in which a thermal oxide film is generated in advance and a wafer without a thermal oxide film. A heat treatment method for a silicon single crystal wafer having a structure in which a thermal oxide film is formed on all the surfaces. 4. The heat treatment method for a silicon single crystal wafer according to claim 1, wherein the heat treatment atmosphere is an oxygen gas alone or an oxygen-containing inert or reducing gas atmosphere. 5. The method for heat treating a silicon single crystal wafer according to claim 1, wherein each group of wafers is placed on a heat treatment boat via a disk or a ring made of a material having excellent high-temperature strength. 6. The method according to claim 1, wherein the heat treatment includes a step of forming a defect-free region (DZ layer) in a surface layer of the wafer. 7. The method for heat treating a silicon single crystal wafer according to claim 6, wherein the heat treatment is performed at 1100 ° C. to 1380 ° C. for 5 minutes to 6 hours at the time of raising or lowering the temperature. 8. The method according to claim 7, wherein the temperature is raised to 500 ° C.
Heat treatment is performed for 10 minutes or more and 4 hours or less in a temperature range of up to 900 ° C. to form an oxygen precipitate to impart IG capability.
A heat treatment method for a silicon single crystal wafer which is heat-treated at 100 ° C. or higher. 9. The method according to claim 7, wherein the temperature is 500 ° C. to 900 ° C.
The temperature is raised at a rate of 0.5 ° C./min to 5 ° C./min in the range of to form an oxygen precipitate to impart IG capability,
Then, a heat treatment method for a silicon single crystal wafer, which is heat-treated at 1100 ° C. or higher. 10. The IG according to claim 7, wherein a heat treatment is performed at a temperature in the range of 500 ° C. to 900 ° C. for 10 minutes to 16 hours to form oxygen precipitates in the temperature decreasing process after the heat treatment at 1100 ° C. or more. A heat treatment method for a silicon single crystal wafer that imparts functions. 11. The method according to claim 7, wherein in the cooling step after the heat treatment at 1100 ° C. or more, the cooling rate in the range of 500 ° C. to 900 ° C. is 0.5 ° C./min to 5 ° C./min,
A heat treatment method for a silicon single crystal wafer for providing an IG function by forming an oxygen precipitate. 12. The method according to claim 1, wherein the heat treatment is performed at a temperature of 1250 ° C. or more, so that the COP in the surface layer of the wafer and the C
A heat treatment method for a silicon single crystal wafer including a step of reducing a grown-in defect that causes an OP. 13. The method according to claim 12, wherein the temperature is from 1280 ° C. to 1
A heat treatment method for a silicon single crystal wafer, which is heat-treated at 380 ° C. for 5 minutes to 6 hours. 14. The heat treatment of a silicon single crystal wafer according to claim 13, wherein the heat treatment is performed at 1100 ° C. to 1380 ° C. for 5 minutes to 6 hours at the time of raising or lowering the temperature to form a defect-free region (DZ layer) on the surface layer of the wafer. Method. 15. The method according to claim 14, wherein the temperature is raised by 50%.
Heat treatment in the range of 0 ° C. to 900 ° C. for 10 minutes to 4 hours, or increase the temperature in the range of 500 ° C. to 900 ° C. to 0.5 ° C./min. A method for heat-treating a silicon single crystal wafer that imparts IG capability by forming silicon. 16. The method according to claim 14, wherein the temperature is lowered by 5%.
Heat treatment in the range of 00 ° C to 900 ° C for 10 minutes to 16 hours, or the cooling rate in the range of 500 ° C to 900 ° C of 0.5 ° C / min to 5 ° C / min to form oxygen precipitates to form IG A heat treatment method for a silicon single crystal wafer that imparts functions. 17. A plurality of silicon single crystal wafers are stacked and arranged on a heat treatment boat such that only the lowermost wafer of the group of wafers formed by laminating a plurality of silicon single crystal wafers is supported in contact with the heat treatment boat. Each wafer group is horizontally or one side is tilted upward from the horizontal, and 1280 in an oxygen-containing inert or reducing gas atmosphere.
° C. to 1380 and a heat treatment of 5 minutes to 6 hours at ° C., to generate a slip bottom layer wafer for each wafer groups, of laminated
Grow which is the source of the COP in the surface layer of the wafer and the internal COP without any slip on each product wafer
A method for producing a silicon single crystal wafer for obtaining a wafer without n-in defects.