JP2908183B2 - SRTS jitter reduction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an ATM (Asynchronous
(Transfer Mode: Asynchronous Transfer Mode) In communication, the present invention relates to a method of transferring a signal asynchronous with a network clock into cells.

[0002]

2. Description of the Related Art CCITT Recommendation 1.363 states that ATM
As a means for transferring frequency information of an original signal when a signal asynchronous with a network clock is converted into cells and transmitted, a SRTS (Synchronous Residual Time Stamp) is recommended. This is because As indicated by reference numeral 363, the p-bit counter is driven by the x-divided clock fnx of the network clock fn, and the output of this counter is latched every N counts of the clock fs of the transferred signal. The latched result is RTS (ResidualTime
Stamp). This RTS is used as the CSI (C
Onvergence Sublayer Indication) bit is used for transfer, and the receiving side reproduces the clock fs by the phase-locked oscillator PLO based on the received RTS.

[0003] As a conventionally known circuit, for example, a reference (CCITT SG XVIII D.1745, Melbourne, December
1991). FIG. 4 shows an example of a circuit on the transmission side, and FIG. 5 shows an example of a circuit on the reception side. Figure 4 shows CCIT
T Recommendation I. 363. The p-bit counter of 1 is driven by the X-divided clock fnx and is free running. The output of the p-bit counter is latched every N clocks of the clock fs of the signal to be transferred, and RT
It is transmitted and output as S information. On the receiving side, the received R
The TS is stored in the FIFO memory 51. The RTS read from the memory 51 is compared by a p-bit comparison circuit 52 with an output of a p-bit counter 55 driven by the frequency-divided clock fnx. Separately, an M1 frequency dividing counter 56 is prepared, which is also driven by the clock fnx. Here, M1 is set to a value slightly smaller than N * fnx / fs. When the count value of the M1 frequency dividing counter 56 becomes full, the gate circuit 53 is opened, and the circuit itself stops. The coincidence pulse output from the p-bit comparison circuit 52 after the gate circuit 53 is opened is supplied to the phase-locked oscillator 54, and at the same time, resets the M1 frequency division counter.
Read a new RTS from 1.

[0004]

SRTS is a technique similar to the well-known pulse stuff synchronization scheme.
It is known that low-frequency jitter called latency jitter occurs in pulse stuff synchronization (for example, "Easy Digital Transmission", edited by Yamashita, Telecommunications Association). Similarly, low frequency jitter also occurs in the SRTS. Literature (Murakami "Jitter in SRTS", 19
According to the 1992 IEICE Spring Conference), the amplitude Aj of the low-frequency jitter is

[0005]

(Equation 1) Given by Here, N is a parameter that determines the period for latching the output of the p-bit counter,

[0006]

[Mathematical formula-see original document] Mq = [N * fnx / fs] where [x] is a Gaussian symbol representing the largest integer not exceeding,

[0007]

R = N * fnx / fs-Mq = q / p, where p and q are integers, and therefore R is a rational number.
R is a parameter called a residue. As described in the above document, low frequency jitter having an amplitude given by the above equation 1 occurs when R is near a rational number. Low frequency jitter is difficult to suppress by a phase locked loop PLL or the like, and deteriorates quality.

The North American DS3 interface fs =
The value of Mq in the case of 44.736 MHz (Mq = 522
FIG. 6 shows the result obtained by simulation of the output jitter amplitude in the range of 0 to 1 for the remainder R with respect to 8). However, as the PLL in FIG. 5, the jitter cutoff frequency is 1 ppm of 44.736 MHz.
A frequency of 4.736 Hz was used. FIG.
The change range of the remainder R when 4.736 MHz is changed with its allowable frequency deviation ± 20 ppm is shown. FIG.
From this, it can be seen that low frequency jitter of about 0.3 UIp-p occurs when the remainder R is around 0.5.

[0009]

SUMMARY OF THE INVENTION The present invention reduces jitter generated by varying a parameter N for determining a period for latching the output of a p-bit counter on the transmission side above and below an average value NO. Is what you do.

[0010]

When the transmitting side latches the output of the counter driven by the clock fnx obtained by dividing the network clock fn, the jitter generated on the receiving side is changed by changing the dividing ratio N of the transferred signal. Can be reduced.

[0011]

Next, an embodiment of the present invention will be described.

FIG. 1 is a block diagram showing a configuration of a jitter reduction system according to the present invention. The present invention only modifies the prior art transmitter, so FIG. 1 is an example circuit on the transmitter. On the receiving side, for example, the conventional circuit of FIG. 5 can be used as it is.

In FIG. 1, 1 is a p-bit counter driven by an x-divided clock fnx of the network clock fn, and 2 is a clock f of a signal to which a counter output is transferred.
A p-bit latch circuit that latches every N counts of s,
The latched result is transferred to the receiving side using the CSI bit in the cell as RTS. Reference numeral 4 denotes an N-ary counter for controlling the latch circuit 3. The dividing ratio N can be temporally changed from the outside. This point is a feature of the present invention.

The transmitting side circuit example of FIG. 1 is different from the conventional transmitting side circuit example of FIG. 4 in that the frequency division ratio of the N frequency dividing counter 3 can be externally controlled. The circumference ratio N can take any one of the average values NO, NO + 1, and NO-1. Here, the frequency division ratio is changed every cycle of the N frequency division counter. Therefore, the N dividing counter is
For example, in the first one cycle, NO frequency division, and in the next one cycle, N
O + 1 frequency division, and in the next one cycle, NO-1 frequency division is performed. How to change the frequency division ratio is determined by the parameters of the target system.

FIG. 2 is a view similar to the conventional example of FIG.
For Mq at 44.736 MHz, which is the S3 interface, the output jitter amplitude when N is changed in the order of NO, NO + 1, and NO-1 at period 3 was obtained by simulation for the range of remainder R from 0 to 1. Things. The receiver circuit shown in FIG. 5 is used, and the jitter cutoff frequency of the PLL is 4 as in the conventional example shown in FIG.
4.736 MHz. It can be seen that, for example, when the remainder R = 0.0, 0.5, 1.0, the jitter amplitude is reduced as compared with the output jitter of the prior art of FIG. Therefore, the jitter amplitude is reduced in the allowable frequency range of 44.736 MHz, which is the DS3 interface in North America. On the other hand, when R = 1/3, the jitter amplitude increases.
That is, when N is changed in cycle 3, R = 0.0,
It can be seen that there is an effect near 0.5 and 1.0.

FIG. 3 is a simulation result of the output jitter when N is changed in the order of NO + 1 and NO-1 at the period 2. The parameters used are the same as in FIG.
In this case, when R = 1/3, the jitter amplitude is smaller than that in FIG. On the other hand, when R = 0.5, the jitter amplitude increases.

From the above, it can be seen that the output jitter amplitude can be reduced by appropriately selecting a change in the parameter N that determines the cycle of latching the p-bit counter for a given remainder R. In addition, the present invention can be realized by changing only the transmitting side circuit, and the receiving side circuit may be a conventional technique. It has the advantage that it can be interconnected freely.

Here, the changing period of N is 2 or 3
Although the case of (1) has been exemplified, other change periods may be adopted. Further, it is also possible to change N randomly without periodicity.

[0019]

As described above, according to the present invention, the SR
The output jitter amplitude when the TS method is adopted can be effectively reduced by a simple circuit. Further, it can be freely connected to a device to which the present invention is not applied.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a jitter reduction system according to the present invention.

FIG. 2 is a diagram showing a simulation result of an output jitter amplitude of the jitter reduction method according to the present invention.

FIG. 3 is a diagram showing a simulation result of an output jitter amplitude of the jitter reduction method according to the present invention.

FIG. 4 is a block diagram showing a configuration of a transmission side of a conventional SRTS.

FIG. 5 is a block diagram showing a configuration of a receiving side of a conventional SRTS.

FIG. 6 is a diagram showing a simulation result of an output jitter amplitude by the conventional SRTS method.

[Explanation of symbols]

 Reference Signs List 1 p-bit counter 2 p-bit latch circuit 3 N-ary counter 51 FIFO memory 52 p-bit comparison circuit 53 gate circuit 54 phase-locked oscillator 55 p-bit counter 56 M-ary counter

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hiromi Ueda 1-6-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-7-38570 (JP, A) Patent 2620443 ( JP, B2) IEICE Technical Report, CS92-106 (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 7/02 H04L 12/28

Claims (6)

(57) [Claims] 1. An S which transfers the result of latching the output of a counter driven by a clock synchronized with a network clock with an N-divided clock of a clock of information to be transferred.
The jitter reduction method according to the RTS method, further comprising means for changing a frequency dividing ratio N of the clock of the transferred information above and below an average value NO. 2. The jitter reduction method according to claim 1, further comprising means for changing the frequency division ratio N by three types of average values NO, NO + 1, and NO-1. 3. The jitter reduction method according to claim 1, further comprising means for changing the frequency division ratio N between two types, that is, NO + 1 and NO-1 with respect to the average value NO. 4. The jitter reduction method according to claim 1, further comprising means for periodically changing the frequency dividing ratio N above and below its average value NO. 5. The method according to claim 4, wherein the dividing ratio N is NO, N
A jitter reduction method comprising means for changing the order of O + 1, NO-1 or NO, NO-, NO + at a cycle 3. 6. The method according to claim 4, wherein the dividing ratio N is NO +
1. A jitter reduction method comprising means for changing in the order of 1, NO-1 at period 2.