JP2706199B2 - SDH interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous digital hierarchy (hereinafter referred to as "SDH") interface circuit in a broadband integrated services digital network (hereinafter referred to as "wideband ISDN").

[0002]

2. Description of the Related Art A configuration example of an SDH interface circuit in a conventional wideband ISDN will be described with reference to FIGS. The interface structure of the SDH-based physical layer has a transmission frame conforming to Recommendations G707, G708, and G709 that defines the network node interface structure of SDH. FIG. 11 shows an example of the structure.
The information is in units of 53 bytes of cell C, with 8 bits as 1 byte. In order to store the cell C in the interface structure related to the 155.52 Mbit / s interface, a continuous full cell stream of the cell C is stored in the C-4 area which is the payload of the VC-4 of the virtual container of the SDH. Next, VC-
AU-4 is formed by adding a 4-pass overhead.
The cell boundary is aligned with the STM-1 byte boundary, but the C-4 capacity (2340 bytes) is equal to the cell length (533 bytes).
(byte), the cell may span a C-4 boundary on two separate transmission frames.

FIG. 10 is a block diagram of a conventional SDH interface circuit, in which a signal flow from right to left is a transmission system, and a signal flow from left to right is a reception system. This is provided as a signal system. Here, the receiving system will be mainly described. In the figure, the SDH interface circuit includes a section terminating unit 101, a clock transfer unit 100, a pointer terminating unit 102, a POH terminating unit 103, and a cell terminating unit 104. STM-1 to the section end part 101
The signal is transmitted in the state of (1), AU-4 after the clock transfer unit 100, the pointer is separated at the pointer termination unit 102 to VC-4, and then the POH is separated at the POH termination unit 103 to C-4. Finally, in the cell termination unit 104, a transmission format conversion for converting between the container and the full cell stream and a cell length conversion such as removing cells having no information in C-4 are performed to perform a full cell stream. And

[0004] The section terminating unit 101 operates with a transmission line clock, and the pointer terminating unit 102, the POH terminating unit 103, and the cell terminating unit 104 operate with a local clock. The transmission line clock and the intra-station clock are input to the clock transfer unit 100. If the transmission line clock and the intra-station clock have different frequencies, the frequency is changed by converting the clock to perform speed matching. ing.

The clock transfer unit 100, the pointer terminating unit 102, and the POH terminating unit 103 are composed of one element and are called path terminating units. Further, the path termination unit absorbs jitter, wander and frame phase difference generated as a time shift from a normal position between the intra-station clock and the transmission line clock.

Accordingly, in the conventional SDH interface circuit, the speed change and the absorption of jitter, wander and frame phase difference are performed in the path termination unit constituted by the clock transfer unit 100, the pointer termination unit 102 and the POH termination unit 103. I do. FIG. 11 shows a conventional S
It is a block diagram of speed matching of a DH interface circuit. The conventional speed matching will be described with reference to FIG.

The cell C is stored in a container C-4, and
H-added VC-4 to which an AU-4PTR pointer and SOH are further added, STM-1 is
-C transfer unit 100 using the -C transmission clock
(See FIG. 10). When the transmission clock CLK-C and the intra-station clock CLK-C0 have the same frequency,
Since there is no need to perform speed matching, the data is transmitted directly to the station.

When the frequency of the transmission clock CLK-C is higher than the frequency of the intra-station clock CLK-C0, the next byte of the pointer AU-4PTR in the figure is used as a stuff byte, and the pointer value is increased by one. If the frequency of the intra-office clock CLK-C0 is higher than the frequency of the transmission clock CLK-C, the pointer value of the pointer AU-4PTR in the figure is reduced by one, and a negative stuff byte is added to the pointer AU-4PTR. Accommodates and transmits VCs. In this way, the absorption of small frequency fluctuations is accommodated by the stuff control for increasing or decreasing the pointer value by one.

Next, as a conventional example for absorbing jitter, wander, and frame phase difference, “Keep frame phase difference” published by Masahiro Takatori (four others) at the 1990 Spring Meeting of the Institute of Electronics, Information and Communication Engineers (IEICE). SDH Pointer Conversion Method "(1990 IEICE Spring National Convention B-764), and FIG. 12 is a block diagram of the pointer conversion circuit.

The pointer conversion circuit includes a VC buffer 110 for temporarily storing a VC, an input control unit 111 for decoding a reception pointer from the VC and controlling writing of the VC into the VC buffer 110, reading control from the VC buffer 110, and An output control unit 113 performs output pointer generation control including output stuff control, and a stuff determination unit 112 that determines whether to perform stuffing by comparing the difference between the write address and the read address.

These processes are performed by the stuff control of the clock transfer unit 100 (see FIG. 10) at the end of the path.

[0012]

However, the above-mentioned conventional method has the following problems. The path terminator performs stuff control and speed matching and absorbs jitter, wander and frame phase differences, and the cell terminator performs transmission format conversion and cell length conversion. Therefore, there is a disadvantage that the gate scale increases and the hardware configuration becomes complicated.

Further, since a plurality of VCs are multiplexed in a frame, the number of pointer conversion circuits in the path termination unit is required by the number of VCs. Generally each VC
Are independent signals having different frame phases, it is necessary to independently perform pointer conversion on a plurality of multiplexed VCs. However, if VCs are controlled independently, the frame phase difference between VCs may be different. Therefore, in order to realize a communication service using a plurality of channels at the same time, a large-capacity buffer for phase adjustment and a complicated control circuit are required at the path termination unit.

Therefore, the functions of speed matching and absorption of jitter, wander and frame phase difference in the conventional SDH interface circuit are performed by clock transfer and stuff control of a large amount of information in units of frames at the path termination. Requires a large-capacity memory and a gate, and the hardware configuration becomes complicated. The present invention eliminates the above-mentioned problems, removes the drawback that the hardware configuration becomes complicated as the memory capacity and the gate scale increase, and provides an SDH interface circuit excellent in simplification of the memory capacity, the gate scale and the hardware configuration. The purpose is to provide.

[0015]

According to the present invention, there is provided an SDH interface circuit comprising: a cell terminator for performing format conversion and cell length conversion; a means for introducing a transmission line clock and an intra-office clock to the cell termination; Means for matching the difference between the frequencies of the clocks, and means for eliminating the phase difference between the clocks. The means for adjusting the difference between the frequencies and the means for eliminating the phase shift are provided in the cell termination unit. Thus, speed matching by clock transfer at the cell end portion and absorption of jitter, wander and frame phase difference by stuff control are performed.

[0016]

According to the present invention, in the above-mentioned configuration, the termination unit of the SDH interface circuit inputs a first-in first-out memory for inputting input data and outputting output data, and introduces either a transmission line clock or an intra-office clock. A write control unit for controlling the writing of the first-in first-out memory, and a clock different from the clock introduced into the write control unit, which is either a transmission line clock or an in-station clock, is introduced, A read control unit for controlling the reading of the memory, when a mismatch occurs between the input data input to the cell termination unit and the output data output due to a shift in the frequency or phase of the transmission line clock and the local clock. , The write control unit discards the data for one cell length, and Control unit sends an empty cell.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the SDH interface circuit of the present invention. Here, the receiving system will be mainly described as in the description of the above-described conventional example. This is because the clock fluctuation which causes jitter and wander occurs only in the receiving system.

In this configuration, the speed matching, jitter, and wander absorption functions performed in the conventional path termination unit are provided in the cell termination unit. In FIG. 1, the SDH interface circuit of the present invention includes a section terminator 1, a pointer terminator 2, a POH terminator 3, and a cell terminator 4 in order toward a receiving device.

The STM-1 from the transmission line is designated as AU-4 in the section termination section 1, the pointer is separated in the pointer termination section 2 as VC-4, and then the POH termination section 3
, The POH is separated into C-4, and finally, in the cell termination unit 4, the transmission format conversion for converting between the container and the full cell stream and the cells having no information in C-4 are removed. Is performed to obtain a full cell stream. The cell termination unit 4 has not only a format conversion function and a cell length conversion function but also a speed matching by clock transfer, a jitter by stuff control, and a wander absorption function. The section terminating unit 1, the pointer terminating unit 2, and the POH terminating unit 3 operate with the transmission line clock, and the cell terminating unit 4 and thereafter operate with the intra-office clock. In addition, the cell termination part 4
In addition to the intra-station clock, a transmission line clock is added for speed matching.

With this configuration, the speed matching function is performed in the cell termination unit 4 instead of the conventional clock transfer unit in the path termination unit. The path terminating unit which has conventionally been constituted by the clock transfer unit, the pointer terminating unit and the POH terminating unit is constituted by the pointer terminating unit 2 and the POH terminating unit 3. And
The function of absorbing the jitter, wander and frame phase difference is also performed by clock switching and stuff control performed in the cell termination unit 4 instead of the clock switching unit of the conventional path termination unit.

Therefore, according to this configuration, the speed matching and the processing of absorbing the jitter, wander and frame phase difference are conventionally performed by the processing of a large amount of information in units of frames in the path terminating unit. By performing processing with a small amount of information in units of cells in 4, it is possible to reduce the amount of processing information and the memory required for processing. The reasons for this decrease in memory are that the amount of information processing is reduced from the conventional frame unit to the cell unit, and the memory in both the conventional path termination unit and the cell termination unit is changed to the cell termination unit 4 only. There are two points of reduction due to this.

2-8, the speed matching and the function of absorbing jitter, wander and frame phase difference at the cell terminal will be described. First, referring to FIG. 2, a configuration example of the cell length conversion including the speed matching and the jitter in the cell termination unit 4 (see FIG. 1) and the wander absorption function will be described. The cell termination unit 4 includes a first-in first-out memory (hereinafter referred to as FIFO) 41 and its FIFO4
Write control unit 42 and FIFO 4 for controlling writing
1 is configured by a read control unit 43 that controls the reading of data.

The receiving system will be described.
The cell C of C-4 is written by the transmission system clock CLK1 under the control of the write control unit 42 to the input unit of. On the other hand, a full cell stream whose cell length has been converted as shown in the figure is output by the read control unit 43 at the output unit of the FIFO 41 with the intra-station clock CLK0. For speed matching, jitter and wander absorption, the difference between the write address and the read address is compared to determine the stuff of the cell. Note that the content of an empty cell transmitted by the stuff determination of this cell is different from that of an empty cell indicated by * in FIG. Empty cells indicated by * in FIG. 2 are SOH,
This is a cell that fills a gap in the POH area, and is invalid data.

The operation of the FIFO 41 of FIG. 2 will be described with reference to the flowchart of FIG. Steps S1 to S5 in the flowchart of FIG. 3A are steps at the time of writing the input data to the FIFO 41, and FIG.
Steps S6 to S10 in the flowchart of FIG.
Is a step at the time of reading output data from the FIFO 41.

First, the steps at the time of writing will be described with reference to FIG. At the start of step S1, writing is started, and at step S2, it is determined whether or not the writing of the input data to the memory of the FIFO 41 for one cell length has been completed. If it is determined in step S2 that the writing of the input data to the memory of the FIFO 41 for one cell length has not been completed, the determination is NO, and the processing is repeated until the writing is completed. FIFO4 for one cell length of input data
When the writing of data to the memory 1 is completed, the determination in step S2 is YES, and the process proceeds to step S3, where the FIFO4
The process proceeds to the process of writing to the memory No. 1.

Next, in step S4, step S3
It is determined whether or not the memory in the writing process is the same as the memory currently being read. In this determination, if the memory that has undergone the writing process is different from the memory that is being read at that time, the determination in step S4 is NO, and the process returns to step S2 to write one cell length into the memory. If the memory in the writing process is the same as the memory being read at that time, step S
No. 4 determines YES, and discards data of one cell length in the writing process in step S5. This writing step is performed by the transmission system clock CLK1 in FIG.

Next, steps at the time of reading will be described with reference to FIG. Reading is started at the start of step S6, and FIFO 41 to be read in step S7.
It is determined whether or not the memory corresponding to one cell length is stored in the memory. In the determination in step S7, the read F
If data of one cell length is not stored in the memory of the IFO 41, NO is determined, and the routine goes to Step S10.

In step S10, an empty cell containing no data is transmitted. This empty cell is different from the empty cell, which is a cell that fills the gap between the SOH and POH regions indicated by * in FIG. After the transmission of the empty cell in step S10, the process returns to step S7 again, and 1 is stored in the memory of the FIFO 41 to be read.
It is determined whether or not data corresponding to the cell length is included. Also, in the determination of step S7, the read FIFO
If the memory of O41 contains data for one cell length, Y
It is determined as ES, and the process proceeds to step S8.

In step S8, the data in the memory in the process of reading out the FIFO 41 is transmitted. When the transmission of the data is completed, the process moves to the next step S9, moves to the next memory reading, and returns to step S7. This step at the time of reading is performed by the intra-station clock CLK0 in FIG. Next, speed matching will be described. Here, for ease of explanation, it is assumed that there is no jitter, wander and frame phase difference.

FIGS. 4 to 6 are conceptual diagrams for explaining the speed matching function. The transmission system clock frequency CL1 is equal to the intra-station clock frequency CL0, and the transmission system clock frequency CL1 is equal to the intra-station clock frequency. A description will be given along the flow of the flowchart of FIG. 3 in three cases, that is, a case where the frequency is higher than CL0 and a case where the intra-station clock frequency CL0 is higher than the transmission system clock frequency CL1. Note that the FIFO 41 is a first-in first-out memory in which data input first is output first, and here is composed of two memories, a first memory 44 and a second memory 45, for ease of explanation. The description will be made as follows.

First, a case where the frequency CL1 of the transmission system clock is equal to the frequency CL0 of the local clock will be described with reference to FIG. FIG. 4A assumes that a signal is transmitted from the left side to the right side in the receiving system. A transmission system clock having a frequency CL1 and an intra-office clock having a frequency CL0 are introduced into a FIFO 41 of a cell termination unit (not shown).

In FIG. 4B, data 1 for one cell length is written into the first memory 44, and the data is stored in the step S of FIG.
In step 2, the process shifts to writing the next data in the second memory 45. In step S4 of FIG. 3A, since the second memory 45 is not the memory that is reading, writing to the second memory 45 proceeds. Again in step S2 of FIG.
When the writing of the data 2 corresponding to the cell length to the second memory 45 is completed, the step of writing to the data 3 shown in FIG.
Move to (c).

In FIG. 4C, step S in FIG.
Since the determination at 4 is NO, the input of the data 3 to the first memory 44 is continued. The determination of NO in step S4 is because the data 1 recorded in the first memory 44 at this time has already been read. That is, in the determination of step S7 in FIG. 3B, the frequency CL1 of the transmission system clock and the frequency CL
4B, data 1 for one cell length is already stored in FIG. 4B, and the data 1 is transmitted in step S8 in FIG. This is because the data is empty.

Accordingly, the transmission system clock frequency CL
When 1 is equal to the frequency CL0 of the intra-station clock, the clock is transmitted to the intra-station as it is. Next, a case where the transmission system clock frequency CL1 is higher than the intra-office clock frequency CL0 will be described with reference to FIG. FIG. 5A also assumes that a signal is transmitted from left to right in the receiving system. The frequency CL1 is stored in the FIFO 41 of the cell termination unit 4.
, And an intra-office clock having a frequency CL0.

In FIG. 5B, data 1 for one cell length is written to the first memory 44, and the process proceeds to writing the next data to the second memory 45 in step S2. In step S4 of FIG. 3A, since the second memory 45 is not the memory that is reading data, writing of the data 2 to this memory 45 proceeds. When the writing of the data 2 for one cell length into the second memory 45 is completed again in step S2 of FIG. 3A, the process proceeds to FIG.

In FIG. 5C, step S in FIG.
Since the determination at 4 is YES, the process proceeds to step S5, where data 3 which is data for one cell length is discarded.
The determination of YES in step S4 is because the data 1 recorded in the first memory 44 at this point has not been completely read. That is, since the frequency CL1 of the transmission system clock is higher than the frequency CL0 of the intra-office clock, the writing speed of writing the data 2 to the second memory 45 is faster than the reading speed of the data 1 recorded in the first memory 44. In step S4, the first data 3
This is because the reading of the data 1 from the first memory 44 has not been completed yet when the writing to the memory 44 is started.

Next, in FIG. 5 (d), after the data for one cell length is discarded in step S5 of FIG. 3 (a), the operation shifts to writing the next data. At this time, since the position of the memory to be written next does not change, the next data 4 is written to the first memory 44. In step S4 of FIG. 3A, it is determined whether the next data 4 can be written to the first memory 44. At this point, since the data 1 stored in the first memory 44 has been read, YES is determined in step S4, and the data 4 is written to the first memory 44.

In FIG. 5E, when the transmission of the data 2 is completed, the first memory 44 is read in step S7 of FIG. 3B in accordance with step S9.
At this point, since the writing of the data 4 to the first memory 44 has not been completed, it is determined NO in step S7,
In step S10 of (b), an empty cell is transmitted. Therefore, at this stage, writing of data 4 to the first memory 44 and sending of empty cells are performed.

When the writing of the data 4 to the first memory 44 is completed, YES is determined in step S2 of FIG. 3A, and the writing of the data 5 to the second memory 45 which is the next memory is performed in step S3. Done. In the determination in step S4 of FIG. 3A, the memory being read is the first memory 44, so that the determination is NO, and the second memory 4
Writing of data 5 to 5 is continued.

In FIG. 5F, when the writing of the data 5 to the second memory 45 is completed, the frequency CL1 of the transmission system clock is higher than the frequency CL0 of the local clock as described above, so that the first Reading of the data 4 from the memory 44 has not been completed yet. Therefore, in writing the next data 6 to the first memory 44, FIG.
The determination in step S4 of (a) is YES, and FIG.
In step S5 of (a), data corresponding to one cell length of data 6 is discarded.

Thereafter, the state becomes substantially the same as that shown in FIG. 5B, and the difference in frequency is repeated for the same period. Next, the frequency CL0 of the intra-station clock is set to the frequency CL of the transmission system clock.
The case where it is higher than 1 will be described with reference to FIG. FIG. 6 (a)
It is also assumed that a signal is transmitted from the left side to the right side in the receiving system. FIFO 41 of cell termination unit 4
, A transmission system clock having a frequency CL1 and an intra-office clock having a frequency CL0 are introduced.

In FIG. 6B, in step S2 of the flowchart of FIG.
Is written to the first memory 44, and the process proceeds to writing the next data to the next second memory 45 in step S2. And
As shown in FIG. 6C, step S in FIG.
In No. 4, since the second memory 45 is not the memory that is reading, writing of the data 2 to the second memory 45 proceeds. At this time, since the frequency CL0 of the intra-station clock is higher than the frequency CL1 of the transmission system clock, the second memory 4
Before the writing of the data 2 to the first memory 4 is completed, the first memory 4
The reading of data 1 from 4 ends.

Next, in FIG. 6D, when the data transmission is completed in step S8 of FIG.
To step S9, and then to reading of the next memory. This next memory read control is performed in step S7. However, since writing of data 2 to second memory 45 has not yet been completed, the determination is NO, and step S10 is performed.
Send an empty cell.

As shown in FIG. 6 (e), when the timing of writing data 3 to the first memory 44 comes while an empty cell is being transmitted, the data in the first memory 44 has already been read. 3A, the determination is NO in step S4 of FIG. 3A, and the process proceeds to step S2.
Write data for one cell length. 6 (e) and 6
In (f), when the transmission of empty cells from the second memory 45 is completed, the process proceeds to reading of data from the next memory.

Since the position of the next memory to be read after sending an empty cell does not change, the next data 2 is read from the second memory 45. After reading from the second memory 45,
By the step S9 in FIG.
Is read out of the data 3 stored in. The subsequent state is almost the same as in FIG. 6B, and is repeated while the frequency difference is the same.

Therefore, data and empty cells are transmitted within the station. Since this difference in frequency is a rare phenomenon, speed matching can be performed by discarding some data and transmitting empty cells. Next, absorption of jitter, wander and frame phase difference will be described. 7 and 8 are conceptual diagrams for explaining the function of absorbing jitter, wander and frame phase difference. Wander is a long-period fluctuation due to fluctuations in the transmission delay time of the transmission line due to temperature changes, and its period fluctuation is much longer than jitter, and its absorption operation can be explained in the same way as jitter. Therefore, the jitter will be described here.

The case where the clock is shifted forward from the normal position and the case where the clock is shifted backward from the normal position will be described with reference to the flow chart of FIG. 3 by taking the jitter of the transmission system clock as an example. . The FIFO 41 is a first-in first-out memory in which data input first is output first. Here, the FIFO 41 is composed of two memories, a first memory 44 and a second memory 45, for ease of explanation. The description will be made as follows.

First, a case in which the jitter of the transmission system clock is shifted forward from the normal position in time will be described with reference to FIG. FIG. 7A shows a reception system in which signals are transmitted from left to right. A transmission system clock having a frequency CL1 and an intra-office clock having a frequency CL0 are introduced into the FIFO 41 at the cell end. FIG.
(B) corresponds to time t2 in FIG.
In step S2 of FIG. 3A, data 1 for one cell length is written in the first memory 44, and in step S2, the next data is written to the next second memory 45. FIG.
In step S4 of (a), since the second memory 45 is not the memory that is reading, the data 2
Is written. When the writing of the data 2 for one cell length to the second memory 45 is completed again in step S2, the process proceeds to FIG.

FIG. 7C corresponds to the time t3 'in FIG. 7A, and the time t3' is shifted forward from the regular time t3. Therefore, time t2 and time t3 ′
And the clock interval becomes shorter between time t3 ′ and time t3 ′.
4, the clock interval is longer. Time t3 '
At the point in time, the writing of the data 2 to the second memory 45 has been completed because the time t3 ′ has shifted forward from the regular time t3,
The reading from has not been completed. Therefore, FIG.
When it is determined in step S4 that the data 3 is to be written to the first memory 44, the determination is YES because the reading of the data 1 from the first memory 44 has not been completed. Then, in step S5 of FIG. 3A, data 3 which is data for one cell length is discarded.

Next, FIG. 7D shows time t4 in FIG.
, And the reading of the data 2 stored in the second memory 45 is completed, and the step S in FIG.
Then, the process proceeds to step S7 in FIG. 3B, where it is determined whether the first memory 44 to be read next contains data of one cell length. In this determination, since the data 3 has been discarded at the above stage, the determination is NO, and an empty cell is transmitted in step S10 of FIG. 3B.

In step S4 of FIG. 3A in the writing process, the first memory 44 to which data 4 is next written is written.
It is determined whether or not is a memory from which data is being read. After the data is discarded, the data 4 is written to the first memory 44 because the position of the memory where the next data is written does not change.
At this stage, as described above, since the data is transmitted from the first memory 44 as an empty cell, the determination in step S4 is NO and the writing of the data 4 to the second memory 45 is continued.

As described above, by discarding the data and transmitting the empty cell, it is possible to eliminate the influence on the station side of the jitter caused by shifting the transmission system clock forward from the normal position in time. Next, a case where the jitter of the transmission system clock is shifted backward from the normal position in time will be described with reference to FIG. FIG. 8A shows a reception system in which signals are transmitted from left to right. The transmission clock of the frequency CL1 and the intra-station clock of the frequency CL0 are introduced into the FIFO 41 at the cell end. For example, in the transmission system clock CL1, the time t3 "is shifted backward with respect to the normal time t3, so that the interval between the time t2 and the time t3" becomes longer and the interval between the time t3 "and the time t4 becomes shorter.

FIG. 8 (b) corresponds to time t2 in FIG. 8 (a), and data 1 for one cell length is stored in the first memory 4 in step S2 of the flowchart in FIG. 3 (a).
4 and the process proceeds to writing the next data to the second memory 45 in step S2. In step S4 of FIG. 3A, the memory to be written is the second memory 45, and the memory to be read is the first memory 44, so that the determination is NO, and the data 2 is written to the second memory 45.

Next, FIG. 8 (c) shows the time t in FIG. 8 (a).
3 and data 1 from the first memory 44.
Is completed, the transmission of the data in step S8 in FIG. 3B ends, and the process proceeds to the next data read in step S9 in FIG. 3B. At this time, if the jitter of the transmission system clock is shifted backward from the normal position in time, and the time t3 ″ corresponding to the time t3 is delayed, the second memory 45 of the data 2 is used.
Writing to has not been completed. Therefore, at time t3 ″
8D corresponding to FIG. 8B, the determination in step S7 in FIG. 3B is determined to be NO, and the determination in step S7 in FIG.
10 sends an empty cell. At this point, writing of data 3 to the first memory 44 is started.

FIG. 8 (e) corresponds to time t4 in FIG. 8 (a). At this point, the writing of the data 3 into the first memory 44 ends, the reading of the empty cell from the second memory 45 ends, and the reading of the data 2 is performed next. The writing of the data 4 is performed on the second memory 45. However, since the reading of the data 2 is performed on the second memory 45 in the step S4, the data 4 for one cell is discarded in the step S5. In this way, it is possible to eliminate the influence on the station side of the jitter caused by the time lag of the transmission system clock from the normal position.

As described above, the stuff control for inserting and removing the stuff such as discarding the cell and transmitting the empty cell is executed to absorb the speed matching, the jitter and the wander. Next, the transmission system will be described with reference to FIG. The configuration of the transmission system is composed of a cell termination unit 4, a POH termination unit 3, a pointer termination unit 2, and a section termination unit 1 in order from the reception end to the transmission line, as described in the reception system. In the cell termination unit 4, the full cell stream is converted into C-4 by transmission format conversion or cell length conversion for converting between the container and the full cell stream. -4, and a pointer is added to this VC-4 in the pointer termination unit 2 to produce AU-4.
1 is transmitted to the transmission path.

The configuration and flow chart of the termination unit of the present invention described with reference to FIGS. 2 and 3 are the same for the transmission system although the direction of signal flow is reversed. Therefore, here, a different part of the transmission system from the reception system will be described. As described above, the function in the receiving system at the cell termination of the SDH interface circuit of the present invention is to remove jitter and wander caused by clock fluctuations that occur only in the receiving system. ,
This is to absorb the clock phase shift generated in the device.

Referring to FIG. 9, a description will be given of a function in a transmission system for absorbing a phase shift of a clock generated in the apparatus. The left side of the broken line in the figure is the transmission line side, and the right side is the device side. On the device side, for example, a clock source CLK of 150 MHz and L driven by this clock source CLK
There are SI1 and LSI2. LSI1 is clock source CL
K operates at the same frequency of 150 MHz, LSI2
Is a frequency 1 to process, for example, eight parallel data.
It operates at a frequency of 150/8 MHz obtained by dividing 50 MHz.

At this time, the frequency 15 of the clock source CLK
A phase shift occurs between the phase of the data transmitted from the LSI 2 at 0 MHz and the frequency of 150/8 MHz due to clock rotation in the device. Therefore, the function in the transmission system at the cell termination of the SDH interface circuit of the present invention is to absorb the clock phase shift occurring in the device unlike the reception system.

[0060]

As described above, according to the present invention,
A large amount of information in units of frames is performed by clock transfer and stuff control at a path termination unit provided in a conventional SDH interface circuit for speed matching and absorbing jitter, wander and frame phase difference. In addition, it is possible to provide an SDH interface circuit excellent in simplification of the memory capacity, the gate scale, and the hardware configuration by eliminating the disadvantage that the hardware configuration becomes complicated as the memory capacity and the gate scale increase.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an SDH interface circuit of the present invention.

FIG. 2 is a configuration diagram of a cell termination unit of the SDH interface circuit of the present invention.

FIG. 3 is a flowchart of a cell termination unit of the SDH interface circuit of the present invention.

FIG. 4 is a conceptual diagram for explaining a function of speed matching of a cell termination portion of the SDH interface circuit of the present invention.

FIG. 5 is a conceptual diagram for explaining a function of speed matching of a cell terminal of the SDH interface circuit of the present invention.

FIG. 6 is a conceptual diagram for explaining a function of speed matching of a cell terminal of the SDH interface circuit of the present invention.

FIG. 7 is a conceptual diagram for explaining the function of absorbing jitter, wander, and frame phase difference at the cell termination part of the SDH interface circuit of the present invention.

FIG. 8 is a conceptual diagram for explaining a function of absorbing a jitter, a wander, and a frame phase difference at a cell termination portion of the SDH interface circuit of the present invention.

FIG. 9 is a block diagram illustrating functions of a transmission system according to the present invention.

FIG. 10 is a block diagram of a conventional SDH interface circuit.

FIG. 11 is a block diagram of speed matching of a conventional SDH interface circuit.

FIG. 12 is a block diagram of a conventional pointer conversion circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Section termination part 2 Pointer termination part 3 POH termination part 4 Cell termination part 41 FIFO 42 Write control part 43 Read control part 44 1st memory 45 Second memory 100 Clock transfer part 101 Section termination part 102 Pointer termination part 103 POH termination Unit 104 cell termination unit 110 VC buffer 111 input control unit 112 stuff determination unit 113 output control unit

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-226831 (JP, A) JP-A-4-220829 (JP, A) JP-A-5-14393 (JP, A) JP-A-5-205 14325 (JP, A)

Claims (3)

(57) [Claims] (A) a cell termination unit for performing format conversion and cell length conversion; (b) means for introducing a transmission line clock and an intra-office clock to the cell termination unit; and (c) a frequency between the clocks. Means for performing matching; and (d) means for eliminating the phase shift of the clock, and (e) means for performing the frequency matching and means for eliminating the phase shift, provided in the cell termination unit . (F) Speed due to clock change at the cell end
Jitter, wander and
An SDH interface circuit for absorbing a frame phase difference . 2. The cell termination unit comprises: (a) a first-in first-out memory for inputting input data and outputting output data; and (b) introducing either the transmission line clock or the intra-station clock, and (C) introducing a clock, which is either the transmission line clock or the intra-office clock, which is different from the clock introduced into the write control unit, and consists of a read control section for controlling reading of the memory, (d) the write control unit, the line clock and the station
The cell is shifted by the frequency or phase shift of the clock.
Input data input to the termination and output data output
Discards data for one cell length when data mismatch
2. The SDH interface circuit according to claim 1, wherein: 3. SDH interface circuit <br/> claim 1, wherein the deviation of the phase is caused by the clock routing in station.