JP2018125568A - Semiconductor device and IO cell - Google Patents

Abstract

The conventional semiconductor device has a problem that the resistance value of the peripheral wiring cannot be sufficiently reduced. According to one embodiment, a semiconductor device and an IO cell are supplied with power of different voltages, and have a plurality of first power supply wirings 31 and a plurality of second power supplies arranged alternately in a first direction. The first power supply line 32 is formed in a wiring layer different from the wiring layer in which the first power supply line 31 and the second power supply line 32 are arranged, and is adjacent to the first power supply line 31. The first power supply wiring 31, the second power supply wiring 32, and the third power supply wiring 41, 51 are all connected to the wiring 31 through vias. It is formed so as to extend in a second direction orthogonal to the first direction. [Selection] Figure 9

Description

  The present invention relates to a semiconductor device and an IO cell, for example, a semiconductor device having IO cells arranged along the outer periphery of a chip and the IO cell.

  In a semiconductor integrated circuit (LSI: Large Scale Integration), it is necessary to provide power supply wiring in order to supply power to a transistor formed on a semiconductor substrate. Since a large amount of current flows through this power supply wiring, avoiding problems such as voltage drop (IRDrop) and electromigration that occur on the wiring due to this large current can improve the performance or reliability of the LSI. Is necessary for. Accordingly, Patent Documents 1 to 3 disclose examples of wiring methods for power supply wiring.

  Patent Document 1 discloses an example in which two power supply wirings are formed in a comb-teeth shape, arranged so that the comb tooth portions of the two power supply wirings are engaged, and the semiconductor chip is covered with the two power supply wirings. Patent Document 2 discloses an example in which power supply wirings are arranged in a ring shape along the outer periphery of a chip. In Patent Document 3, in a semiconductor device having a peripheral power supply wiring in which a power supply wiring to which a power supply voltage is supplied and a ground wiring to which a ground voltage is supplied are alternately arranged, the peripheral wiring is extended between the peripheral power supply wirings of the same potential. An example of connection by wiring orthogonal to the current direction is disclosed.

Japanese Patent No. 4275110 Japanese Patent Laid-Open No. 04-116850 JP 2010-219332 A

  2. Description of the Related Art In recent years, the scale of circuits mounted on LSIs has increased as semiconductor integrated circuits (LSIs: Large Scale Integration) have become more sophisticated and miniaturized. As the circuit scale increases, the amount of power supply wiring increases in order to supply sufficient power to the increased circuit. Further, as the circuit scale increases, the amount of signal wiring that connects each circuit also increases. Therefore, in recent LSIs, there is a problem that the increased signal wiring and power supply wiring cannot be arranged. Therefore, the amount of power supply wiring is reduced by reducing the power consumption of the circuit by circuit technology such as DVFS (Dynamic Voltage Frequency Scaling).

  However, in recent years, there is a tendency to reduce the number of wiring layers for the purpose of reducing the chip cost or improving the reliability of the LSI. For this reason, even if the power consumption is reduced, the resistance value of the power supply wiring cannot be made sufficiently small, and it has become difficult to arrange the power supply wiring and the signal wiring while avoiding problems such as IR Drop.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the semiconductor device and the IO cell are supplied with power of different voltages, and have a plurality of first power supply wirings and a plurality of second power supply wirings arranged alternately in the first direction; Formed in a wiring layer different from a wiring layer in which the first power supply wiring and the second power supply wiring are arranged, and is connected to the adjacent first power supply wiring among the plurality of first power supply wirings through vias. And the first power supply wiring, the second power supply wiring, and the third power supply wiring all extend in a second direction orthogonal to the first direction. It is formed.

  According to the one embodiment, it is possible to reduce the resistance value of the power supply wiring constituted by the first power supply wiring to the third power supply wiring.

1 is a schematic diagram of a layout of a semiconductor device according to a first embodiment; 2 is a schematic diagram of a layout of an IO cell according to the first embodiment; FIG. FIG. 3 is a schematic diagram of a layout of transistors in an IO logic formation region of the IO cell according to the first embodiment; FIG. 3 is a schematic diagram of a layout of a first global wiring layer of the IO cell according to the first exemplary embodiment; FIG. 3 is a schematic diagram of a layout of a second global wiring layer of the IO cell according to the first exemplary embodiment; FIG. 6 is a schematic diagram of a layout of a third global wiring layer of the IO cell according to the first embodiment; It is sectional drawing of the IO cell along the VII-VII line of FIG. It is sectional drawing of the IO cell along the VIII-VIII line of FIG. FIG. 6 is a perspective view showing a structure of power supply wiring from a first global wiring layer to a third global wiring layer of the IO cell according to the first exemplary embodiment; It is a perspective view which shows the structure of the power supply wiring and ground wiring of the semiconductor device concerning a comparative example. 3 is a table comparing the number of vias and the allowable current amount of vias in the IO cell according to the first embodiment and the IO cell of the semiconductor device according to the comparative example; 5 is a table showing the relationship between the number of wirings in the horizontal direction of the global wiring layer and the wiring resistance in the IO cell according to the first embodiment and the IO cell of the semiconductor device according to the comparative example. 5 is a table showing the relationship between the number of wirings in the vertical direction of the global wiring layer and the wiring resistance in the IO cell according to the first embodiment and the IO cell of the semiconductor device according to the comparative example. It is the table | surface which showed the relationship between the number of IO cells connected to circumference wiring, and the resistance value of power supply wiring in the semiconductor device concerning a comparative example. 4 is a table showing the relationship between the number of IO cells connected to a circuit wiring and the resistance value of a power supply wiring in the semiconductor device according to the first embodiment; It is the graph which compared the total resistance shown in FIG. 14, and the total resistance shown in FIG. 6 is a schematic diagram of a layout of a first global wiring layer of an IO cell according to a second embodiment; FIG. FIG. 6 is a schematic diagram of a layout of a second global wiring layer of an IO cell according to a second embodiment; FIG. 10 is a schematic diagram of a layout of a third global wiring layer of the IO cell according to the second embodiment; FIG. 20 is a cross-sectional view of the IO cell along the line XX-XX in FIG. 19. FIG. 20 is a cross-sectional view of the IO cell along the line XXI-XXI in FIG. 19. FIG. 10 is a schematic diagram of a layout of a first global wiring layer of an IO cell according to a third embodiment; FIG. 6 is a schematic diagram of a layout of a second global wiring layer of an IO cell according to a third embodiment; FIG. 10 is a schematic diagram of a layout of a third global wiring layer of the IO cell according to the third embodiment. FIG. 25 is a cross-sectional view of the IO cell along the line XXV-XXV in FIG. 24. FIG. 25 is a cross-sectional view of the IO cell along the line XXVI-XXVI in FIG. 24. FIG. 10 is a schematic diagram of a layout of a first global wiring layer and a second global wiring layer of an IO cell according to a fourth embodiment. FIG. 10 is a schematic diagram of an IO cell layout according to a fifth exemplary embodiment;

  For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Note that, in each drawing, the same element is denoted by the same reference numeral, and redundant description is omitted as necessary.

  First, FIG. 1 shows a schematic diagram of the layout of the semiconductor device 1 according to the first embodiment. The layout shown in FIG. 1 shows the layout of the entire semiconductor chip of the semiconductor device 1 according to the first embodiment. As shown in FIG. 1, in the semiconductor device 1 according to the first embodiment, the IO cells 10 are arranged so that the IO cells 10 are arranged along the outer periphery of the semiconductor chip. The IO cells 10 do not necessarily have to be arranged over the entire outer periphery of the semiconductor chip, and may be arranged separately according to the pad arrangement position.

  The IO cell 10 is provided with a pad 11. A circumferential wiring 12 is provided in a portion excluding the pad 11 of the IO cell 10. In addition, the semiconductor device 1 has an internal logic formation region 13 in a region surrounded by the IO cells 10.

  The circular wiring 12 includes, for example, a power supply wiring and a ground wiring. FIG. 1 shows an example in which the peripheral wiring 12 is provided so as to circulate the semiconductor chip along the outer periphery of the semiconductor chip. However, the peripheral wiring 12 is not necessarily formed so as to make one round of the semiconductor chip. You don't have to. For example, the circumferential wiring 12 only needs to extend in a direction around the semiconductor chip and may be separated in the middle. A power supply voltage or a ground voltage is supplied to the circumferential wiring 12 from a pad (not shown) or a power supply circuit.

  Next, details of the IO cell 10 according to the first exemplary embodiment will be described. FIG. 2 shows a schematic diagram of the layout of the IO cell 10 according to the first exemplary embodiment. As shown in FIG. 2, the IO cell 10 has a pad 11 and an IO logic formation region 14. In the IO cell 10 according to the first embodiment, the pads 11 and the IO logic formation region 14 are arranged so as not to overlap. In the IO logic formation region 14, a circuit constituting a buffer circuit or the like is formed. In the example shown in FIG. 12, the transistor is not shown by the wiring layer formed in the upper layer of the transistor constituting the circuit. In addition, as shown in FIG. 2, in the IO logic formation region 14, a circumferential power supply wiring 12v and a circumferential ground wiring 12g are formed. The circumferential power supply wiring 12v and the circumferential ground wiring 12g describe the circumferential wiring 12 of FIG. 1 in more detail. In FIG. 2, only the wiring formed in the uppermost wiring layer is shown.

  The semiconductor device 1 according to the first embodiment has one feature in the wiring method of the peripheral power supply wiring 12v and the peripheral ground wiring 12g in the IO cell 10. The peripheral power supply wiring 12v and the peripheral ground wiring 12g are formed so as to be continuous with the peripheral power supply wiring 12v and the peripheral ground wiring 12g of other IO cells 10 arranged at adjacent positions. In the following description, the circumferential power supply wiring 12v and the circumferential ground wiring 12g are referred to as global wiring, and are distinguished from local wiring that connects circuit elements such as transistors in the IO logic formation region 14. Hereinafter, the wiring structure of the global wiring of the IO cell 10 will be described in more detail.

  In the following description, a direction orthogonal to the outer periphery of the semiconductor chip is a first direction (for example, Y direction), a direction parallel to the outer periphery of the semiconductor chip is a second direction (for example, X direction), and the semiconductor The description will be made assuming that the thickness direction of the chip is the third direction (for example, the Z direction). In addition, the first direction and the second direction indicate directions orthogonal to each other.

  FIG. 3 shows a schematic diagram of a transistor layout in the IO logic formation region 14 of the IO cell according to the first embodiment. The example shown in FIG. 3 shows a part of the IO logic formation region 14, and transistors are provided in the IO logic formation region 14 in the layout structure shown in FIG. As shown in FIG. 3, in the IO cell 10 according to the first embodiment, the N-type well regions 20 and the P-type well regions 23 are alternately arranged in the Y direction. A P-type diffusion region 21 is formed in the N-type well region 20, and an N-type diffusion region 24 is formed in the P-type well region 23. The P-type diffusion region 21 and the N-type diffusion region 24 constitute the source or drain of the transistor. Further, the gate electrode 26 is formed so as to straddle two diffusion regions arranged in the vertical direction of the drawing and to divide each diffusion region. That is, a PMOS transistor is formed in the N-type well region 20, and an NMOS transistor is formed in the P-type well region 23. A well contact wiring 27 and a well contact 28 are formed on the N-type well region 20 and the P-type well region 23, and power is supplied to the well via the well contact wiring 27 and the well contact 28.

  In the example shown in FIG. 3, in the IO cell 10 according to the first embodiment, there are four transistor columns in which transistors are arranged in the Y direction, and an inverter row in which inverters composed of NMOS transistors and PMOS transistors are arranged in the X direction. There are 3 lines. The number of transistor columns and the number of inverter rows can be appropriately set according to the capability of the IO cell 10. In the example shown in FIG. 3, a layout is shown in which PMOS transistors and NMOS transistors are arranged along the boundary line between the N-type well region 20 and the P-type well region 23. With such a layout, the arrangement area of the gate electrode 26 can be suppressed when an inverter is configured with transistors. Note that the inverter is one of the components of the buffer circuit.

  Further, as shown in FIG. 3, a contact 22 is disposed on the P-type diffusion region 21, and a contact 25 is disposed on the N-type diffusion region 24. Each diffusion region is connected to a local wiring or the like formed in an upper layer by a contact. In addition, not only the contact but also a wiring structure including a via can be used for connection between each diffusion region and the local wiring.

  In the IO cell 10 according to the first exemplary embodiment, the first local wiring layer, the second local wiring layer, the first global wiring layer, the first global wiring layer, and the first global wiring layer are arranged in the Z direction from the wiring closest to the semiconductor substrate on which the transistor is formed. 2 global wiring layers and a third global wiring layer. That is, the IO cell 10 according to the first exemplary embodiment is formed with wiring by five wiring layers. Here, since the first local wiring and the second local wiring are wiring layers for connecting the transistors in the IO cell 10, description thereof is omitted here. On the other hand, the wiring structure in the global wiring layer constituted by the first global wiring layer, the second global wiring layer, and the third global wiring layer is one of the features of the semiconductor device 1 according to the first embodiment. Therefore, the global wiring layer will be described in more detail below.

  The semiconductor device 1 according to the first embodiment relates to a plurality of first power supply lines to which a first power is supplied and a plurality of second power to which a second power is supplied with respect to the global wiring layer on the IO cell 10. A first wiring layer in which power supply wirings are alternately arranged in a first direction (for example, the Y direction), a first power supply, and a first power supply that is adjacent among the plurality of first power supply wirings. And a second wiring layer in which a third power supply wiring connected by the wiring and the via is disposed. In the semiconductor device 1 according to the first embodiment, the first power supply wiring, the second power supply wiring, and the third power supply wiring are all in a second direction (for example, X Direction). In the semiconductor device 1 according to the first embodiment, the second power is supplied to the second wiring layer, and is connected to the adjacent second power wiring among the plurality of second power wirings by vias. A fourth power supply wiring is arranged.

  Here, in the semiconductor device 1 according to the first embodiment, the first wiring layer is configured by the first global wiring layer, and the second wiring layer is formed by the second global wiring layer and the third global wiring layer. Configure. Further, it is assumed that the power supply voltage is supplied from the first power supply and the ground voltage is supplied from the second power supply.

  The global wiring will be described in detail by showing a layout for each global wiring layer. First, FIG. 4 shows a schematic diagram of the layout of the first global wiring layer of the IO cell 10 according to the first exemplary embodiment.

  As shown in FIG. 4, in the IO cell 10 according to the first embodiment, the first global wiring layer includes a first power supply wiring (for example, the first layer power supply wiring 31) and a second power supply wiring (first One layer ground wiring 32) is arranged. A power supply voltage is supplied to the first layer power supply wiring 31, and a ground voltage is supplied to the first layer ground wiring 32. The first layer power supply wiring 31 is connected to the source of the PMOS transistor shown in FIG. The first layer ground wiring 32 is connected to the source of the NMOS transistor shown in FIG. Note that the first-layer power supply wiring 31 and the first-layer ground wiring 32 and the transistor are electrically connected by a stack via including the via 30 or a wiring structure including the local wiring layer and another via.

  The first layer power supply wiring 31 and the first layer ground wiring 32 are wirings formed to extend in a direction parallel to the X direction. The first layer power supply wiring 31 is disposed so as to mainly cover the upper layer of the N-type well region 20, and the first layer ground wiring 32 is disposed so as to mainly cover the upper layer of the P-type well region 23. If the side parallel to the X direction is the side surface of the first layer power supply wiring 31 and the first layer ground wiring 32, the first layer power supply wiring 31 and the first layer ground wiring 32 are uneven along at least one side surface. Have Further, as shown in FIG. 4, the convex portion of the first layer power supply wiring 31 and the concave portion of the first layer ground wiring 32 are formed so as to mesh with each other. That is, the first layer power supply wiring 31 and the first layer ground wiring 32 are arranged so that the concavo-convex portions of each other mesh with each other.

  Further, as shown in FIG. 4, the tip of the convex portion of the first layer power supply wiring 31 is located above the P type well region 23 adjacent to the N type well region 20 formed below the first layer power supply wiring 31. It is formed. Further, the tip of the convex portion of the first layer ground wiring 32 is formed so as to be located above the N type well region 20 adjacent to the P type well region 23 formed below the first layer ground wiring 32. . That is, the tips of the convex portions of the first layer power supply wiring 31 and the first layer ground wiring 32 are formed at positions that extend beyond the Z-direction extension of the boundary line between the N-type well region 20 and the P-type well region 23. The

  In another aspect, the first layer power supply wiring 31 and the first layer ground wiring 32 have a shape in which the wiring protrudes in a comb shape on the side surface, and the comb teeth of the first layer power supply wiring 31 and the first layer It is formed so that the comb teeth of the ground wiring 32 are engaged with each other.

  Next, FIG. 5 shows a schematic diagram of the layout of the second global wiring layer of the IO cell according to the first embodiment. As shown in FIG. 5, the second layer power wiring 41 and the second layer ground wiring 42 are arranged in the second global wiring layer. The first power is supplied to the second layer power wiring 41, and the second power is supplied to the second layer ground wiring. In the example shown in FIG. 5, the second-layer power supply wiring 41 and the second-layer ground wiring 42 are each formed so that two wirings form one wiring pair. Although details will be described later, in the semiconductor device 1 according to the first embodiment, in the second global wiring layer, the second layer power supply wiring 41 arranged as one wiring pair is formed in the third global wiring layer. One third power supply wiring is formed by connecting with wiring. Also for the second layer ground wiring 42, the second layer ground wiring 42 arranged as one wiring pair is connected by wiring formed in the third global wiring layer to form one fourth power supply wiring. That is, in FIG. 5, a wiring pair formed by two wirings can be regarded as one wiring. Also, as shown in FIG. 5, in the second global wiring layer, wiring pairs to which different voltages are supplied are alternately arranged in the Y direction.

  As shown in FIG. 5, the second layer power supply wiring 41 is connected to the adjacent first layer power supply wiring 31 in the first global wiring layer through the via 40. The second layer ground wiring 42 is connected via the via 40 to the adjacent first layer ground wiring 32 in the first global wiring layer. Here, in the semiconductor device 1 according to the first embodiment, the via 40 that connects the wiring formed in the first global wiring layer and the wiring formed in the second global wiring layer has the first layer. The power supply wiring 31 and the first layer ground wiring 32 are arranged near the tips of the convex portions.

  FIG. 6 is a schematic diagram showing the layout of the third global wiring layer of the IO cell according to the first embodiment. As shown in FIG. 6, a third layer power supply wiring 51 and a third layer ground wiring 52 are arranged in the third global wiring layer. The first power is supplied to the third layer power wiring 51, and the second power is supplied to the third layer ground wiring 52. In the example shown in FIG. 6, the third-layer power supply wiring 51 and the third-layer ground wiring 52 are each formed so that two wirings form one wiring pair. The third-layer power supply wiring 51 is connected to the second-layer power supply wiring 41 through the vias 50 in the two wirings constituting the wiring pair. That is, the second layer power supply line 41 and the third layer power supply line 51 are lines supplied with the same voltage, and function as one third power supply line. The third-layer ground wiring 52 is connected to the second-layer electrical grounding line 42 via the vias 50 in the two wirings constituting the wiring pair. That is, the second layer ground wiring 42 and the third layer ground wiring 52 are lines to which the same voltage is supplied, and function as one fourth power supply wiring. That is, in FIG. 6, a wiring pair formed by two wirings can be regarded as one wiring. Also, as shown in FIG. 5, in the third global wiring layer, wiring pairs to which different voltages are supplied are alternately arranged in the Y direction.

  Here, it is desirable to arrange as many vias 50 as possible to connect the wiring formed in the second global wiring layer and the wiring formed in the third global wiring layer. This is because the resistance values of the third power supply wiring and the fourth power supply wiring can be reduced by arranging as many vias 50 as possible.

  Subsequently, a cross-sectional structure around the global wiring layer of the semiconductor device 1 according to the first embodiment will be described. In the description of the cross-sectional structure centering on the global wiring layer described below, the description of the wiring formed in the local wiring layers such as the well contact wiring 27 and the well contact 28 is omitted. FIG. 7 shows a cross-sectional view of the IO cell along the line VII-VII in FIG. As shown in FIG. 7, in the semiconductor device 1 according to the first embodiment, the N-type well region 20 and the P-type well region 23 are formed in the upper layer of the semiconductor substrate SUB. Then, a P-type diffusion region 21 is formed in the N-type well region 20, and an N-type diffusion region 24 is formed in the P-type well region 23. The N type diffusion region 24 is connected to the first layer ground wiring 32 through a wiring structure including the contact 25 and the via 30. The P-type diffusion region 21 is connected to the first layer power supply wiring 31 through a wiring structure including the contact 22 and the via 30.

  As shown in FIG. 7, in the first global wiring layer in the cross section along the line VII-VII, the first layer power supply wiring 31 has a wiring width (wiring in the Y direction) than the first layer ground wiring 32. (Width) is formed wide. In the second global wiring layer in the cross section along the line VII-VII, a wiring pair constituted by the second layer power supply wiring 41 is formed above the first layer ground wiring 32, and the second layer ground wiring 42. A wiring pair formed by the above is formed above the first layer power supply wiring 31. Further, the total wiring width of the wiring pair constituted by the second layer power supply wiring 41 and the total wiring width of the wiring pair constituted by the second layer ground wiring 42 are formed to be substantially equal.

  Then, as shown in FIG. 7, the two wirings constituting the wiring pair in the second global wiring layer are connected by a wiring that is formed in the third global wiring layer and supplied with the same voltage. More specifically, the two second layer power wirings 41 are connected by a third layer power wiring 51, and the two second layer ground wirings 42 are connected by a third layer ground wiring 52.

  FIG. 8 shows a cross-sectional view of the IO cell along the line VIII-VIII in FIG. As shown in FIG. 8, the structure of the transistor formed over the semiconductor substrate SUB is the same in the cross section along the line VIII-VIII, and thus the description thereof is omitted here.

  As shown in FIG. 8, in the first global wiring layer in the section along the line VIII-VIII, the first layer ground wiring 32 is wider than the first layer power supply wiring 31 (wiring width in the Y direction). Is widely formed. Further, in the second global wiring layer in the cross section along the line VIII-VIII, a wiring pair constituted by the second layer power supply wiring 41 is formed above the first layer ground wiring 32, and the second layer ground wiring 42. A wiring pair formed by the above is formed above the first layer power supply wiring 31. Further, the total wiring width of the wiring pair constituted by the second layer power supply wiring 41 and the total wiring width of the wiring pair constituted by the second layer ground wiring 42 are formed to be substantially equal.

  Then, as shown in FIG. 8, the two wirings constituting the wiring pair in the second global wiring layer are connected by a wiring that is formed in the third global wiring layer and is supplied with the same voltage. More specifically, the two second layer power wirings 41 are connected by a third layer power wiring 51, and the two second layer ground wirings 42 are connected by a third layer ground wiring 52.

  As shown in FIGS. 7 and 8, in the semiconductor device 1 according to the first embodiment, in the global wiring layer, the wiring to which power of different voltages is supplied is arranged in the vertical direction of the semiconductor chip (for example, (Z direction).

  In order to explain the wiring structure in more detail, FIG. 9 is a perspective view showing the structure of the power supply wiring from the first global wiring layer to the third global wiring layer of the IO cell according to the first embodiment. As shown in FIG. 9, in the semiconductor device according to the first embodiment, all the wirings formed from the first global wiring to the third global wiring are formed to extend in the second direction. The first-layer power supply wiring 31 of the same potential adjacent in the vertical direction (Y direction) in the first global wiring layer is a second-layer power supply formed in the second global wiring layer and the third global wiring layer. The wiring 41 and the third layer power wiring 51 are connected. In addition, wirings formed in different wiring layers are connected by vias 40 and 50.

  From the above description, in the semiconductor device 1 according to the first embodiment, all the power supply lines for supplying power to the IO cells 10 are formed so as to extend in the X direction parallel to the outer periphery of the semiconductor chip. Adjacent wires are connected to each other with a wire to which is given. As a result, in the semiconductor device 1 according to the first embodiment, it is possible to reduce the resistance value of the peripheral wiring by increasing the parallel number of the power supply wiring and the ground wiring arranged so as to go around the semiconductor chip.

  Hereinafter, the effect of reducing the resistance value of the surrounding wiring will be described in more detail. FIG. 10 is a perspective view showing the structure of the power supply wiring and the ground wiring of the semiconductor device 100 according to the comparative example. As illustrated in FIG. 10, the semiconductor device 100 according to the comparative example includes a first power supply wiring 111 </ b> A and a second power supply wiring 111 </ b> B that extend in the circumferential direction (for example, the X direction) of the semiconductor chip. The first power supply wiring 111A and the second power supply wiring 111B are alternately arranged in the Y direction orthogonal to the X direction. In the semiconductor device 100, the first power supply wiring 111A formed at different positions is connected by the first power supply wiring 112A. Further, in the semiconductor device 100, the second power supply wiring 111B formed at different positions is connected by the second power supply wiring 112B. Note that the first power supply wiring 111A and the first power supply wiring 112A are connected by a wiring structure including a via 121A and a connection wiring 122A. Further, the second power supply wiring 111B and the second power supply wiring 112B are connected by a wiring structure constituted by the via 121B and the connection wiring 122B.

  As described above, the semiconductor device 100 according to the comparative example connects the power supply wirings arranged apart in the same wiring layer by providing the wiring extending in the direction orthogonal to the different wiring layers. Therefore, the semiconductor device 100 according to the comparative example has a problem that the number of parallel power supply wirings is smaller than that of the semiconductor device 1 according to the first embodiment, and the wiring resistance cannot be reduced.

Subsequently, the wiring resistance in the semiconductor device 1 according to the first embodiment and the wiring resistance in the semiconductor device 100 according to the comparative example are compared numerically. Therefore, first, the condition for calculating the resistance value of the power supply wiring is defined as follows. In this study, the first power supply wiring 111A and the second power supply wiring 111B of the semiconductor device according to the comparative example are arranged so as to extend in the X direction, and the first power supply wiring 112A and the second power supply wiring are arranged. 112B is arranged to extend in the Y direction.
IO cell width (X-direction width): 50 [μm]
Height of IO logic formation region 14 (Y-direction width): 100 [μm]
Height allocated to power supply wiring (width in Y direction): 50 [μm]
Height (width in Y direction) allocated to ground wiring: 50 [μm]
Area of IO logic formation region 14: 2500 [μm ² ]
Operating current of IO logic formation region 14: 50 [μA]
Wiring width in the Y direction per wiring of the first global wiring layer: 1.0 [μm]
Wiring interval in the Y direction of the wiring of the first global wiring layer: 2.0 [μm]
Wiring width in the Y direction per wiring in the second and third global wiring layers: 1.0 [μm]
Wiring interval in the Y direction between the wirings of the second and third global wiring layers: 0.5 [μm]
Sheet resistance of global wiring layer wiring: 0.5 [Ω / □]
Current tolerance per via: 100 [μA]
Via size: 0.1 [μm / □]
Via resistance value: 15 [Ω]
Wiring width in the X direction of the wiring of the first global wiring layer: 1.0 [μm]
Wiring interval in the X direction of the wiring of the first global wiring layer: 2.0 [μm]
Number of vias 40 per one convex portion of the wiring of the first global wiring layer: 2 [pieces]
Number of vias 40 that can be arranged per convex portion of wiring in the first global wiring layer: 2 [pieces]
Length in the Y direction per one convex portion of the wiring of the first global wiring layer: 4.0 [μm]
Arrangement interval of vias 50 between the second and third global wiring layers: 0.1 [μm]

First, let us consider the current allowable amount of the circulating power supply wiring under the above conditions. From the above conditions, the current density per IO cell can be derived from equation (1).
Current density = Operating current in the IO logic formation region 14 / Area of the IO logic formation region 14 = 50 [μA] / 2500 [μm ² ]
= 0.02 [μA / μm ² ] (1)
Next, an allowable area S per via is calculated based on the equation (2).
Allowable area S = allowable current value per via / current density of IO logic forming region 14
= 100 [μA] /0.02 [μA / μm ² ]
= 5000 [μm ² ]

In the IO cell 10, the number of vias 40 connecting the first global wiring layer and the second global wiring layer is the smallest. Therefore, the number of vias 40 in the IO cell 10 is calculated. First, consider the number of vias in the height direction (Y direction) of the IO cell. From the above conditions, the number of wirings in the first global wiring layer that can be arranged in the height direction of the IO logic formation region 14 can be derived from the equation (3).
Number of wirings in the first global wiring layer = 50 [μm] / (1.0 [μm] +2.0 [μm])
= 16.6667 (3)
Here, since the number of wirings is always an integer, the number of wirings in the first global wiring layer is 16 from equation (3). The 16 wirings are each provided with vias 40 along both side surfaces. Therefore, 16 vias 40 are arranged in the Y direction in the IO logic formation region 14.

Next, the number of vias in the width direction (X direction) of the IO logic formation region 14 will be considered. From the above conditions, the number of convex portions that can be arranged in the width direction of the IO logic formation region 14 can be derived from the equation (4).
Number of convex portions that can be arranged in the width direction = 50 [μm] / (1.0 [μm] +2.0 [μm])
= 16.6667 (4)
Here, since the number of convex portions is always an integer, the number of convex portions that can be arranged in the width direction from Equation (4) is 16. Then, two vias 40 are arranged on each of the 16 convex portions. Therefore, 32 vias 40 are arranged in the X direction in the IO logic formation region 14.

  From the above calculation, it is understood that 16 [numbers] × 32 [numbers] = 512 [numbers] of vias 40 are arranged in the IO logic formation region 14. Similar to the above calculation, when the number of vias 40 in the IO logic formation region provided in the IO cell of the semiconductor device 100 according to the comparative example is calculated, 4096 per IO logic formation region in the semiconductor device 100 according to the comparative example. The via 40 is provided.

  From the above conditions, since the allowable current per via is 100 μA, the amount of current that can be supplied to one IO logic formation region is calculated from the product of the number of vias and the allowable current. A table summarizing the calculation results is shown in FIG. As shown in FIG. 11, the IO logic formation region 14 according to the first embodiment has 51.2 mA, and the IO logic formation region of the semiconductor device 100 according to the comparative example has 409.6 mA. On the other hand, the operating current of the IO logic formation region 14 under the above conditions is 50 [μA]. That is, the semiconductor device 1 according to the first embodiment has a sufficient current allowable amount although the amount of current that can be passed through the IO logic formation region 14 is smaller than that of the semiconductor device 100 according to the comparative example. I understand.

  Next, the wiring resistance of the global wiring of the semiconductor device 1 according to the first embodiment and the semiconductor device 100 according to the comparative example will be considered. First, consider the wiring resistance in the X direction. The wiring resistance in the X direction depends on the number of wirings arranged in the Y direction in each global wiring layer. That is, the wiring resistance in the X direction may be a parallel resistance of wiring extending in the X direction. FIG. 12 is a table showing the relationship between the number of wirings in the lateral direction (X direction) of the global wiring layer and the wiring resistance in the IO cell according to the first embodiment and the IO cell of the semiconductor device according to the comparative example. As shown in FIG. 12, in the semiconductor device 100 according to the comparative example, wiring extending in the X direction is provided only in the second global wiring layer and the third global wiring layer. Here, in the IO logic formation region of the semiconductor device 100 according to the comparative example, 16 wirings are provided in each wiring layer as calculated from the equation (3). On the other hand, in the semiconductor device 1 according to the first embodiment, eight wires extend in the X direction in the first global wiring layer, and extend in the X direction in the second global wiring layer and the third global wiring layer. Sixteen wirings to be arranged are arranged. Therefore, the wiring resistance in the X direction is smaller in the semiconductor device 1 according to the first embodiment having a larger number of wirings.

  Next, FIG. 13 is a table showing the relationship between the number of wirings in the vertical direction (Y direction) of the global wiring layer and the wiring resistance in the IO cell according to the first embodiment and the IO cell of the semiconductor device according to the comparative example. As shown in FIG. 13, in the semiconductor device 100 according to the comparative example, a wiring extending in the Y direction is provided only in the first global wiring layer. Here, in the IO logic formation region of the semiconductor device 100 according to the comparative example, 16 wires are provided in the first global wiring layer as calculated from the equation (3). On the other hand, in the semiconductor device 1 according to the first embodiment, 16 wires extending in the X direction are arranged in the first global wiring layer. Further, in the semiconductor device 1 according to the first embodiment, the number of vias arranged in the first via layer between the first global wiring layer and the second global wiring layer is two, and the second global 250 vias are arranged in the second via layer between the wiring layer and the third global wiring layer.

Here, the number of vias in the second via layer is calculated based on equation (5).
Number of vias in second via layer = IO cell width / (via size + via arrangement interval)
= 50 [μm] / (0.1 [μm] +0.1 [μm])
= 250 [pieces] (5)

  And since the semiconductor device 1 concerning Embodiment 1 requires many vias for the connection of the wiring of the same voltage adjacent, it becomes wiring resistance higher than the semiconductor device 100 concerning a comparative example. In the example shown in FIG. 13, the wiring resistance in the Y direction of the semiconductor device 1 according to the first embodiment is about 6.6 times larger than the wiring resistance in the Y direction of the semiconductor device 100 according to the comparative example. .

  From the above examination, the semiconductor device 1 according to the first embodiment can increase the parallel number in the X direction in which the circular wiring extends, and thus the wiring resistance in the X direction is smaller than that of the semiconductor device 100 according to the comparative example. it can. On the other hand, since the semiconductor device 1 according to the first embodiment does not have the wiring extending in the Y direction, the wiring resistance in the Y direction is higher than that of the semiconductor device 100 according to the comparative example.

  However, in recent semiconductor devices, the number of IO cells 10 mounted on one semiconductor chip is increasing. That is, in recent semiconductor devices, the number of IO cells connected to one circuit line is increasing. From the above examination, in the IO cell 10 according to the first embodiment, the wiring resistance in the X direction is small and the wiring resistance in the Y direction is large. When the number of IO cells 10 arranged is increased, the distance between the peripheral wirings increases, so that the wiring resistance in the X direction increases and the wiring resistance in the Y direction tends to decrease due to the increase in the number of parallel connections.

  Therefore, in the following, the wiring resistance with respect to the number of IO cells 10 arranged will be examined. FIG. 14 shows a table showing the relationship between the number of IO cells connected to the peripheral wiring and the resistance value of the power supply wiring in the semiconductor device according to the comparative example, and FIG. 15 shows the peripheral circuit in the semiconductor device according to the first embodiment. The table | surface which showed the relationship between the number of IO cells connected to wiring, and the resistance value of power supply wiring is shown.

  As shown in FIG. 14, in the semiconductor device 100 according to the comparative example, when the number of IO cells connected to the peripheral wiring increases, the wiring resistance in the X direction monotonously increases and the wiring resistance in the Y direction monotonously decreases. . In the semiconductor device 100 according to the comparative example, the total resistance of the wiring resistance in the X direction and the wiring resistance in the Y direction increases monotonously. This is because the amount of decrease in the wiring resistance in the Y direction is always less than the amount of increase in the wiring resistance in the X direction.

  On the other hand, as shown in FIG. 15, in the semiconductor device 1 according to the first embodiment, when the number of IO cells connected to the peripheral wiring increases, the wiring resistance in the X direction monotonously increases and the wiring resistance in the Y direction monotonously. Decrease. In the semiconductor device 1 according to the first embodiment, the total resistance of the wiring resistance in the X direction and the wiring resistance in the Y direction is monotonously decreased until the number of IO cells connected to the circumferential wiring is four. When the number of IO cells connected to is 5 or more, it increases monotonously. This is because the amount of decrease in the wiring resistance in the Y direction exceeds the amount of increase in the wiring resistance in the X direction when the number of parallel IO cells 10 is four.

  FIG. 16 shows a graph comparing the total resistance shown in FIG. 14 with the total resistance shown in FIG. As shown in FIG. 16, the semiconductor device 1 according to the first embodiment has a higher resistance value than the semiconductor device 100 according to the comparative example when the total resistance has a small number of IO cells 10 in parallel. When the number is eight or more, the total resistance of the semiconductor device 1 according to the first embodiment is lower than the total resistance of the semiconductor device 100 according to the comparative example. This is because the increase rate of the total resistance of the semiconductor device 1 according to the first embodiment is smaller than the increase rate of the total resistance of the semiconductor device 100 according to the comparative example. When the number of IO cells 10 in parallel reaches 20, the total resistance of the semiconductor device 1 according to the first embodiment is about 20% smaller than the total resistance of the semiconductor device 100 according to the comparative example.

  From the above description, in the semiconductor device 1 according to the first embodiment, the effect of suppressing the resistance value of the peripheral wiring increases as the number of IO cells 10 connected to one peripheral wiring increases. Then, by suppressing the resistance value of the surrounding wiring, the semiconductor device 1 according to the first embodiment can avoid problems such as IRDrop that occur in the surrounding wiring. In addition, as described above, in the semiconductor device 1 according to the first embodiment, by not providing the power supply wiring in the Y direction, the wiring resistance in the X direction is suppressed while suppressing the number of wiring layers, and one circuit wiring is provided. It is possible to suppress an increase in wiring resistance when the number of IO cells 10 connected to is increased. That is, in the semiconductor device 1 according to the first embodiment, the effect of suppressing the wiring resistance increases as the number of the IO cells 10 connected to one peripheral wiring increases.

  In addition, by suppressing the resistance value of the peripheral wiring, it is possible to suppress the driving capability of the power supply circuit that supplies power to the peripheral wiring, and it is possible to reduce the area of the semiconductor chip. From another viewpoint, the semiconductor device 1 according to the first embodiment can increase the number of IO cells 10 connected to one power supply circuit while maintaining a constant IRDrop. Thus, by increasing the number of IO cells 10 connected to one power supply circuit, the number of power supply circuits can be reduced and the area of the semiconductor chip can be reduced.

  Further, in recent semiconductor devices, the number of IO cells 10 is almost 20 or more, and the effect of reducing the wiring resistance by the IO cells 10 according to the first embodiment is very large. Further, in recent semiconductor devices, it is required to suppress the number of wiring layers in order to improve the reliability of the semiconductor device, and the first embodiment can suppress the wiring resistance even with a small number of wiring layers. The effect of using the IO cell 10 is high.

Embodiment 2
In the second embodiment, another form of the shape of the wiring formed from the first global wiring to the third global wiring will be described. More specifically, in the second embodiment, an example in which unevenness is formed on the side surface of the third power supply wiring formed in the second global wiring layer will be described. Therefore, also in the semiconductor device according to the second embodiment, the transistor has the layout shown in FIG. An IO cell having a global wiring structure according to the second embodiment is hereinafter referred to as an IO cell 60.

  The layout for each global wiring layer of the semiconductor device according to the second embodiment is shown in FIGS. FIG. 17 shows a schematic diagram of the layout of the first global wiring layer of the IO cell 60 according to the second exemplary embodiment.

  As shown in FIG. 17, in the IO cell 60 according to the second embodiment, the first global wiring layer includes the first power supply wiring (for example, the first layer power supply wiring 62) and the second power supply wiring (first power supply wiring). A first layer ground wiring 63) is arranged. That is, the power supply voltage is supplied to the first layer power supply wiring 62, and the ground voltage is supplied to the first layer ground wiring 63. The first layer power supply wiring 62 is connected to the source of the PMOS transistor shown in FIG. The first layer ground wiring 63 is connected to the source of the NMOS transistor shown in FIG. Note that the first layer power supply wiring 62 and the first layer ground wiring 63 and the transistor are electrically connected by a stack via including the via 61 or a wiring structure including the local wiring layer and another via.

  The first layer power supply wiring 62 and the first layer ground wiring 63 are wirings formed so as to extend in a direction parallel to the X direction. The first layer power supply wiring 62 is mainly disposed in the upper layer of the N-type well region 20, and the first layer ground wiring 63 is mainly disposed in the upper layer of the P-type well region 23. In the second embodiment, the first layer power supply wiring 62 and the first layer ground wiring 63 have a shape that does not have irregularities on the side surfaces.

  Next, FIG. 18 shows a schematic diagram of the layout of the second global wiring layer of the IO cell 60 according to the second exemplary embodiment. As shown in FIG. 18, a second layer power supply wiring 65 and a second layer ground wiring 66 are arranged in the second global wiring layer. A first power supply is supplied to the second layer power supply wiring 65, and a second power supply is supplied to the second layer ground wiring 66. As shown in FIG. 18, in the second global wiring layer, the second layer power supply wiring 65 and the second layer ground wiring 66 are alternately arranged in the Y direction.

  As shown in FIG. 18, each of the second layer power supply wiring 65 and the second layer ground wiring 66 has irregularities on at least one side surface. The convex portion of the second layer power supply wiring 65 and the concave portion of the second layer ground wiring 66 are formed so as to mesh with each other. That is, the second layer power supply wiring 65 and the second layer ground wiring 66 are arranged so that their concavo-convex portions are engaged with each other.

  As shown in FIG. 18, the second layer power wiring 65 is formed in an upper layer of the first layer ground wiring 63 formed below the second layer power wiring 65. The tip of the convex portion of the second layer power supply wiring 65 is formed so as to be located above the adjacent first layer power supply wiring 62 in the first global wiring layer. The second layer power supply wiring 65 is connected to the adjacent first layer power supply wiring 62 in the first global wiring layer by a via 64 provided near the tip of the convex portion. That is, the second layer power supply wiring 65 corresponds to a third power supply wiring that connects two power supply wirings formed in another global wiring layer.

  As shown in FIG. 18, the second layer ground wiring 66 is formed in an upper layer of the first layer power wiring 62 formed below the second layer ground wiring 66. The tip of the convex portion of the second layer ground wiring 66 is formed so as to be located in the upper layer of the first layer ground wiring 63 adjacent in the first global wiring layer. The second layer ground wiring 66 is connected to the adjacent first layer ground wiring 63 in the first global wiring layer by a via 64 provided near the tip of the convex portion. That is, the second layer power wiring 65 corresponds to a fourth power wiring that connects two power wirings formed in another global wiring layer.

  In the second embodiment, the third power supply wiring and the fourth power supply wiring that connect wirings formed in other global wiring layers can be formed by wirings formed in one global wiring layer. That is, the tips of the convex portions of the second layer power supply wiring 65 and the second layer ground wiring 66 are formed at positions that extend beyond the Z-direction extension of the boundary line between the N-type well region 20 and the P-type well region 23. The

  Next, FIG. 19 shows a schematic diagram of the layout of the third global wiring layer of the IO cell 60 according to the second exemplary embodiment. As shown in FIG. 19, a third layer power supply wiring 68 and a third layer ground wiring 69 are arranged in the third global wiring layer. The first power supply is supplied to the third layer power supply wiring 68, and the second power supply is supplied to the third layer ground wiring 69. In the example shown in FIG. 19, the third-layer power supply wiring 68 and the third-layer ground wiring 69 are formed so that each of the two wirings forms one wiring pair. The third-layer power supply wiring 68 is connected to the second-layer power supply wiring 65 through vias 67, respectively, in the two wirings constituting the wiring pair. The third layer ground wiring 69 is connected to the second layer electrical ground line 66 through two vias 67 in the two wirings constituting the wiring pair. In FIG. 19, a wiring pair formed by two wirings can be regarded as one wiring. Further, as shown in FIG. 19, in the third global wiring layer, wiring pairs to which different voltages are supplied are alternately arranged in the Y direction.

  Here, it is desirable to arrange as many vias 67 as possible to connect the wirings formed in the second global wiring layer and the wirings formed in the third global wiring layer. This is because the resistance values of the third power supply wiring and the fourth power supply wiring can be reduced by arranging as many vias 67 as possible.

  Next, a cross-sectional structure around the global wiring layer of the semiconductor device according to the second embodiment will be described. Note that since the cross-sectional structure of the transistor is the same in Embodiment 2, the description is omitted and only the wiring formed in the global wiring layer is described.

  FIG. 20 is a cross-sectional view of the IO cell along the line XX-XX in FIG. As shown in FIG. 20, in the first global wiring layer in the cross section along the line XX-XX, the first layer power supply wiring 62 and the first layer ground wiring 63 are formed with substantially the same wiring width. Further, in the second global wiring layer in the cross section along the line XX-XX, the second layer ground wiring 66 is formed wider than the second layer power supply wiring 65 (wiring width in the Y direction). . The second layer power wiring 65 is formed above the first layer ground wiring 63, and the second layer ground wiring 66 is formed above the first layer power wiring 62. As shown in FIG. 20, in the second embodiment, the wiring formed in the third global wiring layer is connected to the wiring of the same voltage formed in the second global wiring layer by the via 68.

  FIG. 21 is a cross-sectional view of the IO cell along the line XXI-XXI in FIG. As shown in FIG. 21, also in the cross section along the XXI-XXI line, the first layer power wiring 62 and the first layer ground wiring 63 are formed with substantially the same wiring width in the first global wiring layer. In the second global wiring layer in the cross section along the XXI-XXI line, the second layer power supply wiring 65 is formed to have a wider wiring width (wiring width in the Y direction) than the second layer ground wiring 66. . The second layer power wiring 65 is formed above the first layer ground wiring 63, and the second layer ground wiring 66 is formed above the first layer power wiring 62. Further, as shown in FIG. 21, in the second embodiment, the wiring formed in the third global wiring layer is connected to the wiring of the same voltage formed in the second global wiring layer by the via 68.

  As shown in FIGS. 20 and 21, in the semiconductor device according to the second embodiment, in the global wiring layer, a wiring to which power of a different voltage is supplied is arranged in the vertical direction of the semiconductor chip (for example, Z Direction). In particular, it is important that the second power supply wiring and the third power supply wiring having a voltage different from that of the second power supply wiring have a structure of being stacked in the vertical direction (for example, the Z direction) of the semiconductor chip. is there.

  From the above description, in the semiconductor device according to the second embodiment, the power supply wiring having the unevenness on the side surface is provided in the second global wiring layer. That is, the power supply wiring having the unevenness on the side surface may be in any global wiring layer, but the semiconductor device according to the first embodiment is provided by providing the power supply wiring having the unevenness on the side surface in at least one layer. The effect of can be obtained. More specifically, by having the above-described characteristics, it is possible to obtain an effect of reducing the wiring resistance when the number of IO cells connected to one circuit wiring is increased.

Embodiment 3
In the third embodiment, another form of the shape of the wiring formed from the first global wiring to the third global wiring will be described. More specifically, in Embodiment 3, an example in which the wiring formed in the second global wiring layer and the wiring formed in the third global wiring layer have a shape with unevenness on the side surfaces, respectively. explain. That is, in the third embodiment, the third power supply wiring that connects the wirings of the same voltage adjacent in the lower layer is formed in the second and third global wiring layers. Therefore, also in the semiconductor device according to the third embodiment, the transistor has the layout shown in FIG. An IO cell having a global wiring structure according to the second embodiment is hereinafter referred to as an IO cell 70.

  The layout for each global wiring layer of the semiconductor device according to the third embodiment is shown in FIGS. FIG. 22 shows a schematic diagram of the layout of the first global wiring layer of the IO cell 70 according to the third exemplary embodiment.

  As shown in FIG. 22, in the IO cell 70 according to the second exemplary embodiment, the first global wiring layer includes a first power supply wiring (for example, the first layer power supply wiring 72) and a second power supply wiring (first power supply wiring). A first layer ground wiring 73) is arranged. In other words, the power supply is supplied to the first layer power supply wiring 72, and the ground voltage is supplied to the first layer ground wiring 73. The first layer power supply wiring 72 is connected to the source of the PMOS transistor shown in FIG. The first layer ground wiring 73 is connected to the source of the NMOS transistor shown in FIG. Note that the first layer power supply wiring 72 and the first layer ground wiring 73 and the transistor are electrically connected by a stack via including the via 71 or a wiring structure including the local wiring layer and another via.

  The first layer power supply wiring 72 and the first layer ground wiring 73 are wirings formed to extend in a direction parallel to the X direction. The first layer power supply wiring 72 is mainly disposed in the upper layer of the N-type well region 20, and the first layer ground wiring 73 is mainly disposed in the upper layer of the P-type well region 23. In the third embodiment, the first layer power supply wiring 72 and the first layer ground wiring 73 have a shape that does not have irregularities on the side surfaces.

  Next, FIG. 23 shows a schematic diagram of the layout of the second global wiring layer of the IO cell 70 according to the third exemplary embodiment. As shown in FIG. 23, a second layer power supply wiring 75 and a second layer ground wiring 76 are arranged in the second global wiring layer. The first power is supplied to the second layer power wiring 75 and the second power is supplied to the second layer ground wiring 76. As shown in FIG. 23, in the second global wiring layer, the second layer power supply wiring 75 and the second layer ground wiring 76 are alternately arranged in the Y direction.

  Further, as shown in FIG. 23, each of the second layer power supply wiring 75 and the second layer ground wiring 76 has irregularities on at least one side surface. The convex portion of the second layer power supply wiring 75 and the concave portion of the second layer ground wiring 76 are formed so as to mesh with each other. That is, the second layer power supply wiring 75 and the second layer ground wiring 76 are arranged so that the concavo-convex portions thereof are engaged with each other.

  As shown in FIG. 23, the second layer power supply wiring 75 is formed in an upper layer of the first layer ground wiring 73 formed below the second layer power supply wiring 75. The tip of the convex portion of the second layer power supply wiring 75 is formed so as to be located in an upper layer of the first layer power supply wiring 72 adjacent in the first global wiring layer. The second layer power supply wiring 75 is connected to the adjacent first layer power supply wiring 72 in the first global wiring layer by a via 74 provided near the tip of the convex portion. That is, the second layer power supply wiring 75 corresponds to a third power supply wiring that connects two power supply wirings formed in another global wiring layer.

  Further, as shown in FIG. 23, the second layer ground wiring 76 is formed in an upper layer of the first layer ground wiring 73 formed below the second layer ground wiring 76. The tip of the convex portion of the second layer ground wiring 76 is formed so as to be located in the upper layer of the first layer ground wiring 73 adjacent in the first global wiring layer. The second layer ground wiring 76 is connected to the adjacent first layer ground wiring 73 in the first global wiring layer by a via 74 provided near the tip of the convex portion. That is, the second layer power supply wiring 75 corresponds to a fourth power supply wiring that connects two power supply wirings formed in another global wiring layer.

  In the third embodiment, the third power supply wiring and the fourth power supply wiring that connect wirings formed in other global wiring layers can be formed by wirings formed in one global wiring layer. That is, the tips of the convex portions of the second layer power supply wiring 75 and the second layer ground wiring 76 are formed at positions that extend beyond the Z-direction extension of the boundary line between the N-type well region 20 and the P-type well region 23. The

  FIG. 24 is a schematic diagram showing the layout of the third global wiring layer of the IO cell 70 according to the third embodiment. As shown in FIG. 24, a third layer power wiring 78 and a third layer ground wiring 79 are arranged in the third global wiring layer. The first power is supplied to the third layer power wiring 78, and the second power is supplied to the third layer ground wiring 79. Then, as shown in FIG. 24, in the second global wiring layer, the third layer power supply wiring 78 and the third layer ground wiring 79 are alternately arranged in the Y direction.

  Also, as shown in FIG. 24, the third layer power supply wiring 78 and the third layer ground wiring 79 each have irregularities on at least one side surface. The convex portion of the third layer power supply wiring 78 and the third layer ground wiring 79 are formed to mesh with each other. That is, the third layer power supply wiring 78 and the third layer ground wiring 79 are arranged so that their concavo-convex portions are engaged with each other.

  As shown in FIG. 24, the third layer power wiring 78 is formed in an upper layer of the second layer ground wiring 76 formed below the third layer power wiring 78. The tip of the convex portion of the third layer power supply wiring 78 is formed so as to be located above the convex portion of the second layer power supply wiring 75 adjacent in the second global wiring layer. The third layer power supply wiring 78 is connected to the convex portion of the second layer power supply wiring 75 adjacent in the second global wiring layer by a via 77 provided near the tip of the convex portion. That is, the third layer power supply wiring 78 corresponds to a third power supply wiring that connects two power supply wirings formed in the second global wiring layer. From another point of view, the second-layer power supply wiring 75 adjacent in the second global wiring layer also serves as the first power supply wiring.

  Further, as shown in FIG. 24, the third layer ground wiring 79 is formed in an upper layer of the second layer power wiring 75 formed below the third layer ground wiring 79. The tip of the convex portion of the third-layer ground wiring 79 is formed so as to be positioned above the adjacent second-layer ground wiring 76 in the second global wiring layer. The third layer ground wiring 79 is connected to the convex portion of the second layer ground wiring 76 adjacent in the second global wiring layer by a via 77 provided near the tip of the convex portion. That is, the third layer ground wiring 79 corresponds to a fourth power supply wiring that connects two power supply wirings formed in the second global wiring layer. From another viewpoint, the second-layer ground wiring 76 adjacent in the second global wiring layer also serves as the second power supply wiring.

  In the third embodiment, the third power supply wiring and the fourth power supply wiring that connect wirings formed in other global wiring layers can be formed by wirings formed in one global wiring layer. That is, the tips of the convex portions of the second layer power supply wiring 75 and the second layer ground wiring 76 are formed at positions that extend beyond the Z-direction extension of the boundary line between the N-type well region 20 and the P-type well region 23. The

  From the above description, in the third embodiment, the second global wiring layer is the second wiring layer having the third power supply wiring in relation to the first global wiring layer. In this relationship, the third wiring layer having the first and second power supply wirings is obtained.

  Subsequently, a cross-sectional structure around the global wiring layer of the semiconductor device according to the third embodiment will be described. Note that since the cross-sectional structure of the transistor is the same in Embodiment 3, the description thereof is omitted, and only the wiring formed in the global wiring layer is described.

  FIG. 25 shows a cross-sectional view of the IO cell along the line XXV-XXV in FIG. As shown in FIG. 25, in the first global wiring layer in the cross section along the line XXV-XXV, the first layer power supply wiring 72 and the first layer ground wiring 73 are formed with substantially the same wiring width. In the second global wiring layer in the cross section along the line XXV-XXV, the second layer ground wiring 76 is formed to have a wider wiring width (wiring width in the Y direction) than the second layer power supply wiring 75. . The second layer power wiring 75 is formed above the first layer ground wiring 73, and the second layer ground wiring 76 is formed above the first layer power wiring 72. Further, as shown in FIG. 25, in the second global wiring layer in the section along the line XXV-XXV, the second layer ground wiring 76 has a wiring width (a wiring in the Y direction) than the second layer power supply wiring 75. (Width) is formed wide. The third layer power wiring 78 is formed above the second layer ground wiring 76, and the third layer ground wiring 79 is formed above the second layer power wiring 75.

  FIG. 26 shows a cross-sectional view of the IO cell along the line XXVI-XXVI in FIG. As shown in FIG. 26, also in the cross section along the line XXVI-XXVI, in the first global wiring layer, the first layer power supply wiring 72 and the first layer ground wiring 73 are formed with substantially the same wiring width. In the second global wiring layer in the cross section along the line XXVI-XXVI, the second layer ground wiring 76 is formed to have a wider wiring width (wiring width in the Y direction) than the second layer power supply wiring 75. . The second layer power wiring 75 is formed above the first layer ground wiring 73, and the second layer ground wiring 76 is formed above the first layer power wiring 72. Further, as shown in FIG. 26, in the second global wiring layer in the cross section along the line XXVI-XXVI, the third layer ground wiring 79 has a wiring width (a wiring in the Y direction) than the third layer power supply wiring 78. (Width) is formed wide. The third layer power wiring 78 is formed above the second layer ground wiring 76, and the third layer ground wiring 79 is formed above the second layer power wiring 75.

  As shown in FIGS. 25 and 26, in the semiconductor device according to the third embodiment, in the global wiring layer, the wiring to which power of different voltage is supplied is arranged in the vertical direction of the semiconductor chip (for example, Z Direction). In particular, it is important that the second power supply wiring and the third power supply wiring having a voltage different from that of the second power supply wiring have a structure of being stacked in the vertical direction (for example, the Z direction) of the semiconductor chip. is there.

  From the above description, in the semiconductor device according to the third embodiment, when two wiring layers that overlap one another are viewed from among the three global wiring layers, the wiring arranged in the lower wiring layer is the first power supply wiring and The second power supply wiring, and the wiring arranged in the upper wiring layer becomes the third power supply wiring for connecting the first power supply wiring. The first wiring layer and the second wiring layer described in the claims are not limited to the example constituted by only one layer, and various forms are possible. Even if the configuration according to the third embodiment described above is employed, the effect of the semiconductor device according to the first embodiment can be obtained. More specifically, by having the above-described characteristics, it is possible to obtain an effect of reducing the wiring resistance when the number of IO cells connected to one circuit wiring is increased.

Embodiment 4
In the fourth embodiment, another form of the shape of the convex portion provided on the circumferential wiring will be described. FIG. 27 shows a schematic diagram of the layout of the first global wiring layer and the second global wiring layer of the IO cell 80 according to the fourth embodiment. In FIG. 27, the wiring provided in the second global wiring layer is made translucent so that both the wiring in the first global wiring layer and the wiring in the second global wiring layer can be visually recognized. .

  In the example shown in FIG. 27, unevenness is provided on the side surfaces of the first layer power supply wiring 81 and the first layer ground wiring 82 provided in the first global wiring layer. In the IO cell 80 according to the fourth embodiment, the second global power wiring 83 provided in the second global wiring layer and the power wiring (not shown) formed in the third global wiring layer are used for the first global. The adjacent first layer power supply lines 81 in the wiring layer are connected. Further, in the IO cell 80 according to the fourth embodiment, the first global is formed by the second layer ground wiring 84 provided in the second global wiring layer and the installation wiring (not shown) formed in the third global wiring layer. The adjacent first layer ground wirings 82 in the wiring layer are connected. The wiring of the first global wiring layer and the wiring of the second global wiring layer are connected by a via 85.

  Here, as shown in FIG. 27, in the IO cell 80 according to the fourth embodiment, the convex portions provided on the side surfaces of the first layer power supply wiring 81 and the first layer ground wiring 82 have a wide portion at the tip thereof. Have. The wide portion is a portion having a width (length in the X direction) larger than the base portion of the convex portion. In the fourth embodiment, a via 85 is provided in the wide portion. Thus, by providing the via 85 in the wide portion, in the fourth embodiment, the number of vias provided in one convex portion can be increased as compared to the other embodiments.

  From the above description, in the fourth embodiment, a wide portion is provided at the tip of the convex portion of the wiring provided in the global wiring layer, and a via is provided in the wide portion. Thereby, in the IO cell 80 according to the fourth embodiment, the number of vias 85 provided in the convex portion can be increased, and the resistance value in the Y direction of the peripheral wiring can be reduced.

Embodiment 5
In the fifth embodiment, another form of positional relationship between the IO cell pad and the IO logic formation region will be described. FIG. 28 shows a schematic diagram of the layout of the IO cell according to the fifth embodiment. As shown in FIG. 28, in the fifth embodiment, the pad 91 is provided in the upper layer of the IO logic formation region 92.

  Thereby, in the fifth embodiment, the pad 91 can be arranged only by the area of the IO logic formation region 92. That is, by adopting the layout of the fifth embodiment, the area of the IO cell can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, even when power supply wirings of the same voltage are adjacent to each other in the same wiring layer, when a group of power supply wirings of the same voltage are alternately arranged, a group of power supply wirings of the same voltage Can be regarded as one power supply wiring.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10, 60, 70, 80, 90 IO cell 11, 91 Pad 12 Circulation wiring 12v Circulation power supply wiring 12g Circulation ground wiring 13 Internal logic formation area 14, 92 IO logic formation area 20 N-type well area 21 P-type diffusion Region 22 Contact 23 P-type well region 24 N-type diffusion region 25 Contact 26 Gate electrode 27 Well contact wiring 28 Well contact 30, 40, 50, 61, 64, 67, 71, 74, 77, 85 Via 31, 32, 72 81 First layer power wiring 32, 63, 73, 82 First layer ground wiring 41, 65, 75, 83 Second layer power wiring 42, 66, 76, 84 Second layer ground wiring 51, 68, 78 Third Layer power wiring 52, 69, 79 Third layer ground wiring

Claims (9)

The first power supply wiring to which the first power supply is supplied, and the second and third power supply wirings to which the second power supply is supplied, and the second power supply wiring is interposed between the second power supply wiring and the second power supply wiring. And a first wiring layer in which the third power supply wiring is disposed,
A fourth power supply line supplied with the first power supply and connected to the first power supply line via a plurality of first vias; and a first power supply supplied to the first power supply line via a plurality of second vias. A fifth power supply line connected to the first power supply line; and a second power supply line supplied with the second power supply and connected to the second and third power supply lines through a plurality of third and fourth vias, respectively. 6 and a second wiring layer in which the fourth power supply wiring and the fifth power supply wiring are arranged with the sixth power supply wiring interposed therebetween,
Each of the first to sixth power supply wirings is formed to extend in the first direction,
The first power supply wiring has irregularities along both side surfaces so as to have a wide portion and a narrow portion,
The second and third power supply wirings have irregularities along at least one side surface, and are arranged so that the concave portion of the second power supply wiring meshes with the convex portion on one side surface of the first power supply wiring. The semiconductor device is arranged such that the concave portion of the third power supply wiring and the convex portion on the other side surface of the first power supply wiring are engaged with each other.   2. The semiconductor device according to claim 1, wherein a width of a tip portion of the convex portion on one side surface of the first power supply wiring is substantially equal to a width of the tip portion of the convex portion on the other side surface of the first power supply wiring. . The plurality of first vias are arranged on a convex portion provided on the one side surface of the first power supply wiring,
The plurality of second vias are arranged on a convex portion provided on the other side surface of the first power supply wiring,
The plurality of third vias are arranged on a convex portion of the second power supply wiring,
2. The semiconductor device according to claim 1, wherein the plurality of fourth vias are arranged on a convex portion of the third power supply wiring. The first wiring layer is formed under the second wiring layer,
The semiconductor device according to claim 1, wherein the sixth power supply wiring is formed above the first power supply wiring.   The sixth power supply wiring is connected to the second power supply wiring through the third via, and the seventh power supply wiring is connected to the third power supply wiring through the fourth via. The semiconductor device according to claim 1, comprising eight power supply wirings.   The semiconductor device according to claim 1, wherein the first power supply wiring is disposed so as to cover an upper layer of the P-type well region, and the second power supply wiring is disposed so as to cover an upper layer of the N-type well region.   A ninth power supply line supplied with the second power supply and connected to the sixth power supply wiring via a fifth via, and a tenth power connected to the sixth power supply wiring via a sixth via. The semiconductor device according to claim 1, further comprising a third wiring layer on which the power supply wiring is disposed.   The semiconductor device according to claim 7, wherein the ninth power supply wiring is disposed so as to cover a part of the sixth power supply wiring. An IO cell in which at least a buffer circuit is formed along a first direction parallel to the outer periphery of the semiconductor chip,
The first power supply wiring to which the first power supply is supplied, and the second and third power supply wirings to which the second power supply is supplied, and the second power supply wiring is interposed between the second power supply wiring and the second power supply wiring. And a first wiring layer in which the third power supply wiring is disposed,
A fourth power supply line supplied with the first power supply and connected to the first power supply line via a plurality of first vias; and a first power supply supplied to the first power supply line via a plurality of second vias. A fifth power supply line connected to the first power supply line; and a second power supply line supplied with the second power supply and connected to the second and third power supply lines through a plurality of third and fourth vias, respectively. 6 and a second wiring layer in which the fourth power supply wiring and the fifth power supply wiring are arranged with the sixth power supply wiring interposed therebetween,
Each of the first to sixth power supply lines is formed to extend in the first direction,
The first power supply wiring has irregularities along both side surfaces so as to have a wide portion and a narrow portion,
The second and third power supply wirings have irregularities along at least one side surface, and are arranged so that the concave portion of the second power supply wiring meshes with the convex portion on one side surface of the first power supply wiring. The IO cell is arranged such that the concave portion of the third power supply wiring and the convex portion on the other side surface of the first power supply wiring are engaged with each other.