JP2000332201A - Semiconductor integrated circuit and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor capable of appropriately suppressing noise generated in a semiconductor integrated circuit in a peripheral cell portion inside the semiconductor integrated circuit at a location close to a noise source, and flexibly supporting various uses of the peripheral cell. An integrated circuit and a method for manufacturing the same are obtained. SOLUTION: In a semiconductor integrated circuit provided with a peripheral cell 1 for transmitting an input / output signal between the outside of the semiconductor integrated circuit and an internal logic circuit, a logic circuit region portion 11 having the input / output signal transmission function, a noise suppression function Is provided in the peripheral cell 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention implements a countermeasure for power supply noise in a cell (hereinafter referred to as a "peripheral cell") which is mainly disposed on the outer periphery of a semiconductor integrated circuit and transmits input / output signals between the semiconductor integrated circuit and the outside. The present invention relates to a semiconductor integrated circuit having a function.

A peripheral cell includes a pad for wire bonding (hereinafter referred to as a pad), and a driver logic for transmitting an output from an internal logic circuit of the semiconductor integrated circuit to the outside.
It is composed of a driver logic for transmitting an input from outside the semiconductor integrated circuit to the internal logic circuit, and a control logic for controlling the input / output of signals.

[0003]

2. Description of the Related Art Generally, an operating semiconductor integrated circuit generates noise, and the noise propagates outside the semiconductor integrated circuit via signal wiring and power supply wiring. It is necessary to control the noise so that the noise does not affect the operation and performance of the system in which the semiconductor integrated circuit is mounted.

When a conventional semiconductor integrated circuit is mounted on a mounting substrate 40, as a countermeasure against power supply noise, FIG.
As shown in (1), a power supply / GND capacitance (bypass capacitor) 42 is inserted between the VDD wiring 41a and the GND wiring 41b on the mounting substrate 40 outside the semiconductor integrated circuit 39.

[0005]

In the above arrangement, in order to take measures against noise generated by the semiconductor integrated circuit, components irrelevant to the original function of the system are mounted on the board on which the semiconductor integrated circuit is mounted. There is a need.

[0006] Therefore, the number of components and the weight on the mounting board are increased, and this has been a problem particularly in portable electronic devices that need to be reduced in size and weight. Also, as a package of a semiconductor integrated circuit, connection terminals to a mounting substrate are arranged in a grid on the package surface to reduce the mounting area.
When a device such as an all grid array (BGA) is employed, the bypass capacitor cannot be disposed at an effective position on the mounting substrate, that is, in the vicinity of the terminal, depending on the position of the terminal on the semiconductor integrated circuit package. The problem had arisen.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and measures against noise generated by a semiconductor integrated circuit are appropriately implemented not in the outside of the semiconductor integrated circuit but in an internal peripheral cell portion. And a method of manufacturing the same.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit including a peripheral cell for transmitting input / output signals between the outside of the semiconductor integrated circuit and an internal logic circuit. A logic circuit portion having a signal transmission function and a capacitance portion having a noise suppression function are provided in the peripheral cell.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit including a peripheral cell for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit.
A power supply wiring portion and a second power supply wiring portion provided in parallel with the first power supply wiring portion in the peripheral cell, and a logic circuit portion having the input / output signal transmission function.
A capacitor portion having a noise suppressing function is provided so as to be connected between a first power supply wiring portion and a second power supply wiring portion provided in the peripheral cell.

According to a third aspect of the present invention, there is provided a semiconductor integrated circuit having peripheral cells for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit.
A power supply wiring portion and a second power supply wiring portion provided in parallel with the first power supply wiring portion in the peripheral cell, and a logic circuit portion having the input / output signal transmission function.
A capacitor portion having a noise suppressing function is provided between the first power supply wiring portion and the second power supply wiring portion provided in the peripheral cell, and the first and second power supply wiring regions are provided. And between these power supply wiring regions.

[0011] In a semiconductor integrated circuit according to a fourth aspect of the present invention, in the semiconductor integrated circuit having peripheral cells for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit,
A power supply wiring portion and a second power supply wiring portion provided in parallel with the first power supply wiring portion in the peripheral cell, and a logic circuit portion having the input / output signal transmission function.
A capacitor portion having a noise suppressing function is arranged side by side with a first power supply wiring portion provided in the peripheral cell and a second power supply wiring portion.
And a power supply wiring portion.

According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit including a peripheral cell for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit.
A power supply wiring portion and a second power supply wiring portion provided in parallel with the first power supply wiring portion in the peripheral cell, and a logic circuit portion having the input / output signal transmission function.
A capacitor portion having a noise suppressing function is arranged side by side with a first power supply wiring portion provided in the peripheral cell and a second power supply wiring portion.
Between the power supply wiring portion and the first
And a second power supply wiring region and a position between these power supply wiring regions.

In a semiconductor integrated circuit according to a sixth aspect of the present invention, in a semiconductor integrated circuit having peripheral cells for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit,
D wiring part and GND arranged in parallel with the VDD wiring part
A wiring portion is provided in the peripheral cell, and a logic circuit portion having the input / output signal transmitting function and a capacitance portion having a noise suppressing function are arranged side by side with each other, and a VDD wiring portion provided in the peripheral cell is connected to GND. It is provided so as to be connected between the wiring portion.

In a semiconductor integrated circuit according to a seventh aspect of the present invention, in a semiconductor integrated circuit having peripheral cells for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit,
D wiring part and GND arranged in parallel with the VDD wiring part
A wiring portion is provided in the peripheral cell, and a logic circuit portion having the input / output signal transmitting function and a capacitance portion having a noise suppressing function are arranged side by side with each other, and a VDD wiring portion provided in the peripheral cell is connected to GND. And a connection portion between the VDD wiring region and the GN.
This is located between the D wiring region and these wiring regions.

In a semiconductor integrated circuit according to an eighth aspect of the present invention, the peripheral cell is provided with a pad and an input / output terminal connected via the logic circuit portion.

In a semiconductor integrated circuit according to a ninth aspect of the present invention, an n-type semiconductor region formed in a p-type semiconductor region is electrically connected to the n-type semiconductor region via a dielectric as a capacitance portion of the peripheral cell. And an electrode coupled to the capacitor.

In a semiconductor integrated circuit according to a tenth aspect,
As a capacitance portion of the peripheral cell, a capacitance constituted by an n-type semiconductor region formed in a p-type well and an electrode electrically coupled to the n-type semiconductor region via a dielectric is provided. .

In the semiconductor integrated circuit according to the eleventh aspect,
As the capacitance portion of the peripheral cell, one in which the gate electrode of the N-channel MOS transistor is connected to the VDD wiring portion and the source / drain is connected to the GND wiring portion is used.

In the semiconductor integrated circuit according to the twelfth aspect,
As a capacitance portion of the peripheral cell, a capacitance formed of a MOS capacitor composed of an n-type semiconductor region formed on a p-type semiconductor substrate, a gate oxide film and a gate electrode is provided.

In the semiconductor integrated circuit according to the thirteenth aspect,
A first gate electrode as a capacitance portion of the peripheral cell;
A capacitor comprising a second gate electrode and an insulating film disposed between the first and second gate electrodes is provided.

According to a fourteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit, comprising a peripheral cell for transmitting an input / output signal between the outside of the semiconductor integrated circuit and an internal logic circuit, and a logic circuit portion having the input / output signal transmission function. Forming a semiconductor region and an electrode forming the logic circuit portion in a semiconductor integrated circuit in which a capacitor portion having a noise suppressing function is provided in the peripheral cell; and forming the capacitor portion. The method includes a step of forming a dielectric element and an electrode, and a wiring step of electrically connecting components of the logic circuit portion and the capacitor portion.

According to a fifteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit, comprising a peripheral cell for transmitting an input / output signal between the outside of the semiconductor integrated circuit and an internal logic circuit, and a logic circuit portion having the input / output signal transmission function. And a capacitor portion having a noise suppressing function, in a semiconductor integrated circuit provided in the peripheral cell, wherein a logic circuit portion forming step of forming a semiconductor region and an electrode forming the logic circuit portion; Forming a dielectric element and an electrode forming a part, and electrically connecting the components of the logic circuit part and the capacitance part after the logic circuit part forming step and the capacitance part forming step. The wiring process is performed.

According to a sixteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit, comprising a peripheral cell for transmitting an input / output signal between the outside of the semiconductor integrated circuit and an internal logic circuit, and a logic circuit portion having the input / output signal transmission function. And a capacitor part having a noise suppressing function in a peripheral integrated cell for manufacturing a semiconductor integrated circuit. A field step of forming a field oxide film on a p-type semiconductor substrate, and forming an n-well for forming an n-well A p-well forming step of forming a p-well, a gate electrode forming step of forming a gate electrode, an n-source / drain forming step of forming an n-source / drain, and a p-source / drain forming a p-source / drain.
A wiring for electrically connecting each element formed by the n-well forming step, the p-well forming step, the gate electrode forming step, the n-source / drain forming step, and the p-source / drain forming step. It includes steps.

According to a seventeenth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit, comprising a peripheral cell for transmitting an input / output signal between the outside of the semiconductor integrated circuit and the internal logic circuit, and a logic circuit portion having the input / output signal transmission function. And a capacitor part having a noise suppressing function in a peripheral integrated cell for manufacturing a semiconductor integrated circuit. A field step of forming a field oxide film on a p-type semiconductor substrate, and forming an n-well for forming an n-well A p-well forming step of forming a p-well, a gate electrode forming step of forming a gate electrode, an n-source / drain forming step of forming an n-source / drain, and a p-source / drain forming a p-source / drain.
A wiring for electrically connecting each element formed by the n-well forming step, the p-well forming step, the gate electrode forming step, the n-source / drain forming step, and the p-source / drain forming step. The wiring step is performed after the n-well forming step, the p-well forming step, the gate electrode forming step, the n-source / drain forming step, and the p-source / drain forming step.

According to an eighteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit, comprising a peripheral cell for transmitting input / output signals between the outside and the internal logic circuit of the semiconductor integrated circuit, and a logic circuit portion having the input / output signal transmission function. And a capacitor part having a noise suppressing function in a peripheral integrated cell for manufacturing a semiconductor integrated circuit. A field step of forming a field oxide film on a p-type semiconductor substrate, and forming an n-well for forming an n-well A p-well forming step of forming a p-well, a gate electrode forming step of forming a gate electrode, an n-source / drain forming step of forming an n-source / drain, and a p-source / drain forming a p-source / drain.
A drain hole forming step, a contact hole forming step of forming a contact hole, a first wiring step of forming a first layer wiring, and a vi forming of a via hole
The method includes an a-hole forming step and a second wiring step of performing wiring of a second layer.

According to a nineteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit, comprising a peripheral cell for transmitting an input / output signal between the outside of the semiconductor integrated circuit and the internal logic circuit, and a logic circuit portion having the input / output signal transmission function. And a capacitor part having a noise suppressing function in a peripheral integrated cell for manufacturing a semiconductor integrated circuit. A field step of forming a field oxide film on a p-type semiconductor substrate, and forming an n-well for forming an n-well A p-well forming step of forming a p-well, a gate electrode forming step of forming a gate electrode, an n-source / drain forming step of forming an n-source / drain, and a p-source / drain forming a p-source / drain.
A drain hole forming step, a contact hole forming step of forming a contact hole, a first wiring step of forming a first layer wiring, and a vi forming of a via hole
a field forming step, an n-well forming step, and a second wiring step of forming a second layer wiring.
After the p-well forming step, the gate electrode forming step, the n-source / drain forming step and the p-source / drain forming step, a contact hole forming step, a first wiring step, vi
The a hole forming step and the second wiring step are performed.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1. One embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an overall configuration of a semiconductor integrated circuit according to one embodiment of the present invention. In FIG. 1, A is a semiconductor chip, 1 is a peripheral cell having an input / output circuit with the outside of the semiconductor integrated circuit and has a built-in capacitor for noise suppression, and 3a is a lateral peripheral in which the peripheral cells 1 are arranged adjacent to each other. The cell column 3b is also a peripheral cell column in the vertical direction, and 6 is an internal logic circuit.

A peripheral cell 1 having an input / output circuit with the outside of the semiconductor integrated circuit and a capacitor for noise suppression is connected to an internal logic circuit 6 and a wiring 7. And 4a, 4b
Are a VDD wiring and a GND wiring forming the first and second power supply wirings of the peripheral cell 1 inside the horizontal peripheral cell row 3a and the vertical peripheral cell row 3b, respectively. Wiring 4a, GND wiring 4b
And are interconnected. Further, the peripheral cell columns 3a, 3b
The VDD wiring 4a and the GND wiring 4b of the peripheral cell 1 inside are connected to the V line provided between the peripheral cell columns 3a and 3b.
They are interconnected by a DD wiring 8a and a GND wiring 8b.

FIG. 2 is a plan view showing the configuration of a cell 1 having a built-in input / output circuit with the outside of the semiconductor integrated circuit and a capacitor for noise suppression. In FIG. 2, 9 is a pad, 4a,
Reference numeral 4b denotes a VDD wiring and a GND wiring. A region 10 surrounded by a dotted line is a capacitance region, and a region 11 is a peripheral cell logic circuit region. A MOS (Me) functioning as a bypass capacitor for power supply noise suppression is provided in the capacitance region 10.
tal Oxide Semiconductor), and one electrode is connected to VDD.
The other electrode is connected to the wiring 4a and the GND wiring 4b.

The peripheral cell logic circuit area 11 is a CMOS
(Complementary Metal Oxid
e semiconductor circuit), a driver logic for transmitting an output from an internal logic circuit of the semiconductor integrated circuit to the outside, a driver logic for transmitting an input from the outside of the semiconductor integrated circuit to the internal logic circuit 6, and a control for controlling signal input / output. It is composed of logic. VD of CMOS circuit forming peripheral cell logic circuit region 11
D and GND are connected to the same VDD wiring 4a and GND wiring 4b as the capacitance region 10.

If necessary, a wiring 12 for connecting the pad 9 to the peripheral cell logic circuit area 11 and a wiring lead-out port 13 for connecting the peripheral cell logic circuit area 11 to the internal logic circuit (hereinafter referred to as a peripheral cell upper part). Output terminal) is formed. The pad 9 and the input / output signal terminal 13 on the peripheral cell (and the internal logic circuit 6 connected thereto) are connected via the peripheral cell logic circuit region 11, and an input or output signal is transmitted.

FIG. 3 is a plan view showing an example of a layout in the capacitance region 10 of the peripheral cell 1 shown in FIG. 3, 4a is a VDD wiring, 4b is a GND wiring, 1
4 is a gate electrode, 15 is an n-type semiconductor region (n source / drain), 16 is a via hole, and 17 is a contact hole.

FIGS. 4 and 5 respectively show the IV-IV section and the VV section of this capacitor shown in FIG.
An n-source / drain 15 is formed in a p-well 19 of a p-type semiconductor substrate 21, and an N-channel MOS in which a gate oxide film 20 and a gate electrode 14 are formed on a channel region between the n-source / drain 15 Has a transistor configuration.

The gate electrode 14 is connected to the VDD wiring 4a, and the n source / drain 15 is connected to the GND wiring 4b. As shown in FIG. 6, the N-channel transistor 22 is always used in the ON state, and the gate oxide film is used. 20 is a derivative, and functions as a capacitor having an inversion layer formed in a region between the gate electrode 14 and the n source / drain 15 as an electrode.

In the figure, since the VDD wiring and the GND wiring are the second-layer metal wiring, the first-layer metal wiring 1
The gate wiring 14 is connected to the gate electrode 14 and the n source / drain 15 through 8, but this does not limit the metal wiring of which layer is used for the VDD wiring and the GND wiring.

FIG. 7 is a plan view of the peripheral cell logic circuit region 11 of the peripheral cell 1 of FIG. 8 and 9
(A) and FIG. 9 (b) respectively show the VI in FIG.
II-VIII section, IX (a) -IX (a) section and IX (b)
-IX (b) shows a cross section.

Formed in the peripheral cell logic circuit region 11;
The driver logic for transmitting an output from the internal logic circuit of the semiconductor integrated circuit to the outside, the driver logic for transmitting an input from the outside of the semiconductor integrated circuit to the internal logic circuit, and the control logic for controlling the input / output of signals are CMOS circuits. Yes, it is of a configuration conventionally used.

FIGS. 7, 8, 9A and 9B
, 4a is a VDD wiring, 4b is a GND wiring, 14
Is a gate electrode, 15 is an n-type semiconductor region (n source / drain), 16 is a via hole, 17 is a contact hole, 18 is a metal wiring, 20 is a gate oxide film, 21 is a p-type semiconductor substrate, and 19 and 24 are respectively. p-type semiconductor substrate 21
The upper p well and the n well, 23 is a p source / drain region, and 36 is a field oxide film. Although the details of the circuit configuration are not shown in the figure, the input driver logic, the output driver logic and the control logic are configured by connecting P-channel and N-channel transistors in the peripheral cell logic circuit region 11 with metal wiring. I have.

With the above configuration, a capacitance (bypass capacitor) can be inserted into the VDD wiring and the GND wiring in the semiconductor integrated circuit. Therefore, measures to suppress noise generated inside the semiconductor integrated circuit in the peripheral cell portion are taken. Becomes possible. As a result, parts (capacitance) required outside the semiconductor integrated circuit for noise suppression can be reduced.

In a semiconductor integrated circuit, a peripheral cell portion having an input / output circuit with the outside of the semiconductor integrated circuit uses a transistor having a large current driving capability for outputting a signal to the outside. It is one of the most prominent sources of noise that can cause problems in systems. With the configuration in which the capacitance is arranged in the peripheral cell shown in FIG.
Capacitance closer to the noise source (bypass capacitor)
Can be added, and a higher noise suppression effect can be expected.

Further, the advantage of the configuration of the peripheral cell shown in FIG.
Gate Array for easy placement of noise suppression capacitors
y (GA) method or Embedded Cell A
That is, the present invention can be applied to a design method of the rray (ECA) method. In the design method of the GA method and the ECA method, the circuit configuration of the semiconductor integrated circuit is changed to a metal wiring step (hereinafter, referred to as a slice step) after a contact hole is formed in a manufacturing process of the semiconductor integrated circuit schematically illustrated in FIGS. Steps from the field step S25 in FIG. 10 to the p source / drain formation step S30 before the formation of the contact holes (hereinafter, referred to as a master step)
To design. This makes it possible to start the wafer process when the design for the process of FIG. 10 is completed, and to design for the processes after the formation of the contact hole while the wafer process is proceeding with the process of FIG. Can be. Thus, the development period of the semiconductor integrated circuit can be shortened.

Here, the manufacturing process flow of the semiconductor integrated circuit shown in FIGS. 10 and 11 will be described. FIG.
0, Step S25 is a field process for forming a field oxide film on the p-type semiconductor substrate, Step S26
Is an n-well forming step of forming an n-well, step S2
7 is a p-well forming step of forming a p-well, step S
28 is a gate electrode forming step of forming a gate electrode, and step S29 is an n source / drain forming n source / drain.
The drain forming step, step S30, is a p source / drain forming step of forming a p source / drain. The processes of steps S25 to S30 starting from step S25 and proceeding according to the arrows in the figure constitute a so-called master process.

In FIG. 11, step S31 is a contact hole forming step of forming a contact hole, step S32 is a first metal wiring step of forming a first layer wiring,
Step S33 is a via hole forming step of forming a via hole, and step S34 is a second metal wiring step of forming a second layer wiring. The processes of steps S31 to S34 starting from step S31 and proceeding according to the arrows in the figure constitute a so-called slice process.

A master step including a field step S25, an n-well forming step S26, a p-well forming step S27, a gate electrode forming step S28, an n-source / drain forming step S29 and a p-source / drain forming step S30 includes:
The method includes a logic circuit portion forming step of forming a semiconductor region and an electrode forming a logic circuit region portion, and a capacitor portion forming step of forming a dielectric element and an electrode forming the capacitance region portion. In addition, the slicing step including the contact hole forming step S31, the first metal wiring step S32, the via hole forming step S33, and the second metal wiring step S34 includes a logic circuit area portion formed by the master step as a whole. This includes a wiring step of electrically connecting the components of the capacitance region portion. Then, after the logic circuit area portion forming step and the capacity area portion forming step as the master step, a wiring step as the slicing step for electrically connecting the components of the logic circuit area portion and the capacitor area portion is performed. This completes a logic circuit portion having an input / output signal transmission function and a capacitance portion having a noise suppression function in peripheral cells.

The peripheral cell having the structure shown in FIG.
ay (GA) method or Embedded Cell
When applied to the array (ECA) design method,
Even if a peripheral cell is assigned to an input / output terminal of the semiconductor integrated circuit, NC (No Control) which is not actually used for input / output of signals between the outside of the semiconductor integrated circuit and the internal logic circuit 6
ct) terminal, or a VDD, GND connection terminal used to connect a power supply to the outside of the semiconductor integrated circuit. In either case, a capacitance is formed in a peripheral cell to prevent noise. It is possible to connect between a VDD wiring and a GND wiring. It is not impossible to form and connect a capacitor depending on the use of the peripheral cell. This is because the formation of the capacitance has been completed in the master process.

In the case of a peripheral cell assigned to an input / output terminal, VDD is used in a slicing process in order to propagate input and output signals of the outside and the internal logic circuit of the semiconductor integrated circuit while taking measures against power supply noise. Wiring 4a
After connecting the electrodes of the capacitors to the GND wiring 4b, the metal wiring required for the circuit configuration in the peripheral cell logic circuit area 11, the wiring 12 connecting the pad 9 and the peripheral cell logic circuit area 11, and the peripheral A peripheral cell input / output signal terminal 13 for connecting the cell logic circuit region 11 and the internal logic circuit 6 may be formed.

In the case of a peripheral cell assigned to an NC (No Contact) terminal, a wiring 12 connecting the pad 9 and the peripheral cell logic circuit area 11 and a metal wiring required for the circuit configuration of the peripheral cell logic circuit area 11 It is not necessary to form the input / output signal terminal 13 on the peripheral cell, and only the connection of the capacitance electrode to the VDD wiring 4a and the GND wiring 4b in the slicing step is necessary to insert the capacitance between the VDD wiring and the GND wiring. Good.

Similarly, if the peripheral cells are assigned to the VDD and GND connection terminals used for connecting the power supply to the outside of the semiconductor integrated circuit, the VDD wiring 4a is similarly used in the slicing process.
And a capacitor 9 is connected to the GND wiring 4b and the pad 9 is connected to the VDD wiring 4a or the GND wiring 4b.
What should I do?

In the above description, the effect of suppressing the noise radiated from the semiconductor integrated circuit to the outside has been described. However, the capacitance connected between the VDD wiring and the GND wiring by the peripheral cell 10 is reversed from the outside of the semiconductor integrated circuit by the power supply. Noise transmitted to the internal logic circuit of the semiconductor integrated circuit through the wiring is also suppressed. Therefore, there is also an effect of preventing malfunction of the internal logic circuit due to noise outside the semiconductor integrated circuit.

According to the first embodiment of the present invention, in a semiconductor integrated circuit having peripheral cell 1 for transmitting input / output signals between the outside of the semiconductor integrated circuit and internal logic circuit 6,
A logic circuit portion 1 having a VDD wiring 4a portion and a GND wiring 4b portion juxtaposed to the VDD wiring portion 4a is provided in the peripheral cell 1 and has the input / output signal transmission function.
1 and a capacitor portion 10 having a noise suppressing function are arranged in parallel with each other, and a VDD wiring 4a provided in the peripheral cell.
And the GND line 4b, the VDD line 4a region, the GND line 4b region, and the region between these lines 4a and 4b. Therefore, noise generated by the semiconductor integrated circuit is reduced. It is possible to obtain a semiconductor integrated circuit that can be appropriately suppressed by a simple configuration in a portion near the noise generation source in one internal peripheral cell and can flexibly cope with various uses of the peripheral cell.

The n-type semiconductor region 15 formed in the p-well 19 and the gate electrode 14 electrically coupled to the n-type semiconductor region 15 via the dielectric oxide film 20 as a capacitance portion of the peripheral cell 1. N channel M composed of
Since the gate electrode 14 of the OS transistor is connected to the VDD wiring 4a and the source / drain is connected to the GND wiring 4b, the capacitor 1 of the peripheral cell 1 is used.
0 can be provided appropriately and easily with a simple configuration.

A logic circuit portion 11 having an input / output signal transmission function and a capacitance portion 10 having a noise suppression function are provided with a peripheral cell 1 for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit. And the peripheral cell 1
In the manufacture of the semiconductor integrated circuit provided in
Field step S25 for forming field oxide film 36 on type semiconductor substrate 21, n-well forming step S26 for forming n-well 24, p-well forming step S27 for forming p-well 19, and gate for forming gate electrode 14. The logic circuit portion 11 includes an electrode forming step 28, an n source / drain forming step 29 for forming the n source / drain 15, and a p source / drain forming step S 30 for forming the p source / drain 23. Forming a logic circuit portion for forming a semiconductor region and an electrode to be formed, and forming a dielectric element and a capacitor for forming a capacitance portion for forming the capacitor portion, and forming a contact hole. S31, a first wiring step S32 for performing wiring of the first layer, and via A via hole formation process S33 of forming a Lumpur, second wiring step S34 to perform the wiring of the second layer
And a slicing step including a wiring step of electrically connecting the components of the logic circuit portion and the capacitance portion. The field step S25, the n-well forming step S26, the p-well forming step S27, the gate electrode forming After the master step including the step S28, the n source / drain forming step S29 and the p source / drain forming step S30, a contact hole forming step S31, a first wiring step S32, a via hole forming step S33, and a second wiring step S34. Since the slicing step is performed, a method of manufacturing a semiconductor integrated circuit that can flexibly cope with various uses of the peripheral cell 1 can be obtained.

Embodiment 2 In the first embodiment, a gate capacitance having a structure in which an N-channel transistor is used in an ON state is used as a built-in capacitance for power supply noise suppression used in the peripheral cell 1, but the structure of the capacitance to be used is limited to this. Do not mean.

FIG. 12 is a plan view of a capacitor having a structure different from the capacitance arranged in the capacitance region 10 of the peripheral cell 1 in the first embodiment. 13 and FIG.
XIII-XIII section and XIV-XIV sectional view of the capacity shown in FIG.

The gate oxide film 20 and the gate electrode 14 are formed on the n-type semiconductor region 35 formed on the p-type semiconductor substrate 21.
Are formed in the MOS capacitor. The gate electrode 14 is connected to the VDD wiring 4a. The n-type semiconductor region 35 functions as a counter electrode of the gate electrode in this capacitor, and is connected to the GND wiring 4b via the n-type region 15 formed in the n-source / drain process. By arranging the capacitance shown in FIG. 12 in the capacitance region 10 of the peripheral cell 1 of the first embodiment, the same effect as that of the first embodiment can be obtained.

According to the second embodiment of the present invention, the capacitance portion 10 of the peripheral cell 1 includes the n-type semiconductor region 35 formed on the p-type semiconductor substrate 21, the gate oxide film 20, and the gate electrode 14. Since the capacitor composed of the MOS capacitor is provided, the capacitance portion 10 of the peripheral cell 1 can be appropriately and easily provided with a simple configuration.

Embodiment 3 In the first embodiment, a gate capacitor having a structure in which an N-channel transistor is used in an ON state is used for the capacitor built-in peripheral cell 1 for power supply noise suppression. Further, in the second embodiment, the capacitor constituted by the n-type region on the p-type semiconductor substrate, the gate oxide film, and the gate electrode is used, but the structure of the used capacitor is not limited to this.

FIG. 15 is a plan view showing a capacitor having a structure different from that of the capacitor arranged in the capacitor region 10 of the peripheral cell 1 incorporating a capacitor in the first and second embodiments. FIGS. 16 and 17 show the XVI-X of the capacity of FIG.
A VI section and a XVII-XVII section are shown.

The capacitance in the third embodiment is such that the gate electrode 37 on the field oxide film 36 formed on the p-type semiconductor substrate 21, the insulating film 38 formed so as to cover the gate electrode 37, and further covers the same. The gate electrode 14 is connected to the VDD wiring 4a. The insulating film 38 is interposed between the gate electrode 14 and the gate electrode 37, functions as a dielectric, and forms a capacitor. The gate electrode 37 is connected to GND from a window opened in the insulating film 38 and the gate electrode 14.
It is connected to the wiring 4b.

If the capacitance shown in FIG. 15 is arranged in capacitance region 10 of peripheral cell 1 in the first or second embodiment, the same effect as in the first or second embodiment can be obtained.

According to the third embodiment of the present invention, the first gate electrode 14,
Since the capacitor composed of the second gate electrode 37 and the insulating film 38 disposed between the first and second gate electrodes 14 and 37 is provided, the capacitance portion 10 of the peripheral cell 1 is simplified. It can be provided appropriately and easily in the configuration.

[0062]

According to the semiconductor integrated circuit of the first aspect, in the semiconductor integrated circuit having peripheral cells for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit, the input / output signal transmission is performed. A logic circuit portion having a function;
Since a capacitance portion having a noise suppressing function is provided in the peripheral cell, noise generated in the semiconductor integrated circuit can be appropriately suppressed at a location near a noise source in a peripheral cell portion inside the semiconductor integrated circuit. A semiconductor integrated circuit that can flexibly cope with various applications can be obtained.

According to the semiconductor integrated circuit of the second invention, in the semiconductor integrated circuit having the peripheral cells for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit, the first power supply wiring portion A second power supply wiring portion provided in parallel with the first power supply wiring portion is provided in the peripheral cell, and a logic circuit portion having the input / output signal transmission function and a capacitance portion having a noise suppression function are provided. Since the semiconductor integrated circuit is connected between the first power supply wiring portion and the second power supply wiring portion provided in the peripheral cell, noise generated in the semiconductor integrated circuit can be generated in the peripheral cell portion inside the semiconductor integrated circuit. It is possible to obtain a semiconductor integrated circuit that can be appropriately suppressed by a simple configuration in the vicinity of the source and that can flexibly cope with various uses of peripheral cells.

According to the semiconductor integrated circuit of the third aspect, in the semiconductor integrated circuit having the peripheral cells for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit, the first power supply wiring portion A second power supply wiring portion provided in parallel with the first power supply wiring portion is provided in the peripheral cell, and a logic circuit portion having the input / output signal transmission function and a capacitance portion having a noise suppression function are provided. Provided between a first power supply wiring portion and a second power supply wiring portion provided in the peripheral cell, and located between the first and second power supply wiring regions and between these power supply wiring regions. As a result, the noise generated by the semiconductor integrated circuit can be appropriately suppressed by a simpler configuration in the vicinity of the noise source in the peripheral cell portion inside the semiconductor integrated circuit, and it is flexible for various uses of the peripheral cell It is possible to obtain a semiconductor integrated circuit capable of handling.

According to the semiconductor integrated circuit of the fourth aspect, in the semiconductor integrated circuit having peripheral cells for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit, the first power supply wiring portion A second power supply wiring portion provided in parallel with the first power supply wiring portion is provided in the peripheral cell, and a logic circuit portion having the input / output signal transmission function and a capacitance portion having a noise suppression function are provided. Are provided in parallel with each other and connected between the first power supply wiring portion and the second power supply wiring portion provided in the peripheral cell.
A semiconductor integrated circuit that can appropriately suppress noise generated by the semiconductor integrated circuit in a peripheral cell portion inside the semiconductor integrated circuit at a location close to the noise source by a simpler configuration and can flexibly cope with various uses of the peripheral cell. be able to.

According to the semiconductor integrated circuit of the fifth aspect, in the semiconductor integrated circuit having peripheral cells for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit, the first power supply wiring portion A second power supply wiring portion provided in parallel with the first power supply wiring portion is provided in the peripheral cell, and a logic circuit portion having the input / output signal transmission function and a capacitance portion having a noise suppression function are provided. Provided between the first power supply wiring portion and the second power supply wiring portion provided in the peripheral cell and juxtaposed to each other, and the first and second power supply wiring regions and the power supply wirings are provided. Since it is located between the regions, the noise generated by the semiconductor integrated circuit can be appropriately suppressed by a simpler configuration in the vicinity of the noise source in the peripheral cell portion inside the semiconductor integrated circuit, and the peripheral cell It is possible to obtain a semiconductor integrated circuit that can respond flexibly to a variety of applications.

According to the semiconductor integrated circuit of the sixth aspect, in the semiconductor integrated circuit provided with the peripheral cells for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit, the VDD wiring portion and the VDD Providing a GND wiring portion arranged in parallel with the wiring portion in the peripheral cell;
The logic circuit portion having the input / output signal transmission function and the capacitance portion having the noise suppression function are juxtaposed with each other and provided between the VDD wiring portion and the GND wiring portion provided in the peripheral cell. Therefore, the noise generated by the semiconductor integrated circuit can be appropriately suppressed by a simpler configuration in the vicinity of the noise source in the peripheral cell 1 inside the semiconductor integrated circuit, and the semiconductor integrated circuit can flexibly cope with various uses of the peripheral cell. A circuit can be obtained.

According to the semiconductor integrated circuit of the seventh invention, in a semiconductor integrated circuit having peripheral cells for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit, a VDD wiring portion and the VDD Providing a GND wiring portion arranged in parallel with the wiring portion in the peripheral cell;
A logic circuit portion having an input / output signal transmission function and a capacitance portion having a noise suppression function are juxtaposed with each other and provided between the VDD wiring portion and the GND wiring portion provided in the peripheral cell; In addition, since the VDD wiring area, the GND wiring area, and the wiring area are located between these wiring areas, noise generated in the semiconductor integrated circuit can be further simplified in the peripheral cell 1 inside the semiconductor integrated circuit at a location close to the noise source. Accordingly, it is possible to obtain a semiconductor integrated circuit which can be appropriately suppressed and can flexibly cope with various uses of the peripheral cell.

According to the semiconductor integrated circuit of the eighth invention, in the semiconductor integrated circuits of the first to fourth inventions, the pad and the input / output terminal connected to the peripheral cell via the logic circuit portion Is provided, noise generated in the semiconductor integrated circuit can be appropriately suppressed in a portion of the peripheral cell inside the semiconductor integrated circuit in the vicinity of the noise generation source, and it is possible to flexibly cope with various uses of the peripheral cell, and a logic circuit is provided. It is possible to obtain a semiconductor integrated circuit having an input / output terminal that contributes to the input / output signal transmission function of a portion.

According to the semiconductor integrated circuit of the ninth aspect, an n-type semiconductor region formed in a p-type semiconductor region as a capacitance portion of the peripheral cell, and the n-type semiconductor region is interposed through a dielectric. Since the capacitance constituted by the electrodes electrically coupled is provided, the capacitance portion of the peripheral cell can be appropriately and easily provided with a simple configuration.

According to the semiconductor integrated circuit of the tenth aspect, an n-type semiconductor region formed in a p-type well as a capacitance portion of the peripheral cell and an electrical connection between the n-type semiconductor region through a dielectric. Since the capacitance constituted by the electrode coupled to the cell is provided, the capacitance portion of the peripheral cell can be appropriately and easily provided with a simple configuration.

According to the semiconductor integrated circuit of the eleventh aspect, the N-channel MOS is used as the capacitance of the peripheral cell.
Connect the gate electrode of the transistor to the VDD wiring part,
Since the one in which the source / drain is connected to the GND wiring portion is used, the capacitance portion of the peripheral cell can be appropriately and easily provided with a simple configuration.

According to the semiconductor integrated circuit of the twelfth aspect, a MOS capacitor comprising an n-type semiconductor region formed on a p-type semiconductor substrate, a gate oxide film, and a gate electrode as a capacitance portion of the peripheral cell. Is provided, the capacitance portion of the peripheral cell can be appropriately and easily provided with a simple configuration.

According to the semiconductor integrated circuit of the thirteenth aspect, the first gate electrode, the second gate electrode, and the first gate electrode are disposed between the first and second gate electrodes as the capacitance portion of the peripheral cell. Since the capacitance constituted by the insulating film provided is provided, the capacitance portion of the peripheral cell can be appropriately and easily provided with a simple configuration.

According to the method of manufacturing a semiconductor integrated circuit of the fourteenth aspect, the logic having the peripheral cell for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit and having the input / output signal transmission function is provided. Forming a semiconductor region and an electrode constituting the logic circuit portion in a semiconductor integrated circuit in which a circuit portion and a capacitor portion having a noise suppression function are provided in the peripheral cell; and Since the method includes a step of forming a dielectric element and an electrode to be configured, and a wiring step of electrically connecting the components of the logic circuit portion and the capacitor portion, it is flexible according to various uses of the peripheral cell 1. And a method of manufacturing a semiconductor integrated circuit that can cope with the above.

According to the method of manufacturing a semiconductor integrated circuit according to the fifteenth aspect, the logic having the peripheral cells for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit and having the input / output signal transmission function is provided. A circuit portion and a capacitor portion having a noise suppressing function, in a semiconductor integrated circuit provided in the peripheral cell, a logic circuit portion forming step of forming a semiconductor region and an electrode constituting the logic circuit portion; Forming a capacitance element for forming a dielectric element and an electrode constituting the capacitance part, and electrically connecting the components of the logic circuit part and the capacitance part after the logic circuit part formation step and the capacitance part formation step. Since the connecting wiring process is performed, it is possible to obtain a method of manufacturing a semiconductor integrated circuit that can flexibly respond to various uses of the peripheral cell 1.

According to the method of manufacturing a semiconductor integrated circuit according to the sixteenth aspect of the present invention, there is provided a logic device having peripheral cells for transmitting input / output signals between the outside and the internal logic circuit of the semiconductor integrated circuit, and having the input / output signal transmission function. A circuit part and a capacitor part having a noise suppression function are provided in a peripheral integrated cell. In a method for manufacturing a semiconductor integrated circuit, a field step of forming a field oxide film on a p-type semiconductor substrate, and an n step of forming an n well A well formation step, a p-well formation step of forming a p-well, a gate electrode formation step of forming a gate electrode, an n-source / drain formation step of forming an n-source / drain, and a p-source formation of a p-source / drain. A source / drain formation step, wherein the n-well formation step, the p-well formation step, the gate electrode formation step, the n-source / drain type Since the method includes a wiring step of electrically connecting each element formed by the step and the p source / drain forming step, a method of manufacturing a semiconductor integrated circuit that can flexibly cope with various uses of the peripheral cell 1 is provided. Obtainable.

According to the method of manufacturing a semiconductor integrated circuit according to the seventeenth aspect of the present invention, the logic having the peripheral cell for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit and having the input / output signal transmission function is provided. A circuit part and a capacitor part having a noise suppression function are provided in a peripheral integrated cell. In a method for manufacturing a semiconductor integrated circuit, a field step of forming a field oxide film on a p-type semiconductor substrate, and an n step of forming an n well A well formation step, a p-well formation step of forming a p-well, a gate electrode formation step of forming a gate electrode, an n-source / drain formation step of forming an n-source / drain, and a p-source formation of a p-source / drain. A source / drain formation step, wherein the n-well formation step, the p-well formation step, the gate electrode formation step, the n-source / drain type Includes a wiring step for electrically connecting the element formed by the process and p source / drain forming step, the n-well forming step, p-well forming step,
Since the wiring step is performed after the gate electrode forming step, the n source / drain forming step, and the p source / drain forming step, the manufacture of a semiconductor integrated circuit that can flexibly respond to various uses of the peripheral cell 1 You can get the way.

According to the method of manufacturing a semiconductor integrated circuit according to the eighteenth aspect of the invention, there is provided a logic circuit having peripheral cells for transmitting input / output signals between the outside and the internal logic circuit of the semiconductor integrated circuit, and having the input / output signal transmission function. A circuit part and a capacitor part having a noise suppression function are provided in a peripheral integrated cell. In a method for manufacturing a semiconductor integrated circuit, a field step of forming a field oxide film on a p-type semiconductor substrate, and an n step of forming an n well A well formation step, a p-well formation step of forming a p-well, a gate electrode formation step of forming a gate electrode, an n-source / drain formation step of forming an n-source / drain, and a p-source formation of a p-source / drain. A source / drain forming step, a contact hole forming step of forming a contact hole, and a first wiring for forming a first layer wiring. And a step, v to form a via hole
Since the method includes the step of forming an ia hole and the second wiring step of wiring the second layer, it is possible to obtain a method of manufacturing a semiconductor integrated circuit that can flexibly respond to various uses of the peripheral cell 1. it can.

According to the method of manufacturing a semiconductor integrated circuit according to the nineteenth aspect of the present invention, there is provided a logic having the peripheral cells for transmitting input / output signals between the outside of the semiconductor integrated circuit and the internal logic circuit, and having the input / output signal transmission function. A circuit part and a capacitor part having a noise suppression function are provided in a peripheral integrated cell. In a method for manufacturing a semiconductor integrated circuit, a field step of forming a field oxide film on a p-type semiconductor substrate, and an n step of forming an n well A well formation step, a p-well formation step of forming a p-well, a gate electrode formation step of forming a gate electrode, an n-source / drain formation step of forming an n-source / drain, and a p-source formation of a p-source / drain. A source / drain forming step, a contact hole forming step of forming a contact hole, and a first wiring for forming a first layer wiring. And a step, v to form a via hole
an ia hole forming step and a second wiring step of forming a second layer wiring, wherein the field step, the n well forming step, the p well forming step, the gate electrode forming step, the n source / drain forming step, and the p source / Drain forming step, contact hole forming step, first wiring step,
Since the via hole forming step and the second wiring step are performed, a method of manufacturing a semiconductor integrated circuit that can flexibly respond to various uses of the peripheral cell 1 can be obtained.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a plan view of a peripheral cell having a built-in capacitor and an input / output circuit with the outside of the semiconductor integrated circuit according to an embodiment of the present invention, which is arranged in the semiconductor integrated circuit of FIG.

FIG. 3 is a plan view of a capacitor arranged in a capacitor region of a peripheral cell in FIG. 2;

FIG. 4 is a sectional structural view taken along line IV-IV of the capacitor of FIG. 3;

FIG. 5 is a sectional structural view taken along line VV of the capacitor in FIG. 3;

FIG. 6 is a circuit diagram illustrating the structure of the capacitor in FIG. 3;

FIG. 7 is a plan view of a peripheral cell logic circuit region of the peripheral cell of FIG. 2;

8 is a view showing a VI of a peripheral cell logic circuit area of the peripheral cell of FIG. 2;
It is sectional drawing in the II-VIII line.

9 is an IX of a peripheral cell logic circuit area of the peripheral cell of FIG. 2;
It is sectional drawing in the -IX line.

FIG. 10 is an outline of a semiconductor integrated circuit manufacturing process flow (master step).

FIG. 11 is an outline of a semiconductor integrated circuit manufacturing process flow (slice step).

FIG. 12 is a plan view of a capacitor having a structure different from that of FIG. 3 showing the second embodiment according to the present invention;

13 is a sectional structural view taken along line XIII-XIII of the capacitor in FIG.

14 is a sectional structural view taken along line XIV-XIV of the capacitor of FIG.

FIG. 15 shows a third embodiment according to the present invention;
FIG. 13 is a plan view of a capacitor having a structure different from that of FIG. 12.

16 is a sectional structural view taken along line XVI-XVI of the capacitor in FIG.

17 is a sectional structural view taken along line XVII-XVII of the capacitor of FIG.

FIG. 18 is a schematic diagram illustrating a conventional noise countermeasure for a semiconductor integrated circuit.

[Explanation of symbols]

A semiconductor chip, 1 peripheral cell, 3a, 3b peripheral cell column, 4a VDD wiring, 4b GND wiring, 6 internal logic circuit, 10 capacitance area, 11 peripheral cell logic circuit area, 12 wiring, 13 peripheral cell input / output signal terminals , 1
4 gate electrode, 15 n-type semiconductor region (n source / drain), 16 via hole, 17 contact hole, 18 metal wiring, 20 gate oxide film, 21 p-type semiconductor substrate, 19, 24 p-well on substrate 21, n Wells, 23p source / drain regions, 36 field oxide.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F038 AC03 AC08 AC14 BH03 BH19 CA02 CA03 CA05 CA10 CD02 EZ20 5F048 AB06 AB07 AC03 BB01 BE03 BF16 CC05 CC19 5F064 CC12 CC23 DD05 DD25 DD33 EE27 EE45 EE52

Claims (19)

[Claims] 1. A semiconductor integrated circuit having a peripheral cell for transmitting an input / output signal between the outside of the semiconductor integrated circuit and an internal logic circuit, wherein the logic circuit portion has the input / output signal transmission function, and has a noise suppression function. A semiconductor integrated circuit, wherein a capacitor portion is provided in the peripheral cell. 2. A semiconductor integrated circuit having a peripheral cell for transmitting input / output signals between the outside of the semiconductor integrated circuit and an internal logic circuit, wherein a first power supply wiring portion and a first power supply wiring portion are juxtaposed. And a logic circuit portion having an input / output signal transmission function and a capacitance portion having a noise suppression function are provided in the peripheral cell. A semiconductor integrated circuit provided between a power supply wiring portion and a second power supply wiring portion. 3. A semiconductor integrated circuit having peripheral cells for transmitting input / output signals between the outside of the semiconductor integrated circuit and an internal logic circuit, wherein the first power supply wiring portion and the first power supply wiring portion are juxtaposed. And a logic circuit portion having an input / output signal transmission function and a capacitance portion having a noise suppression function are provided in the peripheral cell. A semiconductor integrated circuit which is provided so as to be connected between a power supply wiring portion and a second power supply wiring portion, and is located between the first and second power supply wiring regions and between these power supply wiring regions. 4. A semiconductor integrated circuit having peripheral cells for transmitting input / output signals between the outside of the semiconductor integrated circuit and an internal logic circuit, wherein the first power supply wiring portion and the first power supply wiring portion are arranged in parallel. And a logic circuit portion having an input / output signal transmission function and a capacitance portion having a noise suppression function are provided side by side with each other and provided in the peripheral cell. A semiconductor integrated circuit provided between the first power supply wiring portion and the second power supply wiring portion. 5. A semiconductor integrated circuit having a peripheral cell for transmitting an input / output signal between the outside of the semiconductor integrated circuit and an internal logic circuit, wherein the first power supply wiring portion and the first power supply wiring portion are juxtaposed. And a logic circuit portion having an input / output signal transmission function and a capacitance portion having a noise suppression function are provided side by side with each other and provided in the peripheral cell. And provided between the first power supply wiring portion and the second power supply wiring portion, and located between the first and second power supply wiring regions and between these power supply wiring regions. Semiconductor integrated circuit. 6. A semiconductor integrated circuit having a peripheral cell for transmitting an input / output signal between the outside of the semiconductor integrated circuit and an internal logic circuit, wherein a VDD wiring portion, a GND wiring portion juxtaposed to the VDD wiring portion, Are provided in the peripheral cell, and the logic circuit portion having the input / output signal transmission function and the capacitance portion having the noise suppression function are juxtaposed with each other, and the VDD wiring portion provided in the peripheral cell is connected to the GND.
A semiconductor integrated circuit provided to be connected between a D wiring portion. 7. A semiconductor integrated circuit having a peripheral cell for transmitting an input / output signal between the outside of the semiconductor integrated circuit and an internal logic circuit, wherein a VDD wiring portion, a GND wiring portion juxtaposed to the VDD wiring portion, Are provided in the peripheral cell, and the logic circuit portion having the input / output signal transmission function and the capacitance portion having the noise suppression function are juxtaposed with each other, and the VDD wiring portion provided in the peripheral cell is connected to the GND.
A semiconductor integrated circuit which is provided so as to be connected to a D wiring portion, and is located between the VDD wiring region, the GND wiring region, and these wiring regions. 8. The semiconductor integrated circuit according to claim 1, wherein a pad connected to the peripheral cell via the logic circuit portion and an input / output terminal are provided in the peripheral cell. 9. A capacitance portion of the peripheral cell, comprising an n-type semiconductor region formed in a p-type semiconductor region, and an electrode electrically coupled to the n-type semiconductor region via a dielectric. 9. The semiconductor integrated circuit according to claim 1, further comprising a capacitor. 10. A capacitor constituted by an n-type semiconductor region formed in a p-well and an electrode electrically coupled to the n-type semiconductor region via a dielectric is provided as a capacitance portion of the peripheral cell. 9. The semiconductor integrated circuit according to claim 1, wherein: 11. A capacitor in which a gate electrode of an N-channel MOS transistor is connected to a VDD wiring portion and a source / drain is connected to a GND wiring portion is used as a capacitance portion of the peripheral cell. 3. The semiconductor integrated circuit according to claim 1. 12. A capacitor comprising a MOS capacitor comprising an n-type semiconductor region formed on a p-type semiconductor substrate, a gate oxide film and a gate electrode, as a capacitance portion of the peripheral cell. A semiconductor integrated circuit according to claim 1. 13. The method according to claim 1, wherein the first capacitor is a first capacitor.
Gate electrode, a second gate electrode, and the first and second gate electrodes.
9. The semiconductor integrated circuit according to claim 1, further comprising: a capacitor comprising an insulating film disposed between said gate electrodes. 14. A logic circuit part having a peripheral cell for transmitting an input / output signal between the outside of a semiconductor integrated circuit and an internal logic circuit, said logic circuit part having an input / output signal transmission function, and a capacitance part having a noise suppression function, A method for manufacturing a semiconductor integrated circuit provided in the peripheral cell, wherein a step of forming a semiconductor region and an electrode constituting the logic circuit portion, a step of forming a dielectric element and an electrode constituting the capacitance portion, A wiring step of electrically connecting constituent elements of a logic circuit portion and a capacitance portion. 15. A logic circuit portion having a peripheral cell for transmitting an input / output signal between the outside of a semiconductor integrated circuit and an internal logic circuit, the logic circuit portion having an input / output signal transmission function, and a capacitance portion having a noise suppression function, In a method of manufacturing a semiconductor integrated circuit provided in the peripheral cell, a logic circuit portion forming step of forming a semiconductor region and an electrode forming the logic circuit portion, and a dielectric element and an electrode forming the capacitance portion are formed. A semiconductor integrated circuit comprising: a capacitance portion forming step; and after the logic circuit portion forming step and the capacitor portion forming step, a wiring step of electrically connecting components of the logic circuit portion and the capacitance portion is performed. Manufacturing method. 16. A logic circuit portion having a peripheral cell for transmitting an input / output signal between the outside of a semiconductor integrated circuit and an internal logic circuit and having a function of transmitting and receiving an input / output signal, and a capacitance portion having a function of suppressing noise. A step of forming a field oxide film on a p-type semiconductor substrate, a step of forming an n-well, and a step of forming a p-well in a step of manufacturing a semiconductor integrated circuit provided in the peripheral cell. A gate electrode forming step of forming a gate electrode, an n source / drain forming step of forming an n source / drain, and a p source / drain forming step of forming a p source / drain. Process, p-well formation process, gate electrode formation process, n
A method for manufacturing a semiconductor integrated circuit, comprising a wiring step of electrically connecting each element formed by a source / drain formation step and a p source / drain formation step. 17. A logic circuit having a peripheral cell for transmitting an input / output signal between the outside of a semiconductor integrated circuit and an internal logic circuit and having a function of transmitting and receiving an input / output signal, and a capacitor having a function of suppressing noise. A step of forming a field oxide film on a p-type semiconductor substrate, a step of forming an n-well, and a step of forming a p-well in a step of manufacturing a semiconductor integrated circuit provided in the peripheral cell. A gate electrode forming step of forming a gate electrode, an n source / drain forming step of forming an n source / drain, and a p source / drain forming step of forming a p source / drain. Process, p-well formation process, gate electrode formation process, n
A wiring step of electrically connecting each element formed by the source / drain formation step and the p source / drain formation step, the n-well formation step, the p-well formation step, the gate electrode formation step, the n-source / drain formation A method of manufacturing a semiconductor integrated circuit, wherein the wiring step is performed after the step and the p source / drain forming step. 18. A logic circuit having a peripheral cell for transmitting an input / output signal between the outside of a semiconductor integrated circuit and an internal logic circuit and having a function of transmitting / receiving an input / output signal, and a capacitor having a function of suppressing noise. A step of forming a field oxide film on a p-type semiconductor substrate, a step of forming an n-well, and a step of forming a p-well in a step of manufacturing a semiconductor integrated circuit provided in the peripheral cell. Forming a gate electrode, forming a gate electrode, forming an n source / drain, forming an n source / drain, forming a p source / drain, and forming a p source / drain, and forming a contact hole. Forming a contact hole, forming a first layer of wiring, forming a via hole, and forming a via hole. And a second wiring step of performing wiring of a second layer. 19. A logic circuit portion having a peripheral cell for transmitting input / output signals between the outside of a semiconductor integrated circuit and an internal logic circuit, the logic circuit portion having the input / output signal transmission function, and the capacitance portion having a noise suppression function, A step of forming a field oxide film on a p-type semiconductor substrate, a step of forming an n-well, and a step of forming a p-well in a step of manufacturing a semiconductor integrated circuit provided in the peripheral cell. Forming a gate electrode, forming a gate electrode, forming an n source / drain, forming an n source / drain, forming a p source / drain, and forming a p source / drain, and forming a contact hole. Forming a contact hole, forming a first layer of wiring, forming a via hole, and forming a via hole. And a second wiring step of forming a second layer wiring, the field step, the n-well forming step, the p-well forming step, the gate electrode forming step, the n-source / drain forming step, and the p-source / drain forming step. After the steps, a contact hole forming step, a first wiring step,
A method of manufacturing a semiconductor integrated circuit, comprising performing a via hole forming step and a second wiring step.