JP2018195628A - Wiring board manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a decrease in reliability. SOLUTION: A pair of polishing heads 61 and 62 are supported so as to face each other's polishing surfaces 61a and 62a. The wiring board 10a is arranged between the pair of polishing heads 61 and 62. The wiring board 10a has a protruding electrode 41 on the upper surface and a protective layer 52 on the lower surface. Then, the pair of polishing heads 61 and 62 are rotated in opposite directions and relatively moved toward the wiring board 10a, and the protrusion electrode 41 on the upper surface of the wiring board 10a and the protective layer 52 on the lower surface are simultaneously polished. [Selection diagram] Fig. 4

Description

  The present invention relates to a method for manufacturing a wiring board.

  Conventionally, a semiconductor device in which a semiconductor chip is mounted on a wiring board is known. The semiconductor chip is connected to the wiring board in a face-down state, for example. Due to the high integration of semiconductor chips, the pad spacing of semiconductor chips is becoming narrower. For this reason, various wiring boards having protruding electrodes connected to the semiconductor chip have been proposed (see, for example, Patent Documents 1 and 2).

Japanese Patent Laid-Open No. 2005-101068 JP 2008-60122 A

  By the way, if there is a variation in the height of the protruding electrode in the wiring substrate, a variation in the connection between the wiring substrate and the semiconductor chip occurs, and the connection reliability decreases. For this reason, suppression of a decrease in connection reliability is required.

  According to one aspect of the present invention, a method for manufacturing a wiring board includes a first surface and a second surface opposite to the first surface, between a pair of polishing heads arranged so that the polishing surfaces face each other. A wiring board having a protruding electrode on the first surface and a protective layer on the second surface, and rotating the pair of polishing heads in opposite directions to each other. A step of polishing the protruding electrode and the protective layer simultaneously;

  According to one aspect of the present invention, it is possible to suppress a decrease in reliability.

Sectional drawing which shows the manufacturing method of a wiring board. (A) (b) is a schematic sectional drawing which shows the manufacturing method of a wiring board. (A) (b) is a schematic sectional drawing which shows the manufacturing method of a wiring board. (A) (b) is a schematic sectional drawing which shows the manufacturing method of a wiring board. (A) (b) is a schematic sectional drawing which shows the manufacturing method of a wiring board. (A) is a schematic sectional drawing which shows the manufacturing method of a wiring board, (b) is a schematic sectional drawing which shows a semiconductor device. (A) is a schematic sectional drawing which shows the manufacturing method of the wiring board of a comparative example, (b) is a schematic sectional drawing which shows the semiconductor device of a comparative example.

Hereinafter, each embodiment will be described with reference to the accompanying drawings.
In the accompanying drawings, for convenience, there is a case where a characteristic part is enlarged to make the characteristic easy to understand, and a dimensional ratio of each component is not always the same as an actual one. In the cross-sectional view, in order to make the cross-sectional structure of each member easy to understand, the hatching of some members is shown in place of a satin pattern, and the hatching of some members is omitted.

(Manufacturing method of this embodiment)
FIG. 1 shows a cross section of a wiring board 10 at a stage prior to forming protruding electrodes.
As shown in FIG. 1, a core substrate 11 having a predetermined thickness is prepared. The material of the core substrate 11 is, for example, a so-called glass epoxy substrate in which a glass cloth (glass woven fabric) that is a reinforcing material is impregnated with a thermosetting insulating resin mainly composed of an epoxy resin and cured. As the reinforcing material, a woven or nonwoven fabric of glass or aramid, a liquid crystal polymer (LCP) woven fabric or an LCP nonwoven fabric can be used. The insulating resin is not limited to an epoxy resin, and a polyimide resin or a cyanate resin can be used.

  Next, the through hole 11X is formed in the core substrate 11. For example, a laser processing machine or a drilling machine can be used to form the through hole 11X. For example, when the through hole 11X is formed by a laser processing machine, a desmear process is performed to remove resin smear remaining in the through hole 11X. As the desmear treatment, for example, potassium permanganate can be used.

  Next, the through electrode 12 is formed in the through hole 11 </ b> X, and the wiring layers 13 and 14 are formed on the upper surface and the lower surface of the core substrate 11. For example, a seed layer is formed on the surface of the core substrate 11 by an electroless plating method (electroless copper plating method). The through electrode 12 is formed in the through hole 11X by an electrolytic plating method (electrolytic copper plating method) using the seed layer as a power feeding electrode. Then, for example, the wiring layers 13 and 14 are formed by a subtractive method. Note that the through electrode 12 may be formed using a conductive paste.

  Next, insulating layers 21 and 31 covering the wiring layers 13 and 14 are formed. For example, as a material of the insulating layers 21 and 31, for example, an organic resin such as an epoxy resin or a polyimide resin, or a resin material in which a filler such as silica or alumina is mixed with these resins can be used. The insulating layers 21 and 31 are obtained, for example, by vacuum laminating a resin film and curing by heating. The insulating layers 21 and 31 may be formed by applying a paste-like or liquid resin and heating.

  Next, the wiring layer 22 on the upper surface of the insulating layer 21 and the wiring layer 32 on the lower surface of the insulating layer 31 are formed. Openings are formed in the insulating layers 21 and 31, respectively, and desmear treatment is performed if necessary, and then wiring layers 22 and 32 are formed by, for example, a semi-additive method. The wiring layer 22 has a via wiring penetrating the insulating layer 21 in the thickness direction and a wiring pattern connected to the wiring layer 13 through the via wiring. The wiring layer 32 includes a via wiring penetrating the insulating layer 31 in the thickness direction, and a wiring pattern connected to the wiring layer 14 via the via wiring.

  Next, insulating layers 23 and 33 covering the wiring layers 22 and 32 are formed. For example, as the material of the insulating layers 23 and 33, for example, an organic resin such as an epoxy resin or a polyimide resin, or a resin material in which a filler such as silica or alumina is mixed with these resins can be used. The insulating layers 23 and 33 can be obtained by, for example, vacuum laminating a resin film and curing by heating. The insulating layers 23 and 33 may be formed by applying a paste-like or liquid resin and heating.

  Next, the wiring layer 24 on the upper surface of the insulating layer 23 and the wiring layer 34 on the lower surface of the insulating layer 33 are formed. Openings are formed in the insulating layers 23 and 33, respectively, and desmear treatment is performed if necessary, and then wiring layers 24 and 34 are formed by, for example, a semi-additive method. The wiring layer 24 includes a via wiring penetrating the insulating layer 23 in the thickness direction and a wiring pattern connected to the wiring layer 22 through the via wiring. The wiring layer 34 includes a via wiring that penetrates the insulating layer 33 in the thickness direction, and a wiring pattern that is connected to the wiring layer 32 via the via wiring.

  Next, a solder resist layer 25 covering a part of the insulating layer 23 and the wiring layer 24 and a solder resist layer 35 covering a part of the insulating layer 33 and the wiring layer 34 are formed. The solder resist layer 25 has an opening 25 </ b> X that exposes a part of the upper surface of the wiring layer 24. The solder resist layer 35 has an opening 35 </ b> X that exposes a part of the lower surface of the wiring layer 34.

  The solder resist layer 25 is obtained, for example, by laminating a photosensitive solder resist film or applying a liquid solder resist, and exposing and developing the resist by a photolithography method and patterning the resist into a required shape. Similarly, the solder resist layer 35 is formed by, for example, laminating a photosensitive solder resist film or applying a liquid solder resist, and exposing and developing the resist by a photolithography method and patterning the resist into a desired shape. can get.

  Next, a seed layer (not shown) that covers the surface of the solder resist layer 25 and the upper surface of the wiring layer 24 exposed by the opening 25X is formed. As a material for the seed layer, for example, copper or a copper alloy can be used. The seed layer can be formed by, for example, a sputtering method or an electroless plating method. Note that the seed layer may be formed of a plurality of layers. For example, a metal layer such as titanium (Ti) or chromium (Cr) and a metal layer such as copper, nickel (Ni), or a copper nickel alloy (Cu—Ni) can be used.

  As shown in FIG. 2A, resist layers 26 and 36 are formed. The resist layer 26 has an opening 26X at a position corresponding to a protruding electrode to be formed next. For the resist layer 26, for example, a material having resistance to the next plating step can be used. For example, as the resist layer 26, for example, a photosensitive dry film resist (for example, a dry film resist such as a novolac resin or an acrylic resin) can be used. The solder resist layer 25 and the wiring layer 24 are laminated with a thermocompression-bonded dry film, and the dry film is patterned by a photolithography method to form a resist layer 26 having an opening 26X.

  The resist layer 36 is formed so as to cover the surface of the solder resist layer 35 and the lower surface of the wiring layer 34 exposed from the opening 35 </ b> X of the solder resist layer 35. For the resist layer 36, for example, a material having resistance to the next plating step can be used. For example, as the resist layer 36, for example, a photosensitive dry film resist (for example, a dry film resist such as a novolac resin or an acrylic resin) can be used. The solder resist layer 35 and the wiring layer 34 are laminated by a hot-pressed dry film to form a resist layer 36.

  As shown in FIG. 2B, the protruding electrode 41 is formed in the opening 26 </ b> X of the resist layer 26. As a material of the protruding electrode 41, for example, copper (Cu) or a copper alloy can be used. The protruding electrode 41 can be formed by depositing and growing a plating metal on the seed layer exposed in the opening 26X of the resist layer 26 by, for example, an electrolytic plating method using the seed layer as a power supply electrode.

  As shown in FIG. 3A, the resist layers 26 and 36 (see FIG. 2B) are removed. The resist layers 26 and 36 can be removed using, for example, an ashing process or an alkaline stripping solution.

Through the above steps, the wiring substrate 10a having the protruding electrodes 41 on the upper surface (first surface) can be formed.
The wiring board 10a formed by the above process has a non-uniform thickness. This non-uniformity of the thickness is such that the wiring layers 13, 14, 22, 24, 32, 34 are not dense, the core substrate 11 and the insulating layers 21, 23, 31, 33 are non-uniform in thickness, etc. Due to factors. This non-uniform thickness causes undulations on the upper and lower surfaces of the wiring board 10a. The undulation generated in the wiring board 10a causes variations in the height of the protruding electrodes 41 formed on the wiring board 10a. In order to reduce the variation in the height of the protruding electrode 41, the protruding electrode 41 is polished.

  As shown in FIG. 3B, protective layers 51 and 52 are formed on the upper surface (first surface) and the lower surface (second surface) of the wiring board 10a. The protective layer 51 is formed so as to cover the surface of the solder resist layer 25 and expose the upper end of the bump electrode 41. The protective layer 52 is formed so as to cover the surface of the solder resist layer 35 and the surface of the wiring layer 34 exposed at the opening 35X of the solder resist layer 35, that is, cover the entire surface of the wiring substrate 10a.

  Note that the resist layers 26 and 36 shown in FIG. 2A can be used continuously without being removed and used as the protective layers 51 and 52. In this case, a protective layer (resist layer 36) on the lower surface (second surface) side of the wiring substrate 10a is formed before the protruding electrodes 41 on the upper surface of the wiring substrate 10a.

  As shown in FIG. 4A, a polishing apparatus having a pair of polishing heads 61 and 62 is used. The pair of polishing heads 61 and 62 are supported so that the polishing surfaces 61a and 62a face each other. Between the pair of polishing heads 61 and 62, the wiring board 10a on which the protective layers 51 and 52 are formed as described above is disposed. Then, the pair of polishing heads 61 and 62 are rotated in opposite directions by a driving source (for example, a motor) (not shown) and moved relatively toward the wiring board 10a. For example, the wiring substrate 10a is placed with the protective layer 52 facing the polishing surface 62a of the polishing head 62, and the polishing head 61 is lowered toward the wiring substrate 10a. By these polishing heads 61 and 62, the protruding electrode 41 on the upper surface side of the wiring substrate 10a and the protective layer 52 on the lower surface side of the wiring substrate 10a are simultaneously polished.

  As described above, the thickness of the wiring board 10a is not uniform. For this reason, the pair of polishing heads 61 and 62 polish the thick portion of the wiring board 10a, that is, the upper end of the highest protruding electrode 41 and the lowest protective layer 52. Then, as shown in FIG. 4B, many protruding electrodes 41 of the wiring board 10 a are polished by the polishing head 61. Further, the protective layer 52 in the thick part of the wiring board 10 a is polished by the polishing head 62.

By such a polishing process, a wiring substrate 10b in which the upper ends of a number of protruding electrodes 41 are polished is obtained. In the wiring board 10b, the upper surfaces 41a of many protruding electrodes 41 are located on the same plane. Before the polishing, the thickness of the protective layer 52 covering the solder resist layer 35 is preferably set so that the protective layer 52 remains according to the maximum polishing amount in the wiring board 10a.
In such a polishing process, it is preferable that the protective layer 51 remains on the upper surface of the solder resist layer 25 and the protective layer 52 remains on the lower surface of the solder resist layer 35. Thus, the processing time in the polishing process is set. Is done. In the wiring board 10b, it is preferable that the top surfaces of as many protruding electrodes 41 as possible be on the same plane. However, polishing of the solder resist layer 25 covered with the protective layer 51 is not a preferable mode. For this reason, the processing time of the polishing process is set so that the protective layer 51 remains on the upper surface of the solder resist layer 25. The polishing amount when the bump electrode 41 is polished so that the solder resist layer 25 is not exposed is defined as the maximum polishing amount. At this time, the thickness of the protective layer 52 is set so that the protective layer 52 remains on the lower surface of the solder resist layer 35. For example, the thickness of the protective layer 52 is made larger than the thickness of the protective layer 51. Thereby, the protective layer 52 can remain on the lower surface of the solder resist layer 35.

  As shown in FIG. 5B, the protective layers 51 and 52 (see FIG. 5A) are removed. The protective layers 51 and 52 can be removed using, for example, an ashing process or an alkaline stripping solution.

  As shown in FIG. 6A, an individual wiring board 10c is obtained. For example, the wiring board 10b shown in FIG. 5B is cut at a position indicated by a one-dot chain line using, for example, a dicing blade to obtain individual wiring boards 10c shown in FIG. 6A.

  As shown in FIG. 6B, the semiconductor chip 100 adsorbed by a bonding tool (collet) (not shown) is mounted face down on the wiring board 10c. At this time, solder bumps 101 are formed on the connection terminals of the semiconductor chip 100. The semiconductor chip 100 is pressed toward the wiring board 10c while heating the semiconductor chip 100 and the wiring board 10c. As a result, the solder bumps 101 are melted and the terminals of the semiconductor chip 100 are connected to the protruding electrodes 41. At this time, the upper surfaces 41a of the plurality of protruding electrodes 41 of the wiring board 10c are flush with each other, that is, on one plane. For this reason, each terminal of the semiconductor chip 100 can be connected to the plurality of protruding electrodes 41 of the wiring board 10a. Note that the semiconductor chip 100 may be tilted by a bonding tool in accordance with the inclination of the upper surfaces 41a of the plurality of protruding electrodes 41 of the wiring substrate 10c, and the semiconductor chip 100 may be parallel to the upper surfaces 41a of the protruding electrodes 41.

(Function)
First, a manufacturing method of a comparative example and a wiring board formed by the manufacturing method will be described. In addition, the same code | symbol is attached | subjected about the same member as the above-mentioned embodiment, and the one part or all part of the description is abbreviate | omitted.

(Comparative example)
FIG. 7A shows the manufacturing process of the comparative example. The polishing apparatus of this comparative example has a support table 201 and a polishing head 202. The support table 201 is, for example, a substrate suction stage that holds the wiring substrate 10a. The wiring board 10 a is sucked and fixed by the support table 201. Then, the polishing head 202 is lowered toward the wiring substrate 10a while rotating.

  As described above, the wiring board 10a has a non-uniform thickness in one wiring board 10a. For this reason, the waviness has arisen in the upper surface and lower surface of the wiring board 10a, respectively. When the lower surface of the wiring board 10a is sucked and held by the support base 201, the waviness of the upper surface of the wiring board 10a is emphasized, that is, larger than the waviness when not sucking and holding. In the wiring substrate 10a in which the undulation is emphasized in this way, a large number of protruding electrodes 41 that are not polished by the polishing head 202 are generated. If all the protruding electrodes 41 of the wiring board 10a are to be polished, the protective layer 51 and the solder resist layer 25 will be polished.

  As shown in FIG. 7B, a wiring substrate 10d obtained by separating the wiring substrate 10a polished by the polishing method of the comparative example is obtained. Then, the semiconductor chip 100 is mounted on the separated wiring board 10d. However, in the wiring substrate 10d, a part of the plurality of protruding electrodes 41 (the protruding electrode 41 at the right end in FIG. 7B) is not polished. For this reason, the solder bump 101 of the mounted semiconductor chip 100 may not be connected to the unpolished protruding electrode 41. That is, this wiring board 10d has low connection reliability.

  In FIG. 7A, the substrate adsorption stage is used as the support table 201. On the other hand, when a support base that does not adsorb is used, it is necessary to fix the wiring board 10a to the support base by the polishing head 202 with a high pressing force so that the wiring board 10a does not rotate together with the polishing head 202. In this case, the lower surface of the wiring substrate 10 a is flattened by the support base 201 by the pressing force of the polishing head 202. For this reason, even if a support base that does not attract is used, the connection reliability is low as described above.

The effect | action by the manufacturing method of said wiring board is demonstrated.
In the present embodiment, as shown in FIGS. 4A and 4B, the pair of polishing heads 61 and 62 are rotated in opposite directions to each other, so that the protruding electrode 41 on the wiring board 10a is opposite to the protruding electrode 41. The protective layer 52 on the side surface is polished. For this reason, the protruding electrode 41 can be polished by the polishing head 61 without flattening the lower surface of the wiring board 10a. Therefore, the number of protruding electrodes 41 to be polished is larger than that in the comparative example. In the wiring substrate 10a where the undulations on the upper and lower surfaces are small, all the protruding electrodes 41 can be polished. Thus, in the present embodiment, the number of protruding electrodes 41 that can be polished increases in the wiring substrate 10 a having the protruding electrodes 41. That is, the number of protruding electrodes 41 that can be used for connecting the semiconductor chip 100 increases. Thereby, the connection reliability in the case of mounting the semiconductor chip 100 can be improved.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The pair of polishing heads 61 and 62 are supported so that the polishing surfaces 61a and 62a face each other. Between the pair of polishing heads 61 and 62, the wiring board 10a having the protruding electrode 41 is disposed. Then, the pair of polishing heads 61 and 62 are rotated in directions opposite to each other and moved relatively toward the wiring board 10a to polish the protruding electrodes 41 of the wiring board 10a. For this reason, the protruding electrode 41 can be polished by the polishing head 61 without flattening the lower surface of the wiring board 10a. Therefore, the number of protruding electrodes 41 to be polished is larger than that in the comparative example. That is, the number of protruding electrodes 41 that can be used for connecting the semiconductor chip 100 increases. Thereby, the connection reliability in the case of mounting the semiconductor chip 100 can be improved.

  (2) The solder resist layer 25 of the wiring board 10a is covered with a protective layer 51. The solder resist layer 25 can be protected by the protective layer 51. Further, the protective layer 51 can prevent the protruding electrode 41 from being inclined during polishing.

(3) The solder resist layer 35 of the wiring board 10a is covered with a protective layer 52. For this reason, the solder resist layer 35 can be protected.
In addition, you may implement the said embodiment in the following aspects.

In the above embodiment, the protective layer 51 on the upper surface side of the wiring board 10a can be omitted. Further, the protective layer 52 on the lower surface side of the wiring board 10a can be omitted.
In the above embodiment, the wiring substrate 10b is separated into individual wiring substrates 10c, and the semiconductor chip 100 is mounted on each wiring substrate 10c. However, after the semiconductor chip 100 is mounted on the wiring substrate 10b, the wiring substrate 10b is separated. You may make it do.

10, 10a, 10b Wiring board 24 Wiring layer (first wiring layer)
25 Solder resist layer (first protective insulating layer)
26 Resist layer (other protective layers)
34 Wiring layer (second wiring layer)
35 Solder resist layer (second protective insulating layer)
36 resist layer (protective layer)
41 Projection electrode 51 Protective layer (other protective layer)
52 Protective layer (Protective layer)
61, 62 Polishing head

Claims (8)

Between a pair of polishing heads arranged so that their polishing surfaces face each other, a first surface and a second surface opposite to the first surface are provided, and a protruding electrode is provided on the first surface. A wiring board having a protective layer on the second surface, and rotating the pair of polishing heads in opposite directions to simultaneously polish the protruding electrodes and the protective layer;
A method of manufacturing a wiring board characterized by the above.   The method for manufacturing a wiring board according to claim 1, wherein the protective layer is formed so as to cover the entire second surface of the wiring board. Forming the protective layer;
Forming the protruding electrode after forming the protective layer;
The method of manufacturing a wiring board according to claim 1, wherein: The wiring board includes a first wiring layer and a first protective insulating layer having an opening that exposes a part of the upper surface of the first wiring layer, and the protruding electrode includes the first protection layer. Connected to the first wiring layer exposed in the opening of the insulating layer;
Before the step of polishing, comprising the step of forming another protective layer covering the first protective insulating layer,
Having a step of removing the other protective layer after the polishing step;
The method for manufacturing a wiring board according to any one of claims 1 to 3.   The method for manufacturing a wiring board according to claim 4, wherein the protective layer is formed thicker than the other protective layer.   6. The method of manufacturing a wiring board according to claim 4, further comprising a step of forming the other protective layer before the step of forming the protruding electrode. The second surface of the wiring board has a second wiring layer and a second protective insulating layer having an opening exposing a part of the lower surface of the second wiring layer,
After the polishing step, the step of removing the protective layer,
The method for manufacturing a wiring board according to claim 1, wherein: The said protective layer is formed so that the lower surface of the said 2nd wiring layer exposed from the said 2nd protective insulating layer and the said 2nd protective insulating layer may be covered. A method for manufacturing a wiring board.