JP2003008228A - Multilayer printed wiring board and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve yield for solder bump formation that responds to the request for pitch narrowing. SOLUTION: This printed wiring board and the method of manufacturing the same are constituted, such that conductor layers and interlayer insulating resin layers are prepared alternately on an insulation substrate, a plated post 30, having a flat surface, is formed on a pad of a conductor circuit formed on an outermost interlayer insulating resin layer, and a solder member 44 is supplied on the plated post surface that is exposed to the outside from a solder resist layer 32.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board in which a conductive post for supporting a solder body such as a solder bump is formed on the outermost conductor layer, and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventional multilayer printed wiring boards are, for example,
It is manufactured by the method as disclosed in JP-A-9-130050. According to the method, first, a roughened layer is formed on the surface of the circuit pattern of the inner layer of the printed wiring board by electroless plating or etching, and then an interlayer insulating resin is applied, exposed and developed by a roll coater or printing. A via hole opening for interlayer conduction is formed, UV curing and main curing are performed to form an interlayer resin insulation layer. further,
The interlayer resin insulation layer is subjected to a roughening treatment with a roughening liquid containing an acid or an oxidizing agent to form a roughened surface, a catalyst such as palladium is attached to the roughened surface, and then the roughened surface is formed. Form a thin electroless plating film.

Then, a pattern is formed on the electroless plated film by a dry film and thickened by electrolytic plating.
The dry film is peeled off with an alkaline solution and etched to form an outer layer circuit pattern. By repeating such processing, a multilayer printed wiring board having a build-up wiring layer is obtained, and solder bumps and BGA and PGA as external terminals are formed on the outermost circuit pattern of the multilayer printed wiring board. ing.

[0004]

In recent years, the wiring width has been reduced to 0.2 in response to the demand for higher frequency and higher functionality of IC chips.
Ultra-fine wiring technology to reduce the size to less than μm has been developed.
In order to electrically connect the chip to the outside, the distance between the bumps arranged on the IC chip has become narrower with the miniaturization of the wiring width. As the pitch between the bumps is narrowed, the pitch between the conductor pads provided on the printed wiring board is also narrowed.

However, when the size of the pads for forming the solder bumps (solder resist opening diameter) is reduced to 100 μm or less in order to meet the demand for such a narrow pitch, when the solder paste is printed on the pads. The opening diameter of the metal mask used for is also small. As a result, the adhesion between the solder resist and the solder paste becomes poor, and the amount of untransferred solder paste increases. As a result, there is a problem that the electrical connectivity and the connection reliability are deteriorated and the yield of solder bump formation is decreased.

Therefore, the present invention has been made to solve the above problems of the prior art, and an object of the present invention is to provide a printed wiring board having an improved yield of solder bump formation. It is in.

[0007]

As a result of intensive studies aimed at achieving the above object, the inventors have formed a conductive post on a conductor pad exposed from a solder resist layer, and solder connected to a semiconductor chip. By adopting a structure in which bumps are formed on the conductive posts, the problem of untransferred solder paste due to the miniaturization of the solder resist opening diameter can be solved, and the solder bump formation yield can be improved. Based on this knowledge, the present invention has been completed, which has the following contents.

That is, according to the present invention, (1) conductor circuits and interlayer resin insulation layers are alternately provided on an insulating substrate, and the outermost conductor circuit formed in the outermost interlayer resin insulation layer is selectively selected. In a multilayer printed wiring board in which a solder resist layer is provided to cover the conductor resist layer, and a solder body is formed on the conductor circuit surface exposed from the solder resist layer, the land of the conductor circuit formed in the outermost interlayer resin insulation layer. A multilayer printed wiring board, characterized in that a conductive post having a flat surface exposed from the solder resist layer is formed on the surface, and a solder body is supplied to the surface of the conductive post.

In the multilayer printed wiring board of the above (1), the conductive posts are preferably formed by plating, and in particular, Cu, Sn, Ni, Ag, Pd,
It is desirable to be formed by at least one kind of plating selected from Au and Pt. The plating is preferably electrolytic plating or electroless plating.

It is desirable that a corrosion resistant film is formed on the exposed surface of the conductive post, and that the film is a plating, and the plating is Au,
More preferably, it is formed from at least one electroless plating selected from Pt, Ag, Ni, Sn and Pd. Furthermore, it is desirable that the exposed surface of the conductive post be subjected to a flattening treatment by polishing.

Further, according to the present invention, (2) conductor layers and interlayer resin insulation layers are alternately provided on an insulating substrate, and a solder resist layer is formed so as to cover the conductor layers formed on the outermost interlayer resin insulation layers. In manufacturing a multilayer printed wiring board in which a solder body is formed on a conductor layer that is provided and exposed through the solder resist layer, at least the following steps (1) to (2), that is, the outermost interlayer resin insulation layer, are provided. A step of forming a plating resist layer for selectively covering the conductor circuit and then performing a plating treatment to form a plating post on a portion of the conductor circuit surface where the plating resist is not formed; and after removing the plating resist layer, the conductor circuit And a solder resist layer covering the plating post is formed, and the upper end surface of the plating post is exposed from the surface of the solder resist layer. Planarizing to form a solder body on the exposed surface of the plating post, a method for manufacturing a multilayer printed wiring board comprising the city. In the manufacturing method of the above (2), after the step of, a step of forming a corrosion resistant film on the flattened exposed surface of the plating post is included, and the solder body is preferably formed on the corrosion resistant film.

Further, according to the present invention, (3) conductor circuits and interlayer resin insulation layers are alternately provided on an insulating substrate, and the outermost conductor circuit formed in the outermost interlayer resin insulation layer is selectively selected. Is provided with a solder resist layer to cover, in the production of a multilayer printed wiring board in which a solder body is formed on the land of the conductor circuit exposed from the solder resist layer, during the production process, at least the following steps ~, That is, a step of forming a plating resist layer by selectively covering the outermost conductor circuit and then performing an electroless plating treatment to form an electroless plating film on the land surface and the plating resist layer surface, the land After forming the plating resist layer on the portion excluding the electroless plating film formed at the position, the electroless plating process is performed to form the electroless layer formed at the land position. A step of forming an electrolytic plating film on the plating film, after removing the plating resist layer by etching treatment, further, by etching treatment of the electroless plating film underneath and the plating resist layer under the electroless plating film Removing, at the land position of the conductor circuit, a step of forming a plating post consisting of an electroless plating film and an electrolytic plating film, after forming a solder resist layer that covers the outermost conductor circuit and the plating post, Exposing the plating post upper surface from the solder resist layer surface, the exposed surface of the plating post as a conductor pad,
A step of forming a solder body thereon, and a method for manufacturing a multilayer printed wiring board comprising:

Further, according to the present invention, (4) conductor circuits and interlayer resin insulation layers are alternately provided on an insulating resin substrate,
A solder resist layer is provided to selectively cover the outermost conductor circuit including the filled via hole formed in the outermost interlayer resin insulation layer, and the solder body is provided on the land of the conductor circuit exposed from the solder resist layer. In manufacturing a multilayer printed wiring board formed by forming a plating resist layer that selectively covers at least the following steps, ie, the outermost conductor circuit, during the manufacturing process, electroless plating is performed. A step of forming a non-electrolytic plating film on the land surface including the via hole and the plating resist layer surface by applying a treatment, to a portion excluding the electroless plating film formed at the land position including the via hole After forming the plating resist layer, electrolytic plating treatment is performed to electrolytically plate on the electroless plating film of the land including the via hole. A step of forming a film, after removing the plating resist layer by an etching treatment, further removing the electroless plating film underneath and the plating resist layer under the electroless plating film by an etching treatment, A step of forming a plating post consisting of an electroless plating film and an electrolytic plating film on the land including the hole, after forming a solder resist layer covering the outermost conductor circuit and the plating post including the via hole, Exposing the plating post upper surface from the solder resist layer surface, the exposed surface of the plating post as a conductor pad,
And a step of forming a solder body thereon, which is a method for manufacturing a multilayer printed wiring board.

In the manufacturing methods (3) and (4), the step of exposing the upper surface of the plating post is a step of removing the surface of the solder resist layer by polishing, or the step of exposing the surface of the solder resist layer to the surface. It is desirable to include a step of providing an opening reaching the upper surface of the plating post.

In the manufacturing methods (3) and (4), the method includes a step of forming a corrosion resistant film on the exposed surface of the plating post after the above steps, and the solder body is formed on the corrosion resistant film. Is desirable. The corrosion resistant film is preferably formed by a plating process, and the plating process is Au, Pt, Ag, Ni, Sn, Pd.
It is preferable that the electroless plating treatment is at least one selected from the following.

Further, according to the present invention, (5) conductor circuits and interlayer resin insulation layers are alternately provided on an insulating substrate, and the outermost conductor circuits formed in the outermost interlayer resin insulation layer are selectively selected. In manufacturing a multilayer printed wiring board in which a solder resist layer is provided, and a solder body is formed on the land of the conductor circuit exposed from the solder resist layer,
During the manufacturing process, at least the following steps, that is, after forming a plating resist layer selectively covering the outermost conductor circuit and having an opening corresponding to the land position, electroless plating treatment is performed. And a step of filling the opening with an electroless plating film, a step of removing the plating resist layer by an etching process to form a plating post made of an electroless plating film at a land position of the conductor circuit, After forming a solder resist layer covering the outermost conductor circuit and the plating post, the step of exposing the plating post upper surface from the solder resist layer surface, the exposed surface of the plating post as a conductor pad,
A step of forming a solder body thereon, and a method for manufacturing a multilayer printed wiring board comprising:

Further, according to the present invention, (6) conductive circuits and interlayer resin insulating layers are alternately provided on an insulating resin substrate,
A solder resist layer is provided to selectively cover the outermost conductor circuit including the filled via hole formed in the outermost interlayer resin insulation layer, and the solder body is provided on the land of the conductor circuit exposed from the solder resist layer. In manufacturing a multi-layer printed wiring board in which the above-mentioned is formed, at least the following steps (1) to (4) during the manufacturing process, that is, the conductor circuit selectively covering the outermost conductor circuit and including the filling via hole: After forming a plating resist layer having an opening corresponding to the land position, the step of performing electroless plating treatment, filling the electroless plating film in the opening, by removing the plating resist layer by etching treatment, Forming a plating post made of an electroless plating film on the land including the via hole, the outermost portion including the via hole After forming the solder resist layer covering the conductor circuit and plated posts, thereby exposing the plating post top from the solder resist layer surface, the exposed surface of the plating post as a conductor pad,
And a step of forming a solder body thereon, which is a method for manufacturing a multilayer printed wiring board.

In the manufacturing methods (5) and (6), the step of exposing the upper surface of the plating post is a step of removing the surface of the solder resist layer by polishing, or the step of exposing the surface of the solder resist layer to the surface. It is desirable to include a step of providing an opening reaching the upper surface of the plating post.

In addition, in the manufacturing methods of (5) and (6), the method includes a step of forming a corrosion resistant film on the exposed surface of the plating post after the above steps, and the solder body is formed on the corrosion resistant film. In a preferred embodiment, the corrosion resistant film is formed by electroless plating of at least one selected from Au, Pt, Ag, Ni, Sn and Pd.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION The multilayer printed wiring board of the present invention comprises:
A conductive post having a flat surface exposed from the solder resist layer is formed on the land surface of the conductor circuit formed in the outermost interlayer resin insulation layer, and the solder body is supplied to the surface of the conductive post. It is characterized by

The solder resist layer is formed so as to cover the land surface of the outermost conductor circuit provided on the substrate, and its thickness is preferably 10 to 30 μm.

The diameter of the exposed region of the conductive post exposed from the solder resist layer is 50 to 150 μm when a bump is provided on its surface, and 300 to 600 μm when a BGA or PGA is provided. Is desirable. As the bump pitch becomes finer, the diameter is preferably made smaller.

Such conductive posts are made of Cu, Sn,
It is desirable to form it by at least one kind of plating selected from Ni, Ag, Pd, Au and Pt, and as the plating, electrolytic plating or electroless plating is desirable.
In particular, it is preferably formed by electrolytic copper plating or electrolytic tin plating. The reason is that the electrical characteristics are not deteriorated and no precious metal is used, so that it is inexpensive.

Further, it is desirable that the exposed surface of the conductive post be flattened by a polishing process such as belt sander or buffing. The reason is that if the solder resist to be finally formed is applied on the conductive posts, the solder bumps are not soldered, so that it is necessary to remove the contamination on the surface of the conductive posts.

It is desirable that the surface of such a conductive post is covered with a corrosion resistant film, and the corrosion resistant film serves as a solder bump or a solder pad on which a solder body such as BGA or PGA is formed. Function.

The corrosion-resistant coating is made of Au, Ag, Pt, N
It is desirable to be formed by at least one kind of plating selected from i, Sn, and Pd, and a combination of a Ni film and an Au film by electroless plating is particularly preferable.

The thickness of such a corrosion-resistant coating is 2 to 5 μm in the case of a Ni film, and 0.01 to in the case of an Au film.
The range of 0.05 μm is desirable. The reason is that if the thickness of the corrosion resistant film is large, the cost becomes high, and if the film thickness is small, the electroless plated film of copper or the like forming the lower plating post is oxidized and the solder wettability deteriorates.

Solder bumps such as BGA, PGA, etc. formed on the corrosion resistant coating are Sn / Pb, Sn / Sb,
Sn / Ag, Sn / Ag / Cu, Sn / Cu, Sn / Z
It is desirable to be formed from at least one solder selected from n. That is, one kind selected from the above-mentioned various solders may be formed, or two or more kinds may be mixed and used.

As an example of such a solder, tin / lead solder having a composition ratio of Sn: Pb = 63: 37, and S / S
n: Pb: Ag = 62: 36: 2 tin / lead / silver solder, also Sn: Ag = 96.5: 3.5 tin /
There is silver solder etc.

The solder bumps are preferably formed by printing with a mask having a circular opening placed on the solder pads formed on the surface of the conductive posts.

As the solder for forming a solder body according to the present invention, almost all kinds of solder used in the manufacture of general printed wiring boards can be used alone or in combination.

The height of the solder bumps is preferably in the range of 5 to 50 μm, and the height and shape can be made uniform.

Finally, the solder bumps are subjected to a reflow process and hardened. The reflow condition is that the temperature is 100 to 300 ° C. using an inert gas such as nitrogen. The reflow temperature sets an optimum temperature profile according to the melting point of the solder used.

All of the solder bumps formed by the reflow process are substantially hemispherical, and the height thereof is 5 to 5.
The solder resist layer is uniformly formed in the range of 0 μm, and the solder resist layer is not contaminated by the solder paste.

Next, an example of a method for manufacturing a printed wiring board according to the present invention will be described. That is, a conductor circuit and an interlayer resin insulation layer are alternately provided on an insulating substrate, and a solder resist layer is provided to selectively cover the outermost conductor circuit formed in the outermost interlayer resin insulation layer, A multilayer printed wiring board in which a solder body is formed on the land of the conductor circuit exposed from the solder resist layer is manufactured through at least the following steps (1) to (3).

(1) After forming a plating resist layer for selectively covering the conductor circuit provided on the outermost interlayer resin insulation layer, a plating process is performed to form a conductive post on the surface of the conductor circuit where the plating resist is not formed. (2) after peeling the plating resist layer, forming a solder resist layer that covers the conductor circuit and the plating post, and further exposing the upper end surface of the conductive post from the solder resist layer surface (3) A step of forming a solder body on the exposed surface of the conductive post.

According to the method for manufacturing a multilayer printed wiring board of the present invention comprising the above steps (1) to (3), conductive posts are formed on the land surface of the outermost conductor circuit by plating, and then the conductive posts are formed. The step of forming a solder resist layer to cover the conductive posts is provided as an essential constituent feature, and such a structure can improve the adhesion between the conductive post made of plating and the solder resist layer. it can.

In the step (1), the outermost conductor circuit pattern is an electroless plating film formed by electroless plating on the interlayer resin insulation layer formed on the outermost layer of the insulating substrate, and the electroless plating film After forming a plating resist layer on the electroplated film, it is desirable to be formed from two layers including an electroplated film formed on the electroless plated film on the non-plated resist film by electroplating (semi-additive method). .

In the formation of the conductor circuit pattern, first, a non-conductor portion is formed by disposing a plating resist layer on the electroless plating film provided on the entire surface of the roughened interlayer resin insulation layer, and the non-conductor portion is formed. After forming a conductor layer by electrolytic plating other than the portion, by dissolving and removing the plating resist layer and the electroless plating film under this plating resist,
It is desirable to obtain a conductor circuit pattern and a filled via hole that are composed of two layers, an electroless plated film and an electrolytic plated film.

In the multilayer printed wiring board according to the present invention, a plating resist layer having an opening corresponding to the land position of the outermost conductor circuit pattern and the filling via hole is formed and exposed from the opening of the plating resist layer by the plating treatment. A conductive post is formed on the surface of the formed land.

When the conductive posts are formed by a two-layer structure of electroless plating and electrolytic plating, first, electroless plating is applied to the land surface of the conductor circuit including via holes and the plating resist surface. , A thin electroless plating film is formed, and a plating resist having an opening substantially corresponding to the land position of the conductor circuit is formed on the thin electroless plating film, and then electroplating is performed. Then, it is desirable to form the electrolytic plating film on the thin electroless plating film on the land surface.

On the other hand, when the conductive posts are formed only by electroless plating, the openings of the plating resist layer are filled with electroless plating so that the land surface of the conductor circuit pattern and the filled via holes is electrolessly plated. It is desirable to form the conductive posts made of a plated film.

Such conductive posts are made of Cu, Sn,
It is preferably formed by electrolytic plating or electroless plating composed of at least one selected from Ni, Ag, Pd, Au and Pt, and particularly preferably formed by electrolytic copper plating or electrolytic tin plating.

In the step (2), when the conductive posts are formed by a two-layer structure of electroless plating and electrolytic plating, first, the upper plating resist layer is removed by etching treatment, and then, By removing the underlying electroless plating film and the underlying plating resist layer underneath the electroless plating film by etching, the electroless plating film and the electrolytic plating film are formed on the land including the filled via hole surface. It is desirable that a conductive post consisting of is formed.

When the conductive posts are formed only by electroless plating, the plating resist layer is removed by etching so that the conductive post formed of electroless plated film on the land including the filled via hole surface. It is desirable that posts be formed.

Next, a conductive resist formed on the surface of the land is covered to form a solder resist layer, and then the surface of the solder resist layer is ground by mechanical polishing such as belt sander or buff grinding. Processing is performed so that the upper end surface is exposed from the surface of the solder resist layer to be planarized, or an opening is formed in the solder resist layer by a photolithography method, and the surface of the conductive post is exposed from the opening.

In the step (3), the surface of the conductive post is covered with a corrosion resistant film before the solder body is formed on the surface of the conductive post, and the surface of the corrosion resistant film is covered with solder bumps, BGA, or PGA. It is desirable to form a solder body such as.

The corrosion-resistant coating is made of Au, Ag, Pt, N
It is desirable to be formed by at least one kind of plating selected from i, Sn, and Pd, and a combination of a Ni film and an Au film by electroless plating is particularly preferable.

Solder bumps such as BGA and PGA formed on the corrosion-resistant coating are Sn / Pb, Sn / Sb,
Sn / Ag, Sn / Ag / Cu, Sn / Cu, Sn / Z
It is desirable to be formed from at least one solder selected from n. That is, one kind selected from the above-mentioned various solders may be formed, or two or more kinds may be mixed and used.

As the solder for forming a solder body according to the present invention, almost all kinds of solder used in the manufacture of general printed wiring boards can be used alone or in combination.

In the multilayer printed wiring board of the present invention, conductor circuits are provided on both surfaces of the substrate, conductive posts are formed on the land surfaces of the conductor circuits provided on both surfaces, and the conductive posts are formed on the upper surfaces of the conductive posts. Solder bump, BGA or P
Not only the embodiment in which a solder body such as GA is formed, but the conductive post is formed only on the land surface of one conductor circuit and the conductive post is not formed on the land surface of the other conductor circuit. It also applies to the form.

[0052]

(Example) (Example 1) (1) 0.8 mm thick glass epoxy resin (FR4, FR5),
Alternatively, a copper clad laminate obtained by laminating a copper foil 2 having a thickness of 18 μm on both surfaces of a substrate 1 made of BT (bismaleimide-triazine) resin was used as a starting material (see FIG. 1 (a)).
First, the copper clad laminate was drilled and the inner wall surface was treated with a modifier consisting of organometallic sodium to improve the wettability of the surface (see FIG. 1 (b)).

(2) Next, a palladium-tin colloid was attached and electroless plating was performed with the following composition to form a 2 μm electroless copper plating film on the entire surface of the substrate. [Aqueous electroless plating solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 ° C 30 minutes at liquid temperature

Further, electrolytic copper plating was performed under the following conditions to form an electrolytic copper plating film having a thickness of 15 μm (see FIG. 1).
(See (c)). [Electrolytic plating aqueous solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (manufactured by Atotech Japan, trade name: Kaparaside GL) 1 ml / l [Electrolytic plating conditions] Current density 1 A / dm ² hours 30 minutes Temperature room temperature

(3) The substrate 1 having a conductor layer (including the through holes 3) formed of an electroless copper plating film and an electrolytic copper plating film on the entire surface is washed with water and dried, and then a cupric complex and an organic acid are added. The roughening layer 4 is formed on the entire surface of the conductor layer including the through holes 3 by applying an etching solution containing and to act under oxygen coexisting conditions such as spraying and bubbling to dissolve copper in the conductor layer to form voids. Is provided (see FIG. 1 (d)).

In addition to such a roughening treatment by etching, a roughening layer may be provided by an oxidation-reduction treatment or an electroless plating alloy, and the roughening layer formed is from 0.1 to 5
Those in the range of μm are desirable. Within that range,
This is because the conductor circuit pattern and the interlayer resin insulation layer are less likely to be peeled off, and are less likely to remain even if the metal layer is removed by etching.

The cupric complex is preferably a cupric complex of an azole, and acts as an oxidizing agent for oxidizing metallic copper or the like. As the azoles, diazole, triazole and tetrazole are preferable. Among them, imidazole, 2-
Methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-undecylimidazole and the like are preferable. The addition amount of the cupric complex of azoles is preferably 1 to 15% by weight. This is because it has excellent solubility and stability.

In order to dissolve copper oxide, an organic acid is added to the cupric complex of azoles. Specific examples of the organic acid include formic acid, acetic acid, propionic acid, butyric acid, valeric acid,
Caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid,
At least one selected from the group consisting of glycolic acid, lactic acid, malic acid, and sulfamic acid is preferable. The content of the organic acid is preferably 0.1 to 30% by weight. This is for maintaining the solubility of the oxidized copper and ensuring the dissolution stability. The generated cuprous complex is dissolved by the action of an acid, combines with oxygen to form a cupric complex, and contributes again to the oxidation of copper.

Further, in order to assist the dissolution of copper and the oxidizing action of azoles, halogen ions such as fluorine ions, chlorine ions, bromine ions may be added to the etching solution. In the present invention, halogen ions can be supplied by adding hydrochloric acid, sodium chloride or the like. The amount of halogen ions is preferably 0.01 to 20% by weight. This is because the formed roughened surface and the interlayer resin insulation layer have excellent adhesion.

The cupric complex of the azole and the organic acid (halogen ion if necessary) are dissolved in water to prepare an etching solution. In addition, a commercially available etching solution, for example,
It is also possible to form a roughened surface by using a product name “Mec Etch Bond” manufactured by Mec Co., Ltd.

(4) Next, a resin filler 5 prepared by mixing the following resin composition and curing agent composition,
The through holes 3 were filled by screen printing and dried in a drying oven at a temperature of 100 ° C. for 20 minutes.

[Resin composition] Bisphenol F type epoxy monomer (Made by Yuka Shell, molecular weight 310, YL983U) 10
0 parts by weight, SiO ₂ spherical particles having an average particle diameter of 1.6 μm and coated with a silane coupling agent on the surface (manufactured by Admatech, CRS 1101-CE, where the maximum particle size is
The thickness (15 μm) or less of the inner layer copper pattern described later)
170 parts by weight and 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) were mixed by stirring to adjust the viscosity of the mixture at 23 ± 1 ° C. to 36,000 to 49,000 cps. [Curing agent composition] Imidazole curing agent (manufactured by Shikoku Kasei,
2E4MZ-CN) 6.5 parts by weight.

(5) Then, the filler 5 protruding from the roughening layer 4 and the through hole 3 on the upper surface of the conductor layer is removed by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.). Buffing was performed to remove scratches caused by the belt sander polishing to flatten the substrate surface. After such a series of polishing was similarly performed on the other surface of the substrate, heat treatment was performed at 100 ° C. for 1 hour and at 150 ° C. for 1 hour to completely cure the resin filler. It should be noted that while the polishing is performed in a semi-cured state, it may be performed after the curing is completed. (See Fig. 1 (e)).

The above resin filler is preferably composed of metal particles, a thermosetting resin and a curing agent, or preferably composed of metal particles and a thermoplastic resin, and a solvent may be added if necessary. When such a filler contains metal particles, the metal particles are exposed by polishing the surface, and the filler is integrated with the plating film of the conductor layer formed on the exposed metal particles. PCT
Even under severe high temperature and high humidity conditions such as (pressure cooker test), peeling is less likely to occur at the interface with the conductor layer. Further, since this filling material is filled in the through hole having the metal film formed on the wall surface, migration of metal ions does not occur.

Copper, gold, silver, aluminum, nickel, titanium, chromium, tin / lead, palladium, platinum and the like can be used as the metal particles. The particle size of the metal particles is preferably 0.1 to 50 μm. The reason for this is 0.1 μm
When it is less than 50 μm, the copper surface is oxidized to deteriorate the wettability to the resin, and when it exceeds 50 μm, the printability is deteriorated.

The compounding amount of the above metal particles is based on the total amount.
30 ~ 90wt% is good. The reason is that if less than 30 wt%,
This is because the adhesion with the lid plating (the conductor layer formed to cover the exposed surface from the through hole) deteriorates, while when it exceeds 90 wt%, the printability deteriorates.

Examples of the resin used include epoxy resins such as bisphenol A type and bisphenol F type, phenol resin, polyimide resin, fluororesin such as polytetrafluoroethylene (PTFE), bismaleimide triazine (BT) resin, FEP, PFA, PPS, PEN,
PES, nylon, aramid, PEEK, PEKK, P
ET etc. can be used. As the curing agent, imidazole-based, phenol-based, amine-based curing agents and the like can be used.

Examples of the solvent include NMP (normal methylpyrrolidone), DMDG (diethylene glycol dimethyl ether), glycerin, water, 1- or 2- or 3-cyclohexanol, cyclohexanone, methylcellosolve, methylcellosolve acetate, methanol, ethanol, butanol. , Propanol, etc. can be used.

In particular, the optimum composition of this filler is a mixture of Cu powder in a weight ratio of 6: 4 to 9: 1 and a bisphenol F type solventless epoxy (made by Yuka Shell, trade name: E-807). And hardener combination, or Cu in a weight ratio of 8: 2: 3
A combination of flour, PPS and NMP is preferred. The filler is preferably non-conductive. This is because the non-conductive material has a smaller curing shrinkage and is less likely to be separated from the conductor layer or the via hole.

(6) A palladium catalyst (manufactured by Atotech Co., Ltd.) is applied to the surface of the substrate flattened in (5) above, and electroless copper plating is performed according to a conventional method to obtain electroless copper plating having a thickness of 0.6 μm. A film 6 was formed (see FIG. 1 (f)). Instead of the electroless copper plating film, it is possible to form a copper or nickel film by sputtering.

(7) Next, electrolytic copper plating is performed under the following conditions to form an electrolytic copper plating film 7 having a thickness of 15 μm, and the filling material 5 filled in the inner layer conductor circuit portion and the through hole 3 is filled. The portion to be the covering conductor layer for covering the through holes was thickened. [Electrolytic plating aqueous solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (manufactured by Atotech Japan, trade name: Kaparaside GL) 1 ml / l [Electrolytic plating conditions] Current density 1 A / dm ² hours 30 minutes Temperature room temperature

(8) Commercially available photosensitive dry films are attached to both surfaces of the substrate on which the inner conductor circuit and the portion to be the through-hole covering conductor layer are formed, masked, and
The resist was exposed at 0 mJ / cm ² and developed with 0.8% sodium carbonate to form an etching resist 8 having a thickness of 20 μm (see FIG. 2 (a)).

(9) Then, the plating film in the portion where the etching resist 8 is not formed is dissolved and removed by etching using a mixed solution of sulfuric acid and hydrogen peroxide, and the etching resist 8 is removed with NaOH, KOH or the like. It was peeled and removed with an alkaline solution to form a through-hole-covered conductor layer 10 (hereinafter referred to as a "lid plating layer") that covers the conductor circuit 9 and the filler 5 which are independent layers (see FIG. 2 (b)). .

(10) [Preparation of resin filler] 100 parts by weight of bisphenol F type epoxy monomer (Made by Yuka Shell, molecular weight 310, YL983U), coated with silane coupling agent on the surface
O ₂ spherical particles (manufactured by Admatech, CRS 1101-CE, where
The maximum particle size is 170 parts by weight or less and the leveling agent (manufactured by San Nopco, Perenol S4) 1.5 parts by weight is kneaded with a three-roll mill, and the viscosity of the mixture is 23 ±. It was adjusted to 45,000 to 49,000 cps at 1 ° C.

.. Imidazole hardener (Shikoku Kasei, 2E
4MZ-CN) 6.5 parts by weight. These are mixed to prepare the in-layer resin insulation material 12, and the prepared interlayer resin insulation material 12 is applied to one surface of the substrate by screen printing, whereby gaps between the conductor circuit patterns 9 and conductor circuit patterns 9 are formed. 9 is filled in the gap between the lid plating layer 10 and dried at 70 ° C. for 20 minutes. Similarly, on the other surface, the resin filler 12 is similarly filled in the gap between the conductor circuit patterns 9 and the conductor circuit pattern 9. Fill the gap between the lid and the plating layer at 70 ℃, 2
It was dried in 0 minutes. That is, in this step, the interlayer resin insulation material 12 is filled in the recesses between the inner layer copper patterns composed of the inner conductor circuit patterns 9 and the lid plating layer 10.

(11) One side of the substrate which has been subjected to the treatment of (10) above is subjected to belt sander polishing using # 400 belt polishing paper (manufactured by Sankyo Rikagaku) to remove an interlayer resin insulating material on the surface of the inner layer copper pattern. Polishing was performed so as not to remain, and then buffing was performed to remove scratches due to the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate.

In this way, the interlayer resin insulation material 1 filled between the conductor circuit patterns 9 or the lid plating layer 10 is formed.
2 and the roughening layer 11 on the conductor circuit pattern 9 or on the upper surface of the lid plating layer 10 is removed to smooth both surfaces of the substrate, and the interlayer resin insulating material 12 and the side surface of the conductor circuit pattern 9 or the lid plating layer 10 are roughened. A substrate was obtained which was firmly adhered via the chemical layer 11. That is, by this step, the surface of the interlayer resin insulating material 12 and the surface of the inner layer copper pattern are flush with each other.

(12) Next, the surface of the inner conductor circuit pattern 9 and the lid plating layer 10 was subjected to the same treatment as in the step (3) to form a roughened layer having a thickness of 2.5 μm (first). Figure 2
(See (c)).

(13) A semi-cured resin film, which is to be an interlayer resin insulating layer, is applied to both surfaces of the substrate subjected to the roughening treatment of (12) while heating to a temperature of 50 to 150 ° C. It is vacuum-pressed and laminated at 0.5 MPa. Alternatively, it may be formed by applying a resin whose viscosity has been adjusted in advance to a state in which it can be applied by a roll coater, a caten coater or the like. The resin film preferably contains a poorly soluble resin, soluble resin particles, a curing agent, and other components. Each will be described below.

The above resin film comprises an adhesive obtained by dispersing particles soluble in an acid or an oxidant (hereinafter referred to as soluble particles) in a resin hardly soluble in an acid or an oxidant (hereinafter referred to as a sparingly soluble resin). It is formed by pasting on a resin film.

The terms "poorly soluble" and "soluble" used in the present invention are, for the sake of convenience, those having a relatively high dissolution rate when immersed in a solution containing the same acid or oxidizing agent for the same time. For the sake of convenience, those having a relatively slow dissolution rate are referred to as "poorly soluble".

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), acid or an oxidizing agent. Examples thereof include soluble metal particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more kinds.

The shape of the soluble particles is not particularly limited,
Examples thereof include spherical shapes and crushed shapes. Further, it is desirable that the soluble particles have a uniform shape. This is because it is possible to form a roughened surface having unevenness with a uniform roughness. The average particle size of the soluble particles is 0.1 to 10
μm is desirable. Within this particle size range, two or more different particle sizes may be contained. That is, the soluble particles having an average particle size of 0.1 to 0.5 μm and the average particle size of 1
˜3 μm soluble particles and so on. As a result, a more complicated roughened surface can be formed, and the adhesion with the conductor circuit is excellent. The particle size of the soluble particles is
It is the length of the longest part of the soluble particles.

Examples of the soluble resin particles include particles made of a thermosetting resin, a thermoplastic resin, etc., which have a faster dissolution rate than the hardly soluble resin when immersed in a solution containing an acid or an oxidizing agent. It is not particularly limited as long as it is.

Specific examples of the soluble resin particles include those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyether sulfone, phenoxy resin, polyolefin resin, fluororesin, and the like. 1 may be used, or a mixture of two or more resins may be used.

As the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in the acid or the oxidizing agent.

That is, when the soluble resin particles are dissolved with an acid, an acid other than a strong acid can be dissolved, and when the soluble resin particles are dissolved with an oxidizing agent, a relatively strong oxidizing power is obtained. It can dissolve even weak permanganate. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid and the oxidizing agent do not remain on the resin surface, and as described later, when the catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.

Examples of the soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide, and examples of the calcium compound include calcium carbonate and
Examples include calcium hydroxide and the like, examples of the potassium compound include potassium carbonate and the like, examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

Examples of the soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples thereof include particles made of at least one selected from the group consisting of magnesium, calcium and silicon. The surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.

When two or more kinds of the above soluble particles are mixed and used, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both can ensure the insulation of the resin film because the conductivity is low, it is easy to adjust the thermal expansion with the poorly soluble resin, cracks do not occur in the interlayer resin insulation layer made of the resin film, This is because peeling does not occur between the interlayer resin insulation layer and the conductor circuit.

The sparingly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed in the interlayer resin insulating layer using an acid or an oxidizing agent. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, it may be a photosensitive resin obtained by imparting photosensitivity to these resins. By using the photosensitive resin, the via hole opening can be formed in the interlayer resin insulation layer by exposure and development.

Of these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.

Specific examples of the poorly soluble resin include epoxy resin, phenol resin, polyimide resin,
Examples thereof include polyphenylene resin, polyolefin resin, fluororesin, polyether sulfone, and phenoxy resin. These resins may be used alone or in combination of two or more. Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the roughened surface described above be formed, but also because it has excellent heat resistance, stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of a condensation product of a phenol and an aromatic aldehyde having a phenolic hydroxyl group,
Examples thereof include triglycidyl isocyanurate and alicyclic epoxy resin. These may be used alone or in combination of two or more. As a result, the heat resistance is excellent.

In the resin film used for forming the interlayer resin insulation layer, it is desirable that the soluble particles are substantially uniformly dispersed in the sparingly soluble resin. It is possible to form a roughened surface having unevenness with a uniform roughness, and even if a via hole or a through hole is formed in the resin film, it is possible to secure the adhesion of the metal layer of the conductor circuit formed thereon. Because you can.

A resin film containing soluble particles may be used only in the surface layer portion forming the roughened surface. As a result, the parts other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, so that the insulating property between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the above resin film, the compounding amount of the soluble particles dispersed in the poorly soluble resin is preferably 3 to 40% by weight based on the resin film. If the content of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities, and if it exceeds 40% by weight, when the soluble particles are dissolved using an acid or an oxidizing agent. In addition, the resin film may be dissolved to a deep portion, and the insulation between the conductor circuits via the interlayer resin insulation layer made of the resin film cannot be maintained, which may cause a short circuit.

It is desirable that the resin film contains a curing agent and other components in addition to the soluble particles and the poorly soluble resin.

Examples of the above-mentioned curing agent include imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents, microencapsulations of these curing agents, triphenylphosphine,
Examples thereof include organic phosphine compounds such as tetraphenylphosphonium and tetraphenylborate.

The content of the above curing agent is preferably 0.05 to 10% by weight based on the resin film. 0.
If it is less than 05% by weight, the resin film is insufficiently cured, so that the degree of penetration of the acid or the oxidant into the resin film becomes large, and the insulating property of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive amount of the curing agent component may modify the composition of the resin, which may lead to a decrease in reliability.

Examples of the above-mentioned other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, dolomite, and the like. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By including these fillers, the coefficient of thermal expansion can be matched, the heat resistance and the chemical resistance can be improved, and the performance of the printed wiring board can be improved.

Further, the resin film may contain a solvent. Examples of the solvent include acetone,
Ketones such as methyl ethyl ketone and cyclohexanone,
Aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, xylene and the like can be mentioned. These may be used alone or in combination of two or more.

(14) Then, using a carbon dioxide gas laser, an excimer laser, a YAG laser, or a UV laser, the above (1)
60 ~ 80μ diameter for the resin film formed in 1)
A via hole forming opening (non-through hole) 13 of m is provided (see FIG. 2 (e)).

The resin film provided with the via hole forming opening 13 is cured by a thermosetting treatment to form an interlayer resin insulation layer. The via holes may be formed by area processing by laser irradiation or area processing by laser irradiation with a mask placed. Alternatively, it may be formed by processing using a mixed laser (meaning a combination of a carbon dioxide laser and an excimer laser).

(15) Next, a desmear process in the via hole formed in (14) above is performed. This desmear processing is
Chromic acid or permanganate (potassium permanganate,
(Sodium permanganate) is used to clean the inside of the non-through holes for via holes and to form a roughening layer (not shown) on the surface of the interlayer resin insulation layer including the inner walls of the non-through holes. .

(16) After applying a palladium catalyst to the surface of the interlayer resin insulation layer that has been subjected to the roughening treatment of (15) above, electroless plating is performed under the following conditions so that the roughened surface is not coated. An electrolytic copper plating film 14 is formed (see FIG. 3 (a)). [Electroless plating aqueous solution] EDTA: 150 g / l Copper sulfate: 20 g / l HCHO: 30 ml / l NaOH: 40 g / l α, α'-bipyridyl: 80 mg / l PEG: 0.1 g / l [Electroless plating condition] 30 minutes at a liquid temperature of 70 ° C

In this embodiment, the electroless copper plating film is formed as the metal film, but it is also possible to form the copper or nickel film by using sputtering. Before forming the metal layer, the surface may be subjected to plasma treatment, UV treatment, corona treatment or the like as a dry treatment to modify the surface.

(17) A commercially available photosensitive dry film is attached to both surfaces of the substrate on which the electroless plating film 14 is formed in (16) above, and a photomask film is placed on the substrate, and 100 mJ / cm 2.
² exposure, development processing with 0.8% sodium carbonate, thickness 1
A 5 μm plating resist 16 was provided (see FIG. 3 (b)).

(18) Further, electrolysis is performed under the following conditions.
Apply plating to form an electroplated film 15 with a thickness of 15 μm
Then, thicken the portion of the conductor circuit 9 and the via hole 1
7 was filled by plating (see FIG. 3 (c)). [Electrolytic plating solution] Sulfuric acid: 150 g / l Copper sulfate: 160 g / l Leveling agent: 30 ml / l (Polyoxyethylene compound) Brightener: 0.8 ml / l (Amine sulfonate compound) [Electrolytic plating conditions] Current density: 1 A / dm^Two Time: 78 min Temperature: 23 ± 2 ℃

(19) Then, the plating resist 16 is changed to Na.
After stripping and removing with an alkaline solution such as OH or KOH, the electroless plating film 14 under the plating resist is dissolved and removed by etching using a mixed solution of sulfuric acid and hydrogen peroxide, and the electroless copper plating film 14 and electrolytic copper are removed. An outer conductor circuit pattern 9 (including the filling via hole 17) having a thickness of 16 μm and including the plated film 15 was formed (see FIG. 3D).

(20) Etching (etching containing a cupric complex and an organic acid) on the via hole surface and the conductor circuit pattern surface (all surfaces including side surfaces) obtained in the step (19) above. Liquid) to form a roughened layer (not shown) on their surface.

Instead of such etching treatment, electroless plating (Cu-Ni-P) or oxidation-
The roughening layer may be formed by reduction treatment. (21) Next, the steps (13) to (18) are repeated on the substrate with the roughened surface formed thereon to perform electroplating on the electroless plated film on the second interlayer resin insulation layer 22. Then, an electrolytic plated film having a thickness of 15 μm was formed to thicken the outermost conductor circuit 19 and fill via holes 27 (see FIG. 4).

(22) A commercially available liquid resist is applied to both surfaces of the substrate obtained in (21) and dried, and then a circular pattern having a diameter of 100 μm is formed on one side of the substrate. On the other side, place a photomask film on which a circular pattern with a diameter of 400 μm is drawn, expose at 100 mJ / cm ² , develop with 0.8% sodium carbonate, and conduct on one side of the substrate. A thickness of 15 to 20 opens at a predetermined portion of the circuit pattern with a diameter of about 100 μm, and at a predetermined portion of the conductor circuit pattern on the other side of the substrate with a diameter of about 400 μm
A μm plating resist 26 was provided (see FIG. 5).

(23) Furthermore, electroless plating is performed under the following conditions to form electroless copper on the surface of the conductor circuit 19 including the via hole 27 exposed in the opening of the plating resist 26 and the surface of the plating resist. The plating film 24 is formed (see FIG. 6). [Electroless plating aqueous solution] EDTA: 150 g / l Copper sulfate: 20 g / l HCHO: 30 ml / l NaOH: 40 g / l α, α'-bipyridyl: 80 mg / l PEG: 0.1 g / l [Electroless plating condition] 30 minutes at a liquid temperature of 70 ° C

(24) A commercially available photosensitive dry film is attached to both surfaces of the substrate on which the electroless plating film 24 is formed in (23) above, and a photomask film is placed on the substrate, and 100 mJ / cm 2 is applied.
² exposure, developed with 0.8% sodium carbonate, thickness 2
A plating resist 36 of 0 μm was provided.

(25) Furthermore, electrolysis is performed under the following conditions.
Plating is applied to the plating resist opening position
15 μm thick electrolytic copper plating film 2 on the electrolytic plating film 24
5 was plated and filled (see FIG. 7). [Electrolytic plating solution] Sulfuric acid: 150 g / l Copper sulfate: 160 g / l Leveling agent: 30 ml / l (Polyoxyethylene compound) Brightener: 0.8 ml / l (Amine sulfonate compound) [Electrolytic plating conditions] Current density: 1 A / dm^Two Time: 78 min Temperature: 23 ± 2 ℃

(26) Then, the plating resist 36 is changed to Na.
After peeling and removing with an alkaline solution such as OH or KOH (see FIG. 8), the electroless plated film 24 under the plating resist is dissolved and removed by etching using a mixed solution of sulfuric acid and hydrogen peroxide, and further the plating resist 26 for NaOH and KO
Stripping and removing with an alkaline solution such as H to form a plating post 30 having a height of 16 μm consisting of the electroless copper plating film 24 and the electrolytic copper plating film 25 on the conductor circuit pattern 19 (including the filling via hole 27). (See FIG. 9).

(27) Next, 46.67 g of a photosensitizing oligomer (molecular weight 4000) obtained by acrylated 50% of epoxy groups of 60 wt% cresol novolac type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG, 15.0 g of 80 wt% bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Kasei, 2E4MZ-CN) 1.6 g, polyvalent acrylic monomer as a photosensitive monomer (Nippon Kayaku, R
604) 3 g, similarly polyvalent acrylic monomer (manufactured by Kyoeisha Chemical Co., Ltd., DPE6A) 1.5 g, dispersion type defoaming agent (manufactured by San Nopco,
S-65) 0.71 g was mixed, and further 2 g of benzophenone (manufactured by Kanto Kagaku) as a photoinitiator was added to the mixture.
0.2 Michler's ketone (Kanto Kagaku) as a photosensitizer
g to obtain a solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C.

As the solder resist layer, various resins can be used. For example, bisphenol A type epoxy resin, bisphenol A type epoxy resin acrylate,
A novolac type epoxy resin or a resin obtained by curing an acrylate of a novolac type epoxy resin with an amine-based curing agent or an imidazole curing agent can be used.

(28) On both sides of the substrate obtained in (26) above,
The solder resist composition obtained in (27) was applied so as to cover the upper surface of the plating post 30 and have a thickness of 25 μm. It may be a commercially available solder resist composition (see FIG. 10).

(29) Next, the coating film of the solder resist composition was dried at 80 ° C. for 20 minutes and at 100 ° C. for 30 minutes, and then the plating post 30 obtained in (26) above. The surface of this coating film is subjected to polishing until the surface of is exposed. Such polishing is preferably performed by belt sander or buff polishing, for example.

(30) Then, at 80 ° C. for 1 hour, 1
Heat treatment is performed under the conditions of 00 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours to form a solder resist layer 32 having a thickness of 20 μm on both surfaces of the substrate (see FIG. 11). In this state, the flat upper end surface of the polished plating post 30 is exposed on the surface of the solder resist layer 32,
The upper end surface of the plating post 30 presents a circular region having a diameter of about 100 μm on one side of the substrate and a diameter of about 400 μm on the other side of the substrate. However, in the drawing, the plating posts 30 formed on both surfaces of the substrate are shown to have substantially the same size for convenience.

(31) Thereafter, the substrate is nickel chloride 2.3 ×
10 ⁻¹ mol / l, sodium hypophosphite 2.8 × 10 ⁻¹
mol / l, sodium citrate 1.6 × 10 ⁻¹ mol / l
The electroless nickel plating solution consisting of 1 and pH = 4.5 is immersed in the electroless nickel plating solution for 20 minutes, and the upper end surface of the plating post 30 is
A nickel plating layer 40 having a thickness of 5 μm is formed, and further,
Potassium gold cyanide 7.6 x 10 ^-3 mol / l, ammonium chloride 1.9 x 10 ^-1 mol / l, sodium citrate
1.2 x 10 ^-1 mol / l, sodium hypophosphite 1.7 x
The electroless gold plating solution of 10 ⁻¹ mol / l is immersed for 7.5 minutes at 80 ° C. to form a 0.03 μm-thick gold plating layer 42 on the 5 μm-thick nickel plating layer 40. (See Figure 12).

The nickel plating layer 40 and the gold plating layer 42 constitute a corrosion-resistant plating layer for the plating post 30, and the surface of such a corrosion-resistant plating layer is a solder bump, a solder ball, a solder such as a T pin, or the like. Form a conductor pad on which the body is disposed.

Palladium, titanium, etc. may be used as the metal other than nickel, and silver, platinum, etc. may be used as the noble metal other than gold. Also,
The noble metal layer may be formed of two or more layers. The surface treatment may be dry treatment, plasma, UV, or corona treatment. This is because the filling property of the underfill can be improved.

(32) Then, the nickel-covered plating post 30 exposed from the surface of the solder resist layer 32 is formed.
On the gold layer, a solder paste having the following composition was used to form a conical surface-shaped opening (lower opening diameter 11 on the solder resist layer side).
0 μm and upper opening diameter 10 on the side filled with solder paste
5 μm) and a thickness of 40 μm is closely adhered to the surface of the solder resist layer, printing is performed using a squeegee and reflow is performed at 230 ° C., so that solder bumps are formed on the plating posts 30 on the upper surface side of the substrate. 44 to 150 μm
A multi-layer printed wiring board was manufactured in which pitches were formed and solder balls (not shown) were formed at a pitch of 1.27 mm on the surface of the nickel-gold layer on the lower surface side of the substrate via solder ( (See FIG. 13). However, in the drawing, the pitch of the solder bumps 44 and the pitch of the solder balls are drawn substantially the same for convenience.

The solder paste for forming the solder bumps 44 is Sn63 / Pb having a melting temperature of about 183 ° C.
37 solder is used, and the particle size range of the solder as the solder component is preferably 5 to 20 μm.
The range of μm is more preferable.

The viscosity (23 ° C.) of such solder is adjusted to a range of 150-350 Pa · s by the flux, and more preferably 230-290 Pa · s.
Is adjusted to the viscosity of.

Printing of the solder paste with a squeegee is performed, for example, under the following conditions. That is, an additive metal mask and a resin flat squeegee with a hardness of 80 ° at an angle of 60 ° and a solder paste viscosity of 230 Pa ·
s, squeegee speed: Print under the condition of 20 mm / sec.

Among the outermost circuit boards constituting such a multilayer circuit board, solder bumps having a height of 35 μm were formed on the plating posts 30 on the upper surface side of the board. With the electronic component placed on the outermost layer circuit board of this multilayer circuit board, reflow in an atmosphere near the melting point of the Sn / Pb solder to melt and fix the solder ball of the electronic component to the solder bump. To electrically connect the multilayer circuit board and the electronic component. Further, in the above-described embodiment, the solder ball (BGA) is provided on the conductor pad on the lower surface side of the substrate for connection with the mother board, but a T-pin for connection (PGA) may be formed instead. .

(Example 2) (1) By the same processing as (1) to (21) in Example 1 above,
Electroless plating is performed on the electroless plating film formed on the surface of the outermost interlayer resin insulation layer 22 to form an electrolytic plating film having a thickness of 15 μm, and the thickened outermost conductor circuit 19 is formed.
A substrate having the filled via hole 27 formed therein was obtained (see FIGS. 1 to 4).

(2) With the protective film 29 attached to the lower surface side of the substrate obtained in (1) above, a commercially available liquid resist is applied to the upper surface side, and after drying, the aperture is 100 μm. Place a photomask film with a circular pattern drawn on it, expose it to 100 mJ / cm ² , develop it with 0.8% sodium carbonate, and make sure that the conductor circuit pattern on the top side of the substrate has a diameter of about 100 μm. A plating resist 26 having an opening was formed.

(3) Then, (23) to (24) in Example 1 above
A thin electroless copper-plated film 24 is formed on the surface of the conductor circuit 19 including the via hole 27 exposed in the opening of the plating resist 26 and the surface of the plating resist by the same process as in (see FIG. 14).

(4) A commercially available photosensitive dry film is attached to the upper surface of the substrate on which the electroless plating film 24 is formed in (3) above, a photomask film is placed, and 100 mJ / cm 2 is applied.
² exposure, developed with 0.8% sodium carbonate, thickness 15
A plating resist 36 of μm was provided.

(5) Further, electrolysis is performed under the following conditions.
Plating is applied to the plating resist opening position
A 15 μm-thick electrolytic copper-plated film on the electrolytic-plated film 24.
25 was filled by plating (see FIG. 15). [Electrolytic plating solution] Sulfuric acid: 150 g / l Copper sulfate: 160 g / l Leveling agent: 30 ml / l (Polyoxyethylene compound) Brightener: 0.8 ml / l (Amine sulfonate compound) [Electrolytic plating conditions] Current density: 1 A / dm^Two Time: 78 min Temperature: 23 ± 2 ℃

(6) Then, the plating resist 36 is changed to Na.
Stripped and removed with an alkaline solution such as OH or KOH (Fig. 16).
Then, the electroless plating film 24 under the plating resist
Is dissolved and removed by etching using a mixed solution of sulfuric acid and hydrogen peroxide, and the plating resist 26 is further removed with NaOH or K.
Stripping and removing with an alkaline solution such as OH, a plating post 30 having a thickness of 16 μm and formed of an electroless copper plating film 24 and an electrolytic copper plating film 25 is formed on the land of the conductor circuit pattern 19 including the filling via hole 27. (See FIG. 17),
After that, the protective film 29 attached to the lower surface side of the substrate was peeled and removed.

(7) Then, a solder resist composition is obtained by the same treatment as in (27) of Example 1 above. (8) The solder resist composition obtained in the above (7) was applied to both surfaces of the substrate obtained in the above (6) so as to cover the upper surface of the plating post 30 and have a thickness of 18 μm. A commercially available solder resist composition may be used.

(9) Then, at 80 ° C. for 20 minutes, 100
After performing a drying process at 30 ° C. for 30 minutes, a 5 mm-thick photomask film having a circular pattern with a diameter of 200 μm drawn on the surface of the solder resist layer 32 on the lower surface side of the substrate is closely attached and placed at 1000 mJ. / Cm ² of UV exposure,
DMTG development processing is performed (see FIG. 18).

(10) Further, the solder resist layer 32 on the upper surface side of the substrate is polished until the surface of the plating post 30 is exposed. It is desirable to perform this polishing by, for example, belt sander or buff polishing.

(11) Then, at 80 ° C. for 1 hour, 1
Heat treatment is performed under conditions of 00 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours to form a solder resist layer 32 having a thickness of 20 μm on both sides of the substrate, and only the solder resist layer on the lower surface side of the substrate is formed. And an opening 3 with a diameter of approximately 200 μm
4 are formed (see FIG. 19).

In this state, the flat upper end surface of the plating post 30 is exposed on the surface of the solder resist layer 32 on the upper surface side of the substrate, and the upper end surface of the plating post 30 has a diameter of 100 μm. It has a circular area. However, in the drawing, the diameter of the plating post 30 and
The diameters of the openings 34 provided in the solder resist layer on the lower surface side of the substrate are shown as substantially the same size for convenience.

(12) Next, by the same treatment as in (31) of Example 1, the plating post 30 on the upper surface side of the substrate was
A corrosion resistant plating layer including a nickel plating layer 40 and a gold plating layer 42 is formed, and nickel plating is also performed on the surface of the conductor circuit 19 including the via hole 27 exposed in the opening 34 of the solder resist layer 32 on the lower surface side of the substrate. A corrosion-resistant plating layer including the layer 40 and the gold plating layer 42 is formed (see FIG. 20).

(13) Further, the same process as (32) in Example 1 was performed to obtain the solder resist layer 32 on the upper surface side of the substrate.
Nickel covering the plating post 30 exposed on the surface of the
Solder bumps 44 (solder bodies) are formed on the gold layer, and solder balls (shown in the figure) are formed on the nickel-gold layer exposed in the openings 34 of the solder resist layer 32 on the lower surface of the substrate via solder. Was omitted) was manufactured (see FIG. 21).

(Embodiment 3) (1) The same processes as (1) to (28) in the above-mentioned Embodiment 1 are carried out,
A solder resist composition having a thickness of 18 μm was applied to both surfaces of the substrate, covering the upper surfaces of the plating posts 30 (see FIGS. 1 to 1).
(See FIG. 10).

(2) Then, at 80 ° C. for 20 minutes, 100
After drying for 30 minutes at ℃, the diameter is 100μm
5mm thick photomask film with a circular pattern drawn on one side of the multilayer circuit board, and 5mm thick photomask film with a circular pattern of 400μm drawn on the other side of the multilayer circuit board And place it at 1000
It is exposed to ultraviolet rays of mJ / cm ² and subjected to DMTG development processing.

(3) Then, at 80 ° C. for 1 hour, 10
The heat treatment is performed under the conditions of 0 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours, and an opening 46 having a diameter of about 100 μm is formed on one side of the multilayer circuit board and the other side of the multilayer circuit board. A solder resist layer (thickness 20 μm) having an opening 48 having a diameter of approximately 400 μm is formed on each side (see FIG. 22). That is, the upper surfaces of the plating posts 30 provided on both surfaces of the substrate are exposed in the openings 46 and 48 provided in the solder resist layer 32.

(4) Then, according to the process of (31) of the above-mentioned Example 1, the nickel layer 40 and the gold layer 42 are covered with the upper surface of the plating post 30 exposed in the openings 46 and 48 of the solder resist layer 32. Formed (see FIG. 23).

(5) Further, the same treatment as in (32) of Example 1 was performed to form 150 μm of solder bumps 44 on the nickel-gold layer formed on the plating posts 30 on the upper surface side of the substrate.
Solder balls (not shown) are formed at a pitch of 1.27 mm on the surface of the nickel-gold layer formed on the plating posts 30 on the lower surface side of the substrate through the solder.
To produce a multilayer printed wiring board (FIG. 24).
reference).

(Embodiment 4) (1) By the same processing as (1) to (21) of the above Embodiment 1,
An electrolytic plating film having a thickness of 15 μm was formed on the electroless plating film formed on the surface of the outermost interlayer resin insulation layer 22, and the thickened outermost conductor circuit 19 and filling via hole 27 were formed. A substrate was obtained (see FIGS. 1 to 4).

(2) Next, a commercially available liquid resist is applied on both sides of the substrate obtained in (1) above and dried, and then a circular pattern having a diameter of 100 μm is formed on one side of the substrate. On the other side of the substrate, place a photomask film on which a circular pattern with a diameter of 400 μm is drawn, expose it at 100 mJ / cm ² , develop with 0.8% sodium carbonate, and one side of the substrate. In the land of the conductor circuit pattern at about 100 μm, and at the land of the conductor circuit pattern on the other side of the substrate at about 400 μm in diameter, the thickness is 15 to 20 μm.
m plating resist 53 was provided.

(3) Further, electroless plating was performed under the following conditions to fill and form an electroless copper plating film 55 with a thickness of 16 μm in the opening 54 of the plating resist 53 (see FIG. 25). . [Aqueous electroless plating solution] EDTA: 150 g / l Copper sulfate: 20 g / l HCHO: 30 ml / l NaOH: 40 g / l Reaction stabilizer: 50 mg / l [Electroless plating conditions] 75 minutes at 70 ° C. liquid temperature

(4) Next, the plating resist 53 is replaced with Na.
After peeling and removing with an alkaline solution such as OH or KOH, a plating post 30 having a thickness of 16 μm and made of an electroless copper plating film 55 was formed on the upper surface side and the lower surface side of the substrate (see FIG. 26).

(5) Further, (27) to (32) of Example 1 above.
Perform the same process as the above to perform plating post 30 on the upper surface side of the substrate.
Solder bumps 44 are formed on the upper surface at a pitch of 150 μm, and solder balls are formed on the surface of the nickel-gold layer on the lower surface of the substrate at a pitch of 1.27 mm via solder (not shown).
To produce a multilayer printed wiring board (FIG. 27).
~ 29).

(Embodiment 5) (1) The same processes as (1) to (4) in Embodiment 4 are performed,
On the upper surface side and the lower surface side of the substrate, the plating posts 30 made of the electroless copper plating film 55 and having a thickness of 16 μm were formed.

(2) Next, a solder resist composition is obtained by the same treatment as in (27) of Example 1 above. (3) The solder resist composition obtained in (2) above was applied to both surfaces of the substrate obtained in (1) above so as to cover the upper surface of the plating post 30 and have a thickness of 18 μm. A commercially available solder resist composition may be used.

(4) Next, at 80 ° C. for 20 minutes, 100 ° C.
After performing a drying process for 30 minutes, a photomask film with a thickness of 5 mm on which a circular pattern with a diameter of 100 μm is drawn is placed on one side of a multilayer circuit board and a circular pattern with a diameter of 400 μm on which a thickness of 5 mm is drawn. Place the photomask film in close contact with the other surface of the multi-layer circuit board, 1000 mJ /
It is exposed to ultraviolet rays of cm ² and subjected to DMTG development processing.

(5) Further, at 80 ° C. for 1 hour, 1
Heat treatment is performed under the conditions of 00 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours, and the diameter of the substrate is approximately 100 on the upper surface side.
A solder resist layer 32 (thickness 20 μm) having an opening 46 having a diameter of about 400 μm and an opening 48 having a diameter of about 400 μm is formed on the other side of the multilayer circuit board (see FIG. 30).

(6) Then, (31) to (32) in Example 1 above
The same process as above is performed to form the opening 4 of the solder resist layer.
On the surface of the plating post 30 exposed in 6 and 48,
A nickel plating film 40 having a thickness of 5 μm is formed, and a gold plating film 4 having a thickness of 0.03 μm is formed on the nickel plating film 40.
2 and further, solder bumps 44 are formed at a pitch of 150 μm on the surface of the nickel-gold layer on the upper surface of the substrate.
Further, a multilayer printed wiring board was manufactured by forming solder balls (not shown) at a pitch of 1.27 mm on the surface of the nickel-gold layer on the lower surface side of the substrate via solder (see FIG. 31). .

(Sixth Embodiment) (1) By the same processing as (1) to (21) in the first embodiment,
An electrolytic copper plating film having a thickness of 15 μm is formed on the electroless copper plating film formed on the surface of the outermost interlayer resin insulation layer 22, and the thickened outermost conductor circuit 19 and filling via hole 27 are formed. The formed substrate was obtained (see FIGS. 1 to 4).

(2) Next, a commercially available liquid resist is applied to both surfaces of the substrate obtained in (1) above, and after drying, a photomask film having a circular pattern with a diameter of 100 μm is drawn on the substrate. Placed on the upper surface side of 100mJ / c
After exposing with m ² and developing with 0.8% sodium carbonate, an opening (opening 54) with a diameter of about 100 μm is made in the land of the conductor circuit pattern on the upper surface side of the substrate, and all the conductor circuit patterns on the lower surface side of the substrate are exposed. A plating resist 53 having a thickness of 15 to 20 μm was provided so as to cover (see FIG. 32).

(3) Further, electroless plating was performed under the following conditions to fill and form an electroless copper plating film 55 having a thickness of 16 μm in the opening 54 of the plating resist 53 (see FIG. 33). . [Aqueous electroless plating solution] EDTA: 150 g / l Copper sulfate: 20 g / l HCHO: 30 ml / l NaOH: 40 g / l Reaction stabilizer: 50 mg / l [Electroless plating conditions] 75 minutes at a liquid temperature of 70 ° C

(4) Next, the plating resist 53 is changed to Na.
Strip and remove with an alkaline solution such as OH or KOH to obtain a thickness 16 of the electroless copper plating film 55 only on the upper surface side of the substrate.
A μm plating post 30 was formed (see FIG. 34).

(5) Further, the same processes as (2) to (6) of Example 5 were performed to form solder bumps 44 on the plating posts 30 on the upper surface of the substrate at a pitch of 150 μm.
On the surface of the nickel-gold layer on the lower surface side of the substrate, solder balls (not shown) were formed at a pitch of 1.27 mm via solder to manufacture a multilayer printed wiring board (FIGS. 36-).
37).

(Comparative Example 1) (1) By the same processing as (1) to (21) in Example 1 above,
The electroless plating film formed on the surface of the outermost interlayer resin insulation layer 22 is electroplated to form an electrolytic plating film having a thickness of 15 μm, and the thickened outermost conductor circuit 1 is formed.
A substrate having 9 and filling via holes 27 formed was obtained (see FIGS. 1 to 4).

(2) Next, a solder resist composition is obtained by the same treatment as in (27) of Example 1 above. (3) The solder resist composition obtained in (2) above was applied to both surfaces of the substrate obtained in (1) above in a thickness of 18 μm. A commercially available solder resist composition may be used.

(4) Then, at 80 ° C. for 20 minutes, 100
After drying for 30 minutes at ℃, the diameter is 100μm
Place a 5 mm thick photomask film with a circular pattern drawn on the top side of the substrate and a 5 mm thick photomask film with a 400 μm diameter circular pattern drawn on the bottom side of the substrate. , 1000 mJ / cm ² of ultraviolet light, and DMTG development treatment.

(5) Further, at 80 ° C. for 1 hour, 1
Heat treatment is performed under the conditions of 00 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours, and the diameter of the substrate is approximately 100 on the upper surface side.
A solder resist layer (thickness 20 μm) having an opening having a diameter of about 400 μm and an opening having a diameter of about 400 μm is formed on the lower surface side of the substrate.

(6) After that, the same treatment as in (31) of Example 1 above is performed to form a nickel plating layer having a thickness of 5 μm and its nickel on the land of the conductor circuit exposed from the opening of the solder resist layer. 0.03μm thickness on the plating layer
Gold plating layer is formed, and the nickel-gold layer is subjected to the same treatment as in (32) of Example 1 to form solder bumps on the upper surface of the substrate at a pitch of 150 μm, and on the lower surface of the substrate. A multi-layer printed wiring board having solder balls formed with a pitch of 1.27 mm via solder was manufactured.

With respect to the multilayer printed wiring boards of Examples 1-6 and Comparative Example 1 thus manufactured, the ratio of the bumps that were not transferred during solder paste printing (the number of untransferred bumps) was measured by an optical microscope (× 20 times). ) By
The presence or absence of air bubbles in the solder bumps formed by printing is observed by an X-ray inspection machine, and the height of the solder bumps is inspected by a laser measuring machine, and the height variation from the solder resist surface (μm) Was calculated.

In the above inspection, the untransferred rate is 1
X-rays for which the number of bumps per piece is 5000 (150 μm pitch) is inspected for 150 pieces, and if there is even one defective point in one piece, it is regarded as defective, and the number of defective pieces in 150 pieces is calculated. In the inspection, the bubble residual rate (%) was calculated with respect to 15,000 bumps of 3 pieces.

As a result, according to the multilayer printed wiring board of Example 1-6, the untransferred rate of the solder paste was 4%, the residual rate of bubbles in the solder bumps was 0.2%, and the height of the bumps was high. The variation was about 2 μm. On the other hand, in the multilayer printed wiring board of Comparative Example 1, the untransferred rate of the solder paste is 1
2.7%, the residual rate of bubbles in the solder bump is 1.5%,
The variation in height of the solder bumps was also as bad as 3.6 μm.

[0173]

As described above, according to the present invention, a solder resist layer covering the outermost conductor circuit is provided, and a substantially flat surface is formed on the pad of the conductor circuit exposed from the opening provided in the solder resist layer. Since a plating post having a surface is formed and a solder body such as a solder bump is formed on the surface of the plating post, the adhesion between the solder paste and the solder resist is reduced and the solder paste is transferred into the solder resist opening. It is possible to solve the problem of reduction in the rate, which is caused by the miniaturization of the opening diameter of the solder resist layer in the conventional technique. Therefore, the electrical connectivity and the connection reliability are also improved, and the yield of solder bump formation can be improved.

[Brief description of drawings]

1A to 1F are views showing a part of a manufacturing process of a multilayer printed wiring board manufactured according to a first embodiment of the present invention.

2 (a) to 2 (e) are views showing a part of a manufacturing process of a multilayer printed wiring board manufactured according to Example 1 of the present invention.

3 (a) to 3 (d) are views showing a part of a manufacturing process of a multilayer printed wiring board manufactured according to Example 1 of the present invention.

FIG. 4 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board manufactured according to Example 1 of the present invention.

FIG. 5 is a diagram showing part of the process of manufacturing a multilayer printed wiring board manufactured according to Example 1 of the present invention.

FIG. 6 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board manufactured according to Example 1 of the present invention.

FIG. 7 is a diagram showing part of the process of manufacturing a multilayer printed wiring board manufactured according to Example 1 of the present invention.

FIG. 8 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board manufactured according to Example 1 of the present invention.

FIG. 9 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board manufactured according to Example 1 of the present invention.

FIG. 10 is a diagram showing part of the process of manufacturing a multilayer printed wiring board manufactured according to Example 1 of the present invention.

FIG. 11 is a diagram showing part of the process of manufacturing a multilayer printed wiring board manufactured according to Example 1 of the present invention.

FIG. 12 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board manufactured according to Example 1 of the present invention.

FIG. 13 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board manufactured according to Example 1 of the present invention.

FIG. 14 is a diagram illustrating a part of the manufacturing process of the multilayer printed wiring board manufactured according to Example 2 of the present invention.

FIG. 15 is a diagram illustrating a part of the manufacturing process of the multilayer printed wiring board manufactured according to Example 2 of the present invention.

FIG. 16 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board manufactured according to Example 2 of the present invention.

FIG. 17 is a diagram illustrating a part of the manufacturing process of the multilayer printed wiring board manufactured according to Example 2 of the present invention.

FIG. 18 is a diagram showing a part of a manufacturing process of the multilayer printed wiring board manufactured according to Example 2 of the present invention.

FIG. 19 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board manufactured according to Example 2 of the present invention.

FIG. 20 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board manufactured according to Example 2 of the present invention.

FIG. 21 is a diagram showing a part of a process for manufacturing a multilayer printed wiring board manufactured according to Example 2 of the present invention.

FIG. 22 is a diagram showing a part of a process for manufacturing a multilayer printed wiring board manufactured according to Example 3 of the present invention.

FIG. 23 is a diagram illustrating a part of the manufacturing process of the multilayer printed wiring board manufactured according to Example 3 of the present invention.

FIG. 24 is a diagram illustrating a part of the manufacturing process of the multilayer printed wiring board manufactured according to Example 3 of the present invention.

FIG. 25 is a diagram illustrating a part of the manufacturing process of the multilayer printed wiring board manufactured according to Example 4 of the present invention.

FIG. 26 is a diagram showing a part of a process for manufacturing a multilayer printed wiring board manufactured according to Example 4 of the present invention.

FIG. 27 is a diagram showing a part of a process for manufacturing a multilayer printed wiring board manufactured according to Example 4 of the present invention.

FIG. 28 is a diagram showing a part of manufacturing process of the multilayer printed wiring board manufactured according to Example 4 of the present invention.

FIG. 29 is a diagram showing part of a process for manufacturing a multilayer printed wiring board manufactured according to Example 4 of the present invention.

FIG. 30 is a diagram showing part of a process for manufacturing a multilayer printed wiring board manufactured according to Example 5 of the present invention.

FIG. 31 is a diagram showing a part of manufacturing process of the multilayer printed wiring board manufactured according to Example 5 of the invention.

FIG. 32 is a diagram showing a part of a process for manufacturing a multilayer printed wiring board manufactured according to Example 6 of the present invention.

FIG. 33 is a diagram showing a part of a process for manufacturing a multilayer printed wiring board manufactured according to Example 6 of the present invention.

FIG. 34 is a diagram showing part of a process for manufacturing a multilayer printed wiring board manufactured according to Example 6 of the present invention.

FIG. 35 is a diagram showing part of a process for manufacturing a multilayer printed wiring board manufactured according to Example 6 of the present invention.

FIG. 36 is a diagram showing a part of manufacturing process of the multilayer printed wiring board manufactured according to Example 6 of the present invention.

FIG. 37 is a diagram showing part of a process for manufacturing a multilayer printed wiring board manufactured according to Example 6 of the present invention.

[Explanation of symbols]

1 substrate 2 copper foil 3 through holes 4, 11 Roughened layer 5 Through hole filling material 6, 14, 24 Electroless copper plating film 7, 15, 25 Electrolytic copper plating film 8 Etching resist 9, 19 Conductor circuit pattern 10 Lid plating layer 12, 22 Interlayer resin insulation layer 13 Opening for via hole formation 16, 26, 36 plating resist 17,27 Filled via hole 30 plating post 32 Solder resist layer 40 nickel layer 42 gold 44 Solder bump

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ identification code FI theme code (reference) C25D 7/00 C25D 7/00 J H05K 3/34 501 H05K 3/34 501F 505 505A 505C F term (reference) 4K022 AA02 AA42 BA01 BA03 BA08 BA14 BA18 BA21 BA31 BA35 BA36 CA26 CA28 DA01 EA04 4K024 AA09 AB01 AB03 AB04 AB08 AB17 BA09 BB11 FA05 5E319 AA03 AB05 AC01 AC11 AC16 AC17 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB01 BB05 BB ABB BB05 BB05 BB01 AA17 AA32 AA43 AA51 BB16 CC08 CC31 CC32 CC33 CC37 DD23 DD24 EE02 EE06 EE07 EE33 EE35 FF04 FF07 FF08 FF10 FF13 FF14 FF45 GG17 GG25 GG28 HH11 HH26 HH31

Claims (25)

[Claims] 1. A conductor circuit and an interlayer resin insulation layer are alternately provided on an insulating substrate, and a solder resist layer is formed by selectively covering the outermost conductor circuit formed on the outermost interlayer resin insulation layer. In a multilayer printed wiring board provided with a solder body on a conductor circuit surface exposed from the solder resist layer, a conductive post exposed from the solder resist layer is formed on the land surface of the outermost conductor circuit. And a solder body is supplied to the surface of the conductive post, a multilayer printed wiring board. 2. The multilayer printed wiring board according to claim 1, wherein the conductive post is formed by plating. 3. The conductive post is made of Cu, Sn, N.
The multilayer printed wiring board according to claim 2, which is formed by at least one plating selected from i, Ag, Pd, Au, and Pt. 4. The multilayer structure according to claim 1, wherein a corrosion resistant film is formed on an upper surface of the conductive post, and the solder body is formed on the corrosion resistant film. Printed wiring board. 5. The corrosion resistant film is made of Au, Pt, Ag,
The multilayer printed wiring board according to claim 4, wherein the multilayer printed wiring board is formed by at least one electroless plating selected from Ni, Sn, and Pd. 6. The multilayer printed wiring board according to claim 1, wherein the exposed surface of the conductive post is subjected to a flattening treatment by polishing. 7. A solder resist layer is formed by alternately providing conductor circuits and interlayer resin insulation layers on an insulating substrate, and selectively covering the outermost conductor circuits formed on the outermost interlayer resin insulation layer. During the manufacturing process of a multilayer printed wiring board provided with a solder body formed on the land of the conductor circuit exposed from the solder resist layer,
At least the following steps, that is, after forming a plating resist that selectively covers the outermost conductor circuit, then performing a plating process to form a conductive post on the land, the plating resist layer After peeling, a step of forming a solder resist layer that covers the outermost conductor circuit and the conductive post, and exposing the conductive post upper surface from the solder resist layer surface, the exposed surface of the conductive post is a solder pad As
And a step of forming a solder body thereon, and a method for manufacturing a multilayer printed wiring board. 8. The method according to claim 7, further comprising a step of forming a corrosion resistant film on the exposed surface of the conductive post after the step, wherein the solder body is formed on the corrosion resistant film. A method for producing the multilayer printed wiring board described. 9. The method for manufacturing a multilayer printed wiring board according to claim 8, wherein the corrosion resistant film is formed by plating. 10. The plating is Au, Pt, Ag, N
The method for manufacturing a multilayer printed wiring board according to claim 9, wherein the electroless plating is at least one selected from i, Sn, and Pd. 11. The conductive post is made of Cu, Sn, N.
The method for manufacturing a multilayer printed wiring board according to claim 7, wherein the multilayer printed wiring board is formed by plating of at least one selected from i, Ag, Pd, Au, and Pt. 12. A conductor resist layer and an interlayer resin insulation layer are alternately provided on an insulating substrate, and a solder resist layer selectively covering the outermost conductor circuit formed on the outermost interlayer resin insulation layer is provided. In manufacturing the multilayer printed wiring board in which the solder body is formed on the land of the conductor circuit exposed from the solder resist layer, during the manufacturing process,
At least the following steps, ie, after forming a plating resist layer selectively covering the outermost conductor circuit, an electroless plating treatment is performed to form an electroless plating film on the land surface and the plating resist layer surface. Forming a plating resist layer on the portion except the electroless plating film formed at the land position, then subjected to electrolytic plating treatment, on the electroless plating film formed at the land position Step of forming an electrolytic plating film, after removing the plating resist layer by etching treatment, further, by removing the plating resist layer underneath the electroless plating film and the electroless plating film by etching treatment, Forming a plating post composed of an electroless plating film and an electrolytic plating film at a land position of the conductor circuit; After forming a solder resist layer covering the conductor circuit and the plating post, the step of exposing the plating post upper surface from the solder resist layer surface, the exposed surface of the plating post as a conductor pad,
And a step of forming a solder body thereon, and a method for manufacturing a multilayer printed wiring board. 13. A conductor circuit and an interlayer resin insulation layer are alternately provided on an insulating resin substrate, and the outermost conductor circuit including a filled via hole formed in the outermost interlayer resin insulation layer is selectively formed. Is covered with a solder resist layer,
In manufacturing a multilayer printed wiring board in which a solder body is formed on a land of a conductor circuit exposed from the solder resist layer, during the manufacturing process, at least the following
Step, that is, after forming a plating resist layer that selectively covers the outermost conductor circuit, an electroless plating process is performed to form an electroless plating film on the land surface including the via holes and the plating resist layer surface. Forming a plating resist layer on a portion except the electroless plating film formed at a land position including the via hole, and then performing an electroplating process to form a land including the via hole. The step of forming an electrolytic plating film on the electroless plating film, after removing the plating resist layer by etching treatment, further, the electroless plating film below and the plating resist layer under the electroless plating film The plating formed by the electroless plating film and the electrolytic plating film is removed by the etching process and is formed on the land including the via hole. A step of forming a post, a step of forming a solder resist layer covering the outermost conductor circuit including the via hole and a plating post, and a step of exposing the plating post upper surface from the solder resist layer surface, The exposed surface as a conductor pad,
And a step of forming a solder body thereon, and a method for manufacturing a multilayer printed wiring board. 14. The step of exposing the upper surface of the plating post includes the step of removing the surface of the solder resist layer by polishing.
14. The method for manufacturing a multilayer printed wiring board according to 2 or 13. 15. The method according to claim 12, wherein the step of exposing the upper surface of the plating post includes the step of forming an opening on the surface of the solder resist layer to reach the upper surface of the plating post. Manufacturing method of multilayer printed wiring board. 16. The method according to claim 12, further comprising a step of forming a corrosion resistant film on the exposed surface of the plating post after the step, wherein the solder body is formed on the corrosion resistant film. A method for producing the multilayer printed wiring board described. 17. The method for manufacturing a multilayer printed wiring board according to claim 16, wherein the corrosion resistant film is formed by plating. 18. The plating treatment is Au, Pt, A
2. An electroless plating process comprising at least one selected from g, Ni, Sn and Pd.
7. The method for manufacturing a multilayer printed wiring board according to 7. 19. A solder resist layer, wherein conductor circuits and interlayer resin insulation layers are alternately provided on an insulating substrate, and a solder resist layer selectively covering the outermost conductor circuits formed in the outermost interlayer resin insulation layer is provided. In manufacturing the multilayer printed wiring board in which the solder body is formed on the land of the conductor circuit exposed from the solder resist layer, during the manufacturing process,
At least the following steps, that is, after forming a plating resist layer selectively covering the outermost conductor circuit and having an opening corresponding to the land position, an electroless plating process is performed to form the inside of the opening. A step of filling an electroless plating film with, a step of removing the plating resist layer by an etching process, and forming a plating post made of an electroless plating film at a land position of the conductor circuit, the outermost conductor circuit and After forming a solder resist layer covering the plating post, the step of exposing the plating post upper surface from the solder resist layer surface, the exposed surface of the plating post as a conductor pad,
And a step of forming a solder body thereon, and a method for manufacturing a multilayer printed wiring board. 20. A conductor circuit and an interlayer resin insulation layer are alternately provided on an insulating resin substrate, and the outermost conductor circuit including a filled via hole formed in the outermost interlayer resin insulation layer is selectively formed. Is covered with a solder resist layer,
In manufacturing a multilayer printed wiring board in which a solder body is formed on a land of a conductor circuit exposed from the solder resist layer, during the manufacturing process, at least the following
Step, that is, after forming a plating resist layer selectively covering the outermost conductor circuit and having an opening corresponding to the land position of the conductor circuit including the filled via hole, electroless plating treatment is performed. A step of filling the opening with an electroless plating film, a step of removing the plating resist layer by an etching process to form a plating post made of an electroless plating film on the land including the via hole, After forming a solder resist layer covering the outermost conductor circuit including the via hole and the plating post, the step of exposing the plating post upper surface from the solder resist layer surface, the exposed surface of the plating post as a conductor pad,
And a step of forming a solder body thereon, and a method for manufacturing a multilayer printed wiring board. 21. The step of exposing the upper surface of the plating post includes the step of removing the surface of the solder resist layer by polishing.
21. The method for manufacturing a multilayer printed wiring board according to 9 or 20. 22. The method according to claim 19, wherein the step of exposing the upper surface of the plating post includes the step of providing an opening on the surface of the solder resist layer to reach the upper surface of the plating post. Manufacturing method of multilayer printed wiring board. 23. The method according to claim 19, further comprising the step of forming a corrosion resistant film on the exposed surface of the plating post after the step, wherein the solder body is formed on the corrosion resistant film. A method for producing the multilayer printed wiring board described. 24. The method for manufacturing a multilayer printed wiring board according to claim 23, wherein the corrosion resistant film is formed by plating. 25. The plating treatment is Au, Pt, A
3. An electroless plating process comprising at least one selected from g, Ni, Sn and Pd.
4. The method for manufacturing a multilayer printed wiring board according to 4.