JP2017028150A - Semiconductor device - Google Patents

Abstract

Both VF and IR are small, and a high ESD tolerance is obtained. An outer peripheral groove TR having a width wider than that of a groove T is formed in the outer peripheral region R2. A thick oxide film (second insulating layer) 51C is formed from the side surface on the element region R1 side to the bottom surface on the inner surface of the outer peripheral groove TR, and the anode electrode 31 extends from the thick oxide film (second insulating layer) 51C on the element region R1 side. By setting the groove T, the breakdown voltage of the lower part of the groove T at the time of reverse bias is set to satisfy V0 <V2. That is, in the semiconductor device 10 described above, the breakdown voltage is V0, and the breakdown in this case is in the lower part of the trench T (element region R1). [Selection] Figure 1

Description

  The present invention relates to a structure of a Schottky barrier diode (SBD) that operates with a large current.

  A Schottky barrier diode (SBD) having a small forward voltage drop (VF) and capable of high-speed operation is widely used as a power semiconductor element. In SBD, a rectifying operation is performed by a Schottky junction between a semiconductor layer (n-type layer) and a barrier electrode that is in direct contact with the semiconductor layer, the barrier electrode side is an anode electrode, and the barrier metal layer on the n-type layer side is A cathode electrode is connected to the opposite side. The operating current is passed between the anode electrode and the cathode electrode.

  Further, in such SBD, it is required to reduce the reverse current (IR) at the same time as reducing VF. However, in a general Schottky junction, reducing VF and reducing IR are in a trade-off relationship. For this reason, the structure for making these compatible as SBD is proposed. As one of them, for example, Patent Document 1 discloses a structure in which a plurality of trenches (grooves) are formed in an n-type layer (originally a region where a Schottky junction is provided) immediately below a barrier electrode. A conductive polycrystalline silicon layer is formed in the trench through a thin oxide film, and this polycrystalline silicon layer is connected to the barrier electrode. For this reason, this polycrystalline silicon layer functions as a field plate controlled by the potential of the anode electrode, and this makes it easy for the depletion layer to spread in the n-type layer by this trench during reverse bias. Since an electric field is applied to this depletion layer, the electric field strength applied to the Schottky junction can be reduced by that amount, and the IR can be reduced. As a result, both VF and IR can be reduced.

Also, the SBD is required to have a high breakdown voltage during reverse bias. A breakdown at the time of reverse bias occurs by locally increasing the electric field strength at a location where the width of the depletion layer formed at the time of reverse bias becomes narrow. FIG. 3 schematically shows the shape of the depletion layer when a large reverse bias is applied in a general SBD. Here, an n-type layer (semiconductor layer) 122 that becomes a drift layer and is lightly doped is formed by epitaxial growth on the n ⁺ layer 121 having high conductivity because it becomes the substrate and highly doped n-type. FIG. 3 shows a cross section in the thickness direction.

On the n-type layer 122, a barrier metal layer 130 that makes a Schottky contact with the n-type layer 122 is formed so as to be in direct contact with the n-type layer 122. An anode electrode 131 is formed on the barrier metal layer 130, and these are combined to form one main electrode (first main electrode). On the back side of the n ⁺ layer 121, ^{the n +} layer 121 and the cathode electrode (second main electrode) 132 of ohmic contact is provided.

  In FIG. 3, when a reverse bias is applied between the anode electrode layer 131 and the cathode electrode 132, the depletion layer D is formed in the n-type layer 122 immediately below the barrier metal layer 130. The electric field is applied between the end of the depletion layer D on the n-type layer 22 side and the barrier metal layer 30. Here, the width of the depletion layer D is greatly different between the center portion and the end portion, as shown by the arrows in the figure, and is particularly narrow at the end portion. When the breakdown voltage between the anode electrode 131 and the cathode electrode 132 when the effect of the end portion is ignored is V0, the actual breakdown voltage V1 between the anode electrode 131 and the cathode electrode 132 becomes smaller than V0. For this reason, as described in Patent Document 2, for example, a structure for gently expanding the depletion layer D and increasing V1 (closer to V0) is adopted in the outer region (outer peripheral region) of the element region. .

  FIG. 4 is a cross-sectional view showing the structure of the SBD (semiconductor device 110) described in Patent Document 2, in which an element region R1 in which an operating current is actually passed and an element region for improving the breakdown voltage as described above. The structure near the boundary with the outer peripheral region R2 formed around R1 is shown. In the element region R1, the barrier metal layer 130 is in contact with the n-type layer 122, but a plurality of trenches (trench) T are formed on the surface of the n-type layer 122 in the element region R1. In FIG. 4, the extending direction of the trench T is a direction perpendicular to the paper surface, and the extending direction of each groove T is parallel. Therefore, the barrier metal layer 130 and the n-type layer 122 are in direct contact only in a region where the trench T is not formed in the element region R1.

  A thin oxide film (insulating layer) 151A is formed on the inner surface of the trench T, and a polycrystalline silicon layer (shield electrode) 152A having a high conductivity by being doped at a high concentration fills the trench T. It is formed as follows. Since the polycrystalline silicon layer 152A is formed so as to be in direct contact with the barrier metal layer 130, it functions as a field plate for controlling the surface potential of the n-type layer 122 in contact with the inner surface of the trench T by the potential of the anode electrode 131. For this reason, when anode electrode 131 is set to a large negative voltage (when SBD is reverse-biased), n-type layer 122 in contact with the inner surface of trench T is depleted. As a result, a depletion layer in the element region R1 spreads, and an electric field is applied to the depletion layer. Therefore, the electric field strength at the Schottky junction interface is reduced, and the reverse current IR can be reduced. The structure in the element region R1 is the same as that described in Patent Document 1.

  On the other hand, an outer peripheral groove TR that is sufficiently wider than the groove T is formed in the outer peripheral region R2. FIG. 4 shows a cross section in one direction (a direction perpendicular to the groove T and the outer peripheral groove TR), but the outer peripheral region R2 is formed so as to surround the element region R1 in a plan view, and the outer peripheral groove TR. Is formed so as to surround the element region R1 in which the plurality of trenches T are formed. In FIG. 4, only the structure on the element region R1 side (left side in the figure) in the outer peripheral groove TR is shown. Alternatively, since the outer peripheral trench TR reaches the end of the chip, the outer peripheral region R2 that is the entire outer region of the element region R1 is formed into a shape dug down as the outer peripheral trench TR.

  The outer peripheral groove TR and the groove T can be formed on the surface of the n-type layer 122 by the same etching process. Further, a thin oxide film (insulating layer) 151B is formed at least on the inner surface of the outer peripheral groove TR on the side close to the element region R1, and the inner surface on the element region R1 side of the outer peripheral groove TR is formed on the inner surface on the element region R1 side. As in the trench T, a polycrystalline silicon layer (shield electrode) 152B is formed. The oxide film 151B and the polycrystalline silicon layer 152B in the outer peripheral trench TR can be formed simultaneously with the oxide film 151A and the polycrystalline silicon layer 152A in the trench T, respectively. The thin oxide films 151A and 151B can be formed by thermally oxidizing the surface of the n-type layer 122 exposed at the inner surfaces of the trench T and the outer peripheral trench TR, respectively.

  Further, the barrier metal layer 130 is formed to extend from the element region R1 to the outer peripheral region R2, and is also in contact with the polycrystalline silicon layer 152B in the outer peripheral trench TR. For this reason, the potential of the polycrystalline silicon layer 152B becomes equal to that of the barrier metal layer 130 (the anode electrode 131), and a depletion layer is also formed in the n-type layer 122 around the polycrystalline silicon layer 152B at the time of reverse bias. That is, the polycrystalline silicon layers 152A and 152B similarly function as field plates.

  A thick oxide film (insulating layer) 151C is formed outside the polycrystalline silicon layer 152B in the outer peripheral trench TR. Unlike the oxide films 151A and 151B, the oxide film 151C is formed thick by a CVD method or the like. The barrier metal layer 130 extends further to the outer side (right side in the drawing) than the polycrystalline silicon layer 152B, and is formed over the thick oxide film 151C. For this reason, the barrier metal layer 130 is similar to the polycrystalline silicon layers 152A and 152B with respect to the surface potential of the n-type layer 122 immediately below the barrier metal layer 130, although the degree is smaller than the polycrystalline silicon layers 152A and 152B. Has an effect. That is, the barrier metal layer 130 on the oxide film 151C also functions as a field plate.

  Therefore, at the time of reverse bias, the depletion layer formed in the element region R1 is gently connected to the depletion layer formed at the bottom of the outer peripheral trench TR. Since the end of the depletion layer in the outer peripheral region R2 has a gentle shape due to the field plate, the breakdown voltage at the time of reverse bias can be increased. For this reason, with the structure of FIG. 4, both VF and IR can be reduced and the breakdown voltage at the time of reverse bias can be increased.

JP 2001-68688 A JP 2002-208711 A

  Although the VF and IR can both be reduced and the breakdown voltage can be increased by the above configuration, the power semiconductor element is also required to have a high electrostatic discharge (ESD) resistance. In ESD, a large reverse bias exceeding the breakdown voltage is applied in a short time, and a large reverse current flows, whereby the element is thermally destroyed. The ESD tolerance is a guideline when the element is destroyed during ESD. However, in the SBD, since current flows intensively around the guard ring during electrostatic discharge, the periphery of the guard ring is particularly susceptible to destruction due to current concentration. It was difficult to obtain a high ESD tolerance.

  That is, it was difficult to obtain an SBD having both a small VF and IR and a high ESD tolerance.

  The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.

In order to solve the above problems, the present invention has the following configurations.
The semiconductor device of the present invention includes a semiconductor layer made of n-type silicon, a first main electrode provided on the semiconductor layer and making a Schottky contact with the semiconductor layer, and an ohmic contact with the semiconductor layer A second main electrode, a plurality of grooves formed in the semiconductor layer immediately below the first main electrode, and a first main electrode connected to the first main electrode and formed on the inner surface of the groove inside the groove. A shield electrode provided via one insulating layer is a semiconductor device provided in an element region that is a region through which an operating current flows, and in an outer peripheral region provided outside the element region in plan view, An outer peripheral groove in which the semiconductor layer is dug down in an annular shape surrounding the element region in plan view is formed on the upper surface side of the semiconductor layer with a width wider than the groove, and the element inside the outer peripheral groove is formed. A second insulating layer thicker than the first insulating layer is formed from the side surface on the region side to the bottom surface, the first main electrode is formed on the second insulating layer, and the first main electrode and the second When a reverse bias exceeding the withstand voltage is applied between the main electrode and the main electrode, a current flows in the semiconductor layer immediately below the groove.
In the semiconductor device of the present invention, the first insulating layer is a silicon oxide film having a thickness in the range of 50 to 250 nm.
In the semiconductor device of the present invention, the interval between the grooves in a plan view is 2 to 4 μm.
In the semiconductor device of the present invention, the thickness of the semiconductor layer is 4 to 13 μm, and the depth of the groove is 1.0 to 2.5 μm.
In the semiconductor device of the present invention, the outer peripheral groove is formed deeper than the groove.

  Since the present invention is configured as described above, it is possible to obtain an SBD having both small VF and IR and high ESD tolerance.

It is sectional drawing of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the condition of the depletion layer in the conventional semiconductor device (a) and the semiconductor device (b) which concerns on embodiment of this invention. It is a figure which shows the condition of the depletion layer at the time of reverse bias in the conventional SBD. It is sectional drawing which shows the structure of an example of the conventional semiconductor device.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. This semiconductor device is an SBD that exhibits rectification characteristics by a Schottky junction formed between a barrier metal layer and a semiconductor layer made of silicon. In the element region of the SBD, a plurality of trenches are formed in order to reduce the reverse current IR. In the outer peripheral region of the outer periphery of the element region, an outer peripheral groove for improving the withstand voltage is formed as in the technique described in Patent Document 2. However, the structure inside the outer peripheral groove is different from the technique described in Patent Document 2.

FIG. 1 is a cross-sectional view showing the structure of the semiconductor device (SBD) 10. In this semiconductor device 10, an n-type layer (semiconductor layer) 22 which becomes a drift layer in the SBD and is doped at a low concentration on the n ⁺ layer 21 having high conductivity because it becomes a substrate and is highly doped n-type. Is formed by epitaxial growth. On the n-type layer 22, a barrier metal layer 30 that is in Schottky contact with the n-type layer 22 is formed so as to be in direct contact with the n-type layer 22 in the element region R1. As a material of the barrier metal layer 30, palladium (Pd) that forms a Schottky junction with the n-type layer 22 is used. However, since Pd is not suitable as an electrode material for flowing current, the anode electrode 31 made of aluminum (Al) or the like is thick on the barrier metal layer 30 so as to be in direct contact with the barrier metal layer 30. It is formed. For this reason, the anode electrode 31 and the barrier metal layer 30 are combined to form a main electrode (first main electrode) through which an operating current flows. A thin titanium (Ti) layer (not shown) for preventing diffusion is formed between the anode electrode 31 and the barrier metal layer 30.

On the other hand, on the back side of the ^{n +} layer 21, a cathode electrode (second main electrode) in ohmic and ^{the n +} layer 21 contact 32 is provided. Therefore, the semiconductor device 10 becomes a Schottky barrier diode (SBD) in which an operating current flows between the anode electrode 31 and the cathode electrode 32. FIG. 1 shows a structure near the boundary between the element region R1 and the outer peripheral region R2 provided on the outer side (right side). In fact, the element region R1 extends widely to the left side, At the left end, a structure similar to that of the outer peripheral region R2 in FIG. 1 is formed symmetrically with respect to FIG. In the element region R1, a plurality of grooves T are formed in parallel at equal intervals. In FIG. 1, a cross section perpendicular to the longitudinal direction of the grooves T is shown.

  A thin oxide film (first insulating layer) 51A is formed on the inner surface of the trench T, and a polycrystalline silicon layer (shield electrode) 52 having a high conductivity by being doped at a high concentration is formed in the trench T. Is formed so as to be embedded. Since the polycrystalline silicon layer 52 is formed so as to be in direct contact with the barrier metal layer 30 on the polycrystalline silicon layer 52, the polycrystalline silicon layer 52 is in contact with the inner surface of the trench T by the potential of the anode electrode 31. It functions as a field plate to control. For this reason, when a large negative voltage is applied to the anode electrode 31 (when SBD is reverse-biased), the n-type layer 22 in contact with the inner surface of the trench T is depleted. As a result, the depletion layer in the element region R1 spreads, the component applied to the depletion layer in the electric field increases, and the electric field strength at the Schottky junction interface decreases, so that the reverse current IR can be reduced. This configuration is the same as that described in Patent Documents 1 and 2 (configuration shown in FIG. 4).

  In FIG. 1, an outer peripheral groove TR having a width wider than the groove T is formed in the outer peripheral region R2. This is also the same as the technique described in Patent Document 2. However, the internal structure of the outer peripheral groove TR is different from the technique described in Patent Document 2. In this semiconductor device 10, a thick oxide film (second insulating layer) 51C is formed from the side surface to the bottom surface on the element region R1 side on the inner surface of the outer peripheral trench TR, and the anode electrode 31 extends from the thick side to the element region R1 side. doing. For this reason, the anode electrode 31 functions as a field plate similarly to the structure of FIG. However, the structure corresponding to the polycrystalline silicon layer 152B functioning as a field plate in the configuration of FIG. 4 is not formed, and only the anode electrode 31 functions as a field plate in the outer peripheral groove TR.

  Here, since the element region R1 is a region through which the operating current flows in the semiconductor device 10, the area thereof is set large in accordance with the set value of the operating current in order to ensure the operating current. On the other hand, since the outer peripheral region R2 is provided only for improving the withstand voltage and no operating current is passed, the area thereof is set small as long as the effect of improving the withstand voltage is obtained.

  FIG. 2 is a diagram schematically showing the shape of the depletion layer D at the time of reverse bias for the conventional semiconductor device 110 (a) and the semiconductor device 10 (b). As described above, in the conventional semiconductor device 110 (FIG. 2A), the depletion layer D formed in the element region R1 is connected to the depletion layer D formed immediately below the outer peripheral trench TR. It is suppressed that the depletion layer D becomes locally narrow at the end of R1. Here, although the depletion layer D immediately below the outer peripheral trench TR is thin, since an electric field is also applied to the thick oxide film 151C in this portion, the electric field applied to the depletion layer D is small. As described in Patent Document 2, since the concentration of the electric field in the depletion layer D is suppressed by this configuration, the IR can be reduced.

  In this structure, a portion where the electric field is locally increased in the depletion layer D at the time of reverse bias is not formed. As described above, the breakdown voltage in the element region R1 when the end effect is ignored is V0. In this case, when a large reverse bias is applied as in electrostatic discharge (ESD), as indicated by an arrow in the figure, a path through which a current flows in a portion immediately below the outer peripheral groove TR in the outer peripheral region R2. It becomes. The reverse bias voltage when this current flows is the withstand voltage V2 and V2> V1 (V1 << V0).

  As described above, in this case, breakdown occurs in the outer peripheral region R2, and the region where current flows in this case in a plan view is the region immediately below the outer peripheral groove TR shown in FIG. Further, in practice, since there is a slight non-uniformity in the outer peripheral groove TR and the structure inside thereof, the current actually flows through a part of this region. As described above, since the area of the outer peripheral region R2 (the area of the outer peripheral groove TR) is set small, the current density flowing in this case is eventually increased. For this reason, during ESD, the current density locally increases directly below the outer peripheral groove TR, the temperature rises locally, and this portion is easily destroyed. That is, the ESD tolerance is reduced.

  On the other hand, as shown in FIG. 2B, in the semiconductor device 10 described above, by setting the groove T, the withstand voltage at the lower part of the groove T at the time of reverse bias becomes V0 <V2 due to this. Is set. That is, in the semiconductor device 10 described above, the breakdown voltage is V0, and the breakdown in this case is in the lower part of the trench T (element region R1). Since the trench T is uniformly formed at a narrow interval in the element region R1, the current in this case flows uniformly in the element region R1 having a large area. Therefore, compared to the case of FIG. 2A, the current density flowing in this case can be reduced in the case of FIG. 2B. For this reason, ESD tolerance can be made high. That is, the trench T (element region R1) and the outer peripheral trench TR (outer peripheral region R2) are set so that V0 <V2 (V1 <V2), and the breakdown voltage of the semiconductor device 10 is set to V0. The tolerance can be increased.

  Specifically, the width of the groove T was 0.7 μm, the interval was 3 to 4 μm, and the depth was 1.3 to 1.4 μm. The thickness of the oxide film 51A in the trench T was set to 50 to 250 nm. The outer trench TR had a width of 15 μm and a depth of 1.6 μm. As a result, the current path during ESD can be the element region R1, and the ESD tolerance can be increased. Furthermore, since the effect of the groove T at the time of reverse bias is similar to the technique described in Patent Document 1, VF can be reduced. At this time, as shown in FIG. 2 (b), the shape of the depletion layer D around the trench T at the time of reverse bias is the same as the conventional one (FIG. 2 (a)). The electric field applied to the Schottky junction can be reduced, and IR can be reduced. Alternatively, the same applies when the interval between the grooves T is 2 to 4 μm and the width is 0.5 to 1.2 μm.

  Further, the thickness of the n-type layer 22 commonly used in the element region R1 and the outer peripheral region R2 is in the range of 4 to 13 μm, the depth of the trench T is in the range of 1.0 to 2.5 μm, and the ratio of the n-type layer 22 By setting the resistance in the range of 0.3 to 3.5 Ω · cm, the depletion layer extends toward the outer peripheral trench TR, and the breakdown voltage V0 in the element region R1 can be set to V0 <V2. These adjustments are preferably performed in consideration of VF and IR values.

  In the semiconductor device 10, the trench T in the element region R1 and the outer peripheral trench TR in the outer peripheral region R2 can be simultaneously formed by performing etching (for example, dry etching) on the n-type layer 22. At this time, since the width of the outer peripheral groove TR is wider than that of the groove T, the outer peripheral groove TR can be formed deeper than the groove T even when these etchings are performed at the same time. When the outer peripheral trench TR is deeper than the trench T than the shape of the depletion layer D in FIG. 2B, the shape of the depletion layer D can be made gentler from the element region R1 to the outer peripheral region R2. Such a configuration is particularly preferred, and such a configuration can be manufactured particularly easily.

  The planar shape and configuration of the element region R1, the outer peripheral region R2, the groove T, and the outer peripheral groove TR are arbitrary as long as the above-described effects are exhibited.

10, 110 Semiconductor device (SBD)
21, 121 n ⁺ layer 22, 122 n-type layer (semiconductor layer)
30, 130 Barrier metal layer (first main electrode)
31, 131 Anode electrode (first main electrode)
32, 132 Cathode electrode (second main electrode)
51A oxide film (first insulating layer)
51C oxide film (second insulating layer)
52, 152A, 152B Polycrystalline silicon layer (shield electrode)
151A, 151B, 151C Oxide film (insulating layer)
D Depletion layer R1 Element region R2 Outer peripheral region T Trench (groove)
TR outer peripheral groove

Claims (5)

a semiconductor layer composed of n-type silicon;
A first main electrode provided on the semiconductor layer and making a Schottky contact with the semiconductor layer;
A second main electrode in ohmic contact with the semiconductor layer;
A plurality of grooves formed in the semiconductor layer immediately below the first main electrode;
A shield electrode connected to the first main electrode and provided inside the groove via a first insulating layer formed on the inner surface of the groove is provided in an element region where an operating current flows. A semiconductor device,
In the outer peripheral region provided outside the element region in plan view,
An outer peripheral groove in which the semiconductor layer is dug down in an annular shape surrounding the element region in plan view is formed on the upper surface side of the semiconductor layer with a width wider than the groove,
A second insulating layer thicker than the first insulating layer is formed from the side surface to the bottom surface on the element region side in the outer peripheral groove, and the first main electrode is formed on the second insulating layer,
A semiconductor device characterized in that when a reverse bias exceeding a withstand voltage is applied between the first main electrode and the second main electrode, a current flows in the semiconductor layer immediately below the groove. .   2. The semiconductor device according to claim 1, wherein the first insulating layer is a silicon oxide film having a thickness in a range of 50 to 250 nm.   The semiconductor device according to claim 2, wherein an interval between the grooves in a plan view is 2 to 4 μm.   4. The semiconductor device according to claim 3, wherein the semiconductor layer has a thickness of 4 to 13 [mu] m, and the groove has a depth of 1.0 to 2.5 [mu] m.   The semiconductor device according to claim 1, wherein the outer peripheral groove is formed deeper than the groove.

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