JP2020088158A - Switching element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To connect a bottom region to a body region with low resistance. A switching element having a semiconductor substrate, a gate insulating film covering an inner surface of a trench, a gate electrode arranged in the trench, and a low resistance film. The semiconductor substrate has a source region, a body region, a p-type bottom region arranged below the bottom surface of the trench, an n-type drift region, and a p-type connection region. The semiconductor substrate has an active region and an inactive region. The drift region is in contact with the gate insulating film below the body region in the active region. The low resistance membrane extends along the sides of the trench within the inactive region. The connection region extends in the inactive region so as to be in contact with the low resistance film and connects the body region and the bottom region. [Selection diagram] Fig. 3

Description

The technology disclosed in this specification relates to a switching element.

The switching element disclosed in Patent Document 1 has a gate insulating film and a gate electrode arranged in the trench. The semiconductor substrate has a source region, a body region, a drift region, and a bottom region. The source region is n-type and is in contact with the gate insulating film. The body region is p-type and is in contact with the gate insulating film below the source region. The drift region is n-type and is in contact with the gate insulating film below the body region. The bottom region is p-type and is located below the bottom surface of the trench. Moreover, this switching element has a p-type connection region arranged so as to contact a part of the side surface of the trench. The connection region extends along the side surface of the trench and connects the body region and the bottom region. The connection region is provided to stabilize the potential of the bottom region.

When the switching element is turned off, the depletion layer extends from the bottom region to the surrounding drift region, thereby suppressing the electric field concentration near the bottom surface of the trench. Therefore, the switching element having the bottom region and the connection region has a high breakdown voltage.

When the switching element is turned on, a channel is formed in the body region. In the region where the drift region is arranged below the body region, the channel is connected to the drift region. Therefore, the channel connects the drift region and the source region, and a current flows between the drift region and the source region. Hereinafter, a region where the drift region is provided below the body region (that is, a region in which a current flows when the switching element is turned on) is referred to as an active region.

On the other hand, in the region where the connection region is arranged, even if a channel is formed, the channel is not connected to the drift region, and almost no current flows. Hereinafter, the region where the connection region is provided (that is, the region where almost no current flows when the switching element is turned on) is referred to as an inactive region.

JP, 2007-242852, A

The connection region has a relatively high electric resistance because it is made of a p-type semiconductor. In the switching element of Patent Document 1, in order to connect the body region and the bottom region with low resistance, it is necessary to provide the connection region in a relatively wide range. That is, it is necessary to provide the inactive region in a relatively wide area. As described above, no current flows in the inactive region when the switching element is turned on. If the inactive region is provided in a wide range, it becomes difficult to flow a current with high density in the switching element, and the switching element becomes large. Therefore, this specification proposes a technique capable of connecting the bottom region to the body region with low resistance.

A switching element disclosed in the present specification is a semiconductor substrate having a trench provided on an upper surface, a gate insulating film covering an inner surface of the trench, and the semiconductor substrate provided in the trench and having the gate insulating film. It has a low resistance film and a gate electrode insulated from. The semiconductor substrate has an n-type source region in contact with the gate insulating film, a p-type body region in contact with the gate insulating film below the source region, and a bottom surface of the trench below. It has a p-type bottom region, an n-type drift region, and a p-type connection region which are arranged. The semiconductor substrate has an active region and an inactive region. The drift region is in contact with the gate insulating film below the body region in the active region. The low resistance film has an electric resistance lower than that of the connection region, is insulated from the gate electrode, and extends from the depth of the body region along a side surface of the trench in the inactive region. It extends to the depth of the bottom region. The connection region extends so as to contact the low resistance film in the inactive region, and connects the body region and the bottom region.

In this switching element, a low resistance film extending from the depth of the body region to the depth of the bottom region along the side surface of the trench is provided in the inactive region. The connection region extends to contact the low resistance film and connects the body region and the bottom region. Since the low resistance film is provided, the electric resistance between the body region and the bottom region is reduced. Therefore, in this switching element, it is possible to connect the body region and the bottom region with low resistance without providing a wide range of the inactive region.

The top view of the switching element 10. Sectional drawing in the II-II line of FIG. Sectional drawing in the III-III line of FIG. Sectional drawing corresponding to FIG. 3 of the switching element of a 1st modification. Sectional drawing corresponding to FIG. 3 of the switching element of a 2nd modification. Sectional drawing corresponding to FIG. 3 of the switching element of a 3rd modification. Sectional drawing corresponding to FIG. 3 of the switching element of a 4th modification. Sectional drawing corresponding to FIG. 2 of the switching element of a 5th modification. The expanded sectional view of the low resistance film|membrane of the switching element of the 6th modification.

The switching element 10 of the embodiment shown in FIGS. 1 to 3 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The switching element 10 includes a semiconductor substrate 12, electrodes, insulating layers, and the like. Note that, in FIG. 1, the electrodes and the insulating layer on the upper surface 12 a of the semiconductor substrate 12 are not shown for the sake of clarity. Hereinafter, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as an x direction, a direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as ay direction, and a thickness direction of the semiconductor substrate 12 is referred to as az direction. The semiconductor substrate 12 is a SiC substrate whose main material is SiC (silicon carbide).

As shown in FIG. 1, a lattice trench 22 is provided on the upper surface 12 a of the semiconductor substrate 12. The lattice trench 22 has a plurality of trenches 22a extending in the x direction and a plurality of trenches 22b extending in the y direction. The plurality of trenches 22a are arranged at intervals in the y direction. The plurality of trenches 22b are arranged at intervals in the x direction. Each trench 22b extends so as to straddle the plurality of trenches 22a and is connected to the plurality of trenches 22a.

As shown in FIGS. 2 and 3, the inner surface of the lattice trench 22 is covered with the gate insulating film 24. A gate electrode 26 is arranged in the lattice trench 22. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. The gate electrode 26 in the trench 22a is connected to the gate electrode 26 in the trench 22b. The upper surface of the gate electrode 26 is covered with an interlayer insulating film 28.

As shown in FIGS. 2 and 3, the upper electrode 70 is arranged on the upper surface 12 a of the semiconductor substrate 12. The upper electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 at the portion where the interlayer insulating film 28 is not provided. The upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A lower electrode 72 is arranged on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is in contact with the lower surface 12b of the semiconductor substrate 12.

As shown in FIGS. 2 and 3, the semiconductor substrate 12 has a source region 30, a body region 32, a drift region 33, a drain region 34, a bottom region 36, and a connection region 38. Further, as shown in FIG. 3, a low resistance film 40 is provided inside the semiconductor substrate 12.

The source region 30 is an n-type region. As shown in FIGS. 1 to 3, the source region 30 is arranged in a range facing the upper surface 12 a of the semiconductor substrate 12, and is in ohmic contact with the upper electrode 70. As shown in FIG. 1, the source region 30 is provided along the side surface of the lattice trench 22. As shown in FIG. 2, the source region 30 is in contact with the gate insulating film 24 on the side surface of the trench 22a.

The body region 32 is a p-type region. As shown in FIGS. 1 to 3, the body region 32 has a body contact region 32a and a main body region 32b. The body contact region 32a has a higher p-type impurity concentration than the main body region 32b. The body contact region 32a is arranged in a range facing the upper surface 12a of the semiconductor substrate 12, and is in ohmic contact with the upper electrode 70. As shown in FIG. 1, the body contact region 32 a is arranged in the range surrounded by the source region 30. As shown in FIGS. 2 and 3, the main body region 32b is arranged below the source region 30 and the body contact region 32a. As shown in FIG. 2, the main body region 32b is in contact with the gate insulating film 24 on the side surface of the trench 22a. The main body region 32b is in contact with the gate insulating film 24 below the source region 30. The lower end of the main body region 32b is arranged above the lower end of the gate electrode 26.

The drift region 33 is an n-type region. As shown in FIGS. 2 and 3, the drift region 33 is arranged below the main body region 32b. As shown in FIG. 2, the drift region 33 is in contact with the gate insulating film 24 on the side surface of the trench 22a. The drift region 33 is in contact with the gate insulating film 24 below the main body region 32b. The drift region 33 is separated from the source region 30 by the body region 32.

The drain region 34 is an n-type region having a higher n-type impurity concentration than the drift region 33. As shown in FIGS. 2 and 3, the drain region 34 is arranged below the drift region 33. The drain region 34 is arranged in a range facing the lower surface 12b of the semiconductor substrate 12. The drain region 34 is in ohmic contact with the lower electrode 72.

The bottom region 36 is a p-type region. As shown in FIGS. 2 and 3, the bottom region 36 is in contact with the gate insulating film 24 on the bottom surfaces of the trenches 22a and 22b. The bottom region 36 extends in a lattice shape along the bottom surface of the lattice trench 22. The bottom region 36 is in contact with the gate insulating film 24 over the entire bottom surface of the lattice trench 22. The bottom region 36 is in contact with the drift region 33. As shown in FIG. 2, in the vicinity of the trench 22 a, the bottom region 36 is separated from the body region 32 by the drift region 33.

The broken line in FIG. 1 indicates the range in which the connection region 38 and the low resistance film 40 are provided. As shown in FIGS. 1 and 3, the connection region 38 and the low resistance film 40 are provided in a range in contact with the trench 22b. As shown in FIGS. 1 and 2, the connection region 38 and the low resistance film 40 are not provided in the range in contact with the trench 22a (excluding the intersection of the trench 22a and the trench 22b).

The low resistance film 40 is a thin film made of metal. As shown in FIG. 3, the low resistance film 40 is in contact with the gate insulating film 24 over the entire side surface of the trench 22b. That is, the low resistance film 40 is provided at the interface between the gate insulating film 24 and the semiconductor substrate 12. The low resistance film 40 is insulated from the gate electrode 26 by the gate insulating film 24. The electric resistance of the low resistance film 40 is lower than the electric resistance of the connection region 38. The low resistance film 40 extends from the upper end to the lower end of the side surface of the trench 22b. That is, the low resistance film 40 extends from the depth of the source region 30 to the depth of the bottom region 36. The lower end of the low resistance film 40 is in contact with the bottom region 36.

The connection region 38 is a p-type region. As shown in FIG. 3, the connection region 38 is in contact with the side surface of the low resistance film 40. The connection region 38 extends from the upper end to the lower end of the low resistance film 40. The connection region 38 is in contact with the source region 30, the main body region 32b, the drift region 33, and the bottom region 36. The bottom region 36 is connected to the main body region 32b by the connection region 38.

A region where the drift region 33 is in contact with the gate insulating film 24 below the main body region 32b as shown in FIG. 2 is an active region in which a current flows when the switching element 10 is turned on. In the region where the connection region 38 is arranged near the trench 22b as shown in FIG. 3 (the region where the drift region 33 is not in contact with the gate insulating film 24), almost no current flows when the switching element 10 is turned on. This is the active area.

Next, the operation of the switching element 10 will be described. When the switching element 10 is used, a higher potential than the upper electrode 70 is applied to the lower electrode 72. When a gate-on potential (potential higher than the gate threshold) is applied to the gate electrode 26, a channel (inversion layer) is formed in the p-type region (that is, the main body region 32b and the connection region 38) in the range in contact with the gate insulating film 24. It In the cross section (active region) shown in FIG. 2, when the channel is formed in the main body region 32b, the source region 30 is connected to the drift region 33 by the channel. Therefore, electrons flow from the upper electrode 70 to the lower electrode 72 via the source region 30, the channel, the drift region 33, and the drain region 34. That is, a current flows in the active region. On the other hand, in the cross section (inactive region) shown in FIG. 3, even if a channel is formed in the connection region 38, the channel is not connected to the drift region 33 because the lower end of the connection region 38 is connected to the bottom region 36. Therefore, almost no current flows in the channel formed in the inactive region. Thus, when the switching element 10 is turned on, a current mainly flows in the active region.

When the potential of the gate electrode 26 is lowered to the gate-off potential (potential equal to or lower than the gate threshold), the channel disappears and the switching element 10 turns off. When the switching element 10 is turned off, the potential of the lower electrode 72 rises. Since the drift region 33 is connected to the lower electrode 72 via the drain region 34, the potential of the drift region 33 rises as the potential of the lower electrode 72 rises. On the other hand, since the main body region 32b is connected to the upper electrode 70 via the body contact region 32a, the potential of the main body region 32b is maintained at substantially the same potential as the upper electrode 70. Therefore, a high reverse voltage is applied to the pn junction at the interface between the main body region 32b and the drift region 33. Therefore, when the switching element 10 is turned off, the depletion layer spreads from the main body region 32b to the drift region 33. The depletion layer spreading in the drift region 33 holds the potential difference between the lower electrode 72 and the upper electrode 70.

Further, the bottom region 36 is connected to the main body region 32b via the connection region 38. That is, the bottom region 36 is connected to the upper electrode 70 via the connection region 38, the main body region 32b, and the body contact region 32a. Therefore, when the switching element 10 is turned off, the bottom region 36 is maintained at substantially the same potential as the upper electrode 70. Therefore, when the switching element 10 is turned off, a high reverse voltage is also applied to the pn junction at the interface between the bottom region 36 and the drift region 33. As a result, a depletion layer spreads from the bottom region 36 to the surrounding drift region 33. The depletion layer extending from the bottom region 36 suppresses electric field concentration near the lower ends of the trenches 22a and 22b. Therefore, the switching element 10 has a high breakdown voltage.

When the switching element 10 is turned off and the potential of the lower electrode 72 rises, holes flow from the bottom region 36 to the main body region 32b. If the resistance of the path through which the holes flow from the bottom region 36 to the main body region 32b (hereinafter referred to as the connection path) is high, the holes cannot be sufficiently discharged from the bottom region 36 to the main body region 32b, and the lower electrode 72 of the lower electrode 72 cannot be discharged. The potential of the bottom region 36 rises as the potential rises. In this case, the depletion layer is unlikely to spread around the bottom region 36, and electric field concentration is likely to occur near the lower ends of the trenches 22a and 22b. On the other hand, in the switching element 10 of the embodiment, the connection path that connects the bottom region 36 and the main body region 32b is composed of the connection region 38 and the low resistance film 40. Since the electric resistance of the low resistance film 40 is extremely low, the electric resistance of the connection path is extremely low. Therefore, when the switching element 10 is turned off, the potential of the bottom region 36 is maintained at substantially the same potential as the upper electrode 70, and the rise of the potential of the bottom region 36 is prevented. As a result, the depletion layer spreads quickly around the bottom region 36, and electric field concentration near the lower ends of the trenches 22a and 22b is suppressed.

Further, as described above, when the connection path connecting the bottom region 36 and the main body region 32b includes the low resistance film 40, the electric resistance of the connection path can be made extremely low. Therefore, even if the area where the connection path is provided is reduced, it is possible to sufficiently reduce the electric resistance of the connection path, and it is possible to prevent the potential of the bottom area 36 from rising. The area where the connection path is provided is an inactive area, and is an area in which no current flows when the switching element 10 is turned on. By reducing the non-active area, it is possible to increase the active area and flow a high density current to the semiconductor substrate 12. As a result, the switching element 10 can be downsized. As described above, by providing the low resistance film 40 in the connection path, it is possible to reduce the inactive region and realize the miniaturization of the switching element 10.

In FIG. 3, the low resistance film 40 extends from the depth of the source region 30 to the depth of the bottom region 36. However, the low resistance film 40 only needs to extend at least from the depth of the main body region 32b to the depth of the bottom region 36. Further, in FIG. 3, the low resistance film 40 is arranged so as to be in contact with the side surface of the trench 22b, but as shown in FIG. 4, the low resistance film 40 is arranged along the side surface of the trench 22b at a position apart from the side surface of the trench 22b. 40 may be provided. Further, in FIG. 3, the low resistance film 40 is arranged only near the side surface of the trench 22b, but as shown in FIG. 5, the low resistance film 40 extends along the upper surface 12a of the semiconductor substrate 12 to form the upper electrode 70. It may have a contact portion. According to this configuration, the bottom region 36 can be connected to the upper electrode 70 with lower resistance. Further, in FIG. 3, the low resistance film 40 is not provided at a position in contact with the bottom surface of the trench 22b, but even if the low resistance film 40 has a portion in contact with the bottom surface of the trench 22b as shown in FIG. Good. Further, as shown in FIG. 7, the low resistance film 40 may have a portion extending along the upper surface 12a of the semiconductor substrate 12 and a portion contacting the bottom surface of the trench 22b. Although the low resistance film 40 is not provided below the trench 22a in FIG. 2, the low resistance film 40 may extend to the lower side of the trench 22a as shown in FIG. In FIG. 8, the low resistance film 40 is in contact with the bottom surface of the trench 22a and the bottom region 36 below the trench 22a. With this structure, the bottom region 36 below the trench 22a can be connected to the main body region 32b with lower resistance.

Further, in the above-described embodiments, the low resistance film 40 is made of metal (for example, Al, Ti, W, Ni), but the low resistance film 40 may be made of polysilicon or the like. Further, as shown in FIG. 9, the low resistance film 40 may be composed of a metal layer 40a and a silicide layer 40b.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in the present specification or the drawings exert technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Further, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and achieving the one object among them has technical utility.

10: switching element 12: semiconductor substrate 22: lattice trench 22a: trench 22b: trench 24: gate insulating film 26: gate electrode 28: interlayer insulating film 30: source region 32: body region 32a: body contact region 32b: main body region 33: Drift region 34: Drain region 36: Bottom region 38: Connection region 40: Low resistance film 70: Upper electrode 72: Lower electrode

Claims (1)

A switching element,
A semiconductor substrate having a trench on the upper surface,
A gate insulating film covering the inner surface of the trench;
A gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film,
Low resistance film,
Has
The semiconductor substrate is
An n-type source region in contact with the gate insulating film,
A p-type body region below the source region and in contact with the gate insulating film,
A p-type bottom region located below the bottom surface of the trench,
an n-type drift region,
p-type connection area,
Has
The semiconductor substrate has an active region and an inactive region,
The drift region is in contact with the gate insulating film below the body region in the active region,
The low resistance film has an electric resistance lower than that of the connection region, is insulated from the gate electrode, and extends from the depth of the body region along the side surface of the trench in the inactive region. Extends to the depth of the bottom area,
The connection region extends so as to contact the low resistance film in the inactive region and connects the body region and the bottom region,
Switching element.

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